PROCEEDINGS VOLUME 3508
MICROELECTRONIC MANUFACTURING | 20-24 SEPTEMBER 1998
Multilevel Interconnect Technology II
IN THIS VOLUME

0 Sessions, 25 Papers, 0 Presentations
CMP  (3)
MICROELECTRONIC MANUFACTURING
20-24 September 1998
Santa Clara, CA, United States
Dielectric Layer Process Integration
Proc. SPIE 3508, Damascene Cu-interconnect formation in benzocyclobuten (BCB) film using a novel end-point monitoring technique, 0000 (4 September 1998); doi: 10.1117/12.324023
Proc. SPIE 3508, Integration of hydrogen silsesquioxane into an advanced BiCMOS process, 0000 (4 September 1998); doi: 10.1117/12.324032
Poster Session
Proc. SPIE 3508, Effects of post-treatment for low-dielectric hydrogen silsesquioxane (HSQ), 0000 (4 September 1998); doi: 10.1117/12.324044
Dielectric Layer Process Integration
Proc. SPIE 3508, Control of the interaction of metals with fluorinated silicon oxides, 0000 (4 September 1998); doi: 10.1117/12.324045
Barrier Layer Process Integration
Proc. SPIE 3508, IMP Ta/Cu seed layer technology for high-aspect-ratio via fill by electroplating, and its application to multilevel single-damascene copper interconnects, 0000 (4 September 1998); doi: 10.1117/12.324046
Proc. SPIE 3508, Thin electroless barrier for copper films, 0000 (4 September 1998); doi: 10.1117/12.324047
Etching and Cleaning
Proc. SPIE 3508, Improved post-etch cleaning of dual-damascene system for 0.18-um technology, 0000 (4 September 1998); doi: 10.1117/12.324024
Proc. SPIE 3508, Characterization of pattern density and the metal stack composition on chlorine residues from the metal etch process, 0000 (4 September 1998); doi: 10.1117/12.324025
Proc. SPIE 3508, Post-etching polymer removal in sub-half-micron device technology, 0000 (4 September 1998); doi: 10.1117/12.324026
Proc. SPIE 3508, Titanium silicide etching in sub-half-micron device technology, 0000 (4 September 1998); doi: 10.1117/12.324027
Proc. SPIE 3508, Etching of dual-damascene oxide structures in a medium-density oxide etch reactor, 0000 (4 September 1998); doi: 10.1117/12.324028
Poster Session
Proc. SPIE 3508, Novel two-step AI CMP process for overcoming pattern geometry effects, 0000 (4 September 1998); doi: 10.1117/12.324029
CMP
Proc. SPIE 3508, Introduction to 300-mm/0.18-um to 0.13-um clean CMP system, 0000 (4 September 1998); doi: 10.1117/12.324030
Proc. SPIE 3508, Chemical mechanical polishing: future processes require CMP tool flexibility, 0000 (4 September 1998); doi: 10.1117/12.324031
Proc. SPIE 3508, Copper post-CMP cleaning process on a dry-in/dry-out tool, 0000 (4 September 1998); doi: 10.1117/12.324033
Multilevel Metal Process Integration
Proc. SPIE 3508, Novel AlCu: fill process for via applications, 0000 (4 September 1998); doi: 10.1117/12.324038
Proc. SPIE 3508, Explosive phenomenon of AlCu/TiN and W-plugs multilevel interconnect system, 0000 (4 September 1998); doi: 10.1117/12.324039
Proc. SPIE 3508, Applications of Forcefill aluminum for contact and via metallization, 0000 (4 September 1998); doi: 10.1117/12.324040
Proc. SPIE 3508, 0.50-um pitch metal integration in 0.18-um technology, 0000 (4 September 1998); doi: 10.1117/12.324041
Proc. SPIE 3508, Integration of a W-plug in an Al-based metallization scheme for 0.25-um IC technology, 0000 (4 September 1998); doi: 10.1117/12.324042
Proc. SPIE 3508, Inorganic bottom ARC SiOxNy for interconnection levels on 0.18-um technology, 0000 (4 September 1998); doi: 10.1117/12.324043
Plenary Papers
Proc. SPIE 3508, Microprocessor technology challenges through the next decade, 0000 (4 September 1998); doi: 10.1117/12.324034
Proc. SPIE 3508, Copper chip technology, 0000 (4 September 1998); doi: 10.1117/12.324035
Proc. SPIE 3508, Foundry technology trend, 0000 (4 September 1998); doi: 10.1117/12.324036
Proc. SPIE 3508, Equipment challenges for a total material system change: enabling device manufacturing at 130 nm and below, 0000 (4 September 1998); doi: 10.1117/12.324037
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