Configurable Computing: Technology and Applications

0 Sessions, 27 Papers, 0 Presentations
1-6 November 1998
Boston, MA, United States
Image Processing
Proc. SPIE 3526, Design and implementation of a high-level image processing machine using reconfigurable hardware, (8 October 1998);doi: 10.1117/12.327017
Proc. SPIE 3526, Low-cost reconfigurable DSP-based parallel image processing computer, (8 October 1998);doi: 10.1117/12.327028
Proc. SPIE 3526, Spatial and color clustering on an FPGA-based computer system, (8 October 1998);doi: 10.1117/12.327039
Proc. SPIE 3526, Computer vision application on RIPP10 configurable platform using DIPSA modular architecture, (8 October 1998);doi: 10.1117/12.327040
Proc. SPIE 3526, Design and implementation of a systolic circuit dedicated to dynamic programming algorithm parallel calculation, (8 October 1998);doi: 10.1117/12.327041
Proc. SPIE 3526, Applicability of reconfigurable computers in satellite telemetry data processing, (8 October 1998);doi: 10.1117/12.327042
Poster Session
Proc. SPIE 3526, Alternative approaches implementing high-performance FIR filters on lookup-table-based FPGAs: a comparison, (8 October 1998);doi: 10.1117/12.327043
Proc. SPIE 3526, Toward a system for automatic FPGA-based reconfigurable vision system design, (8 October 1998);doi: 10.1117/12.327044
Proc. SPIE 3526, Implementation of adaptive logic networks on an FPGA board, (8 October 1998);doi: 10.1117/12.327045
Proc. SPIE 3526, Architectural adaptation in MORPH, (8 October 1998);doi: 10.1117/12.327018
Applications Development
Proc. SPIE 3526, Spatiotemporal partitioning of computational structures onto configurable computing machines, (8 October 1998);doi: 10.1117/12.327019
Proc. SPIE 3526, Tools for mapping applications to CCMs, (8 October 1998);doi: 10.1117/12.327020
Proc. SPIE 3526, Flexible multiservice ATM network interface using reconfigurable logic devices, (8 October 1998);doi: 10.1117/12.327021
Proc. SPIE 3526, Hardware/software codesign of a fuzzy ART neural clusterer: the benefits of configurable computing, (8 October 1998);doi: 10.1117/12.327022
Proc. SPIE 3526, XBI: a Java-based interface to FPGA hardware, (8 October 1998);doi: 10.1117/12.327023
Proc. SPIE 3526, Novel single-chip evolutionary hardware design using FPGAs, (8 October 1998);doi: 10.1117/12.327024
Proc. SPIE 3526, Comparing computing machines, (8 October 1998);doi: 10.1117/12.327025
Proc. SPIE 3526, Analysis of technology trends: making a case for architectural adaptation in custom datapaths, (8 October 1998);doi: 10.1117/12.327026
Proc. SPIE 3526, Architecture of a reconfigurable system based on an embedded FPPA, (8 October 1998);doi: 10.1117/12.327027
Proc. SPIE 3526, Using the KressArray for reconfigurable computing, (8 October 1998);doi: 10.1117/12.327029
Proc. SPIE 3526, Abstract models of reconfigurable architectures for synthesis and compilation, (8 October 1998);doi: 10.1117/12.327030
DSP and Computation
Proc. SPIE 3526, Rapid implementation of mathematical and DSP algorithms in configurable computing devices, (8 October 1998);doi: 10.1117/12.327031
Proc. SPIE 3526, Minimum multiplicative complexity implementation of the 2D DCT using Xilinx FPGAs, (8 October 1998);doi: 10.1117/12.327032
Proc. SPIE 3526, Use of delayed addition techniques to accelerate integer and floating-point calculations in configurable hardware, (8 October 1998);doi: 10.1117/12.327033
Proc. SPIE 3526, FPGA-based floating-point datapath design for geometry processing, (8 October 1998);doi: 10.1117/12.327034
Proc. SPIE 3526, Dynamically programmable cache, (8 October 1998);doi: 10.1117/12.327035
Applications Development
Proc. SPIE 3526, Development environment for configurable computing, (8 October 1998);doi: 10.1117/12.327038
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