In order to characterize 300mm wafers at different stages of the IC manufacturing, a new tool based on spectroscopic ellipsometry has been recently developed at SOPRA. This new instrument called SE-300 has some important new features compared to the other ellipsometers of SOPRA or of the competition. First the optical setup allows to obtained very small measurement spots down to 35 by 45 micrometers in polychromatic light to be able to work from deep UV 190nm to near IR; second the combined monochromator/spectrometer is directly setup on the analyzer arm and allows both multichannel and scanning measurements on the same spot. Scanning measurement made with a real double monochromator including prism and grating allows very accurate measurement that can be used to extract optical indices and solve complex multilayer structures. Multichannel measurements are made through a prism/grating spectrometer with quasi-linear dispersion in wavelength. All the elements are fully compatible with the new generation of 300mm wafers. Practical results obtained on antireflective coatings and photoresist films are presented.

Improvements in the modeling of chemically amplified resist systems are necessary to extract maximum possible information form limited experimentation. Previous post- exposure bake models have neglected volume shrinkage, thus violating the continuity equations used to model the process. This work aims at describing the kinetics of the post-exposure bake process by tracking the volume shrinkage observed in both low and high activation energy resists. Both static and dynamic models are derived and corroborated with experimental results for Shipley UV5 and AZ 2549 resists. A global simulation technique is then used in conjunction with the models to extract the lithography parameters for these resists.

In semiconductor manufacturing there is a great demand for innovations towards higher cost-effectiveness. The increasing use of integrated metrology is one means to improve manufacturing processes effectively and, hence, to lower costs. Especially for the 300 mm technology, a substantial reduction of costly monitor wafers is required. Moreover, misprocessing has to be reduced by efficient feedback process control. Scatterometry can be a versatile technique for these tasks. In order to define the requirements on integrated scatterometric metrology, a cost and break-even analysis is carried out first. Several conclusions are drawn from the economic analysis to determine appropriate arrangements for scatterometric intensity measurements. The evaluation of intensity signatures measured at a fixed angle of incidence is demonstrated to be a valuable tool for the in-line characterization of critical dimensions and layer thickness.

Characterization of the geometrical parameters of microstructures in electronics and photonics is an important problem from the point of view of fabrication methods. With UV and especially electron-beam lithography feature sizes of the order of hundreds of nanometers are attainable. However, there is a lack of methods for a fast, reliable, and quantitative inspection of these structures. Scanning electron microscopy and atomic force microscopy have a good resolution but they require expensive equipment and are not suitable as on-line methods. Optical scatterometry is a nondestructive technique which predicts the structure geometry from a scattered intensity distribution. We utilize optical scatterometry with a hierarchical system of neural networks for the characterization of diffractive gratings with submicrometer features. It is shown that five geometrical parameters may be predicted simultaneously from the grating with an accuracy of less than 5 nm for the depths of the grooves and the line widths. Furthermore, the hierarchical system reduces the requirements for a prior information of the grating structure.

Optical scatterometry (OS) is a promising new technique for the in-line metrology of submicron features since it is non- invasive, rapid and highly accurate for multiparametric CD- measurements of submicon features. A serious drawback of the method is the need for relative large periodic areas to measure at. This is caused by the underlying model of plane- wave incidence. In this paper, the reduction of the measuring field to a few square microns is proposed. In this case, the diffraction of a focussed beam from a grating with a finite number of periods has to be investigated. This is done by means of rigorous modeling. One of the most essential outcomes is that, while increasing the number of covered grating periods with a wider beam, the integrated diffraction efficiency approaches very quickly the value obtained with plane wave diffraction on an infinite grating. Besides, it can be shown that both - a lateral shift as well as a moderate defocusing have negligible impact even at very small beam diameters. In addition, an effective model was developed for the efficient simulation of 2(theta) - scatterometry on FNPs.

We report about our first attempts to apply optical scatterometry to the characterization of 3D resist patterns. Particularly, nominal quarter micron dots and holes are investigated having a pitch of a half micron in both directions. The specular reflected light versus the incidence angle shows significant variance with changing exposure dose and thus with changing dot or hole diameter, respectively. Scanning electron micrographs serve as an assisting tool for the characterization of the developed resist pattern. Additionally, an algorithm for the rigorous modeling of diffraction from regular 3D-patterns is sketched. In some cases, the match between experiment and theory is already quite satisfying. This might be improved by more refined profile adaption and enhanced computer power.

The scanning electron microscope presented here allows for enhanced and selective detection of on-axis secondary electrons by a novel two-detector arrangement in combination with a beam separator. It is based on our high-resolution electron beam column. The off-axis secondary electrons are recorded by a conventional in-lens detector. The on-axis secondary electrons from the primary electrons and deflects them towards a scintillator-based detector. The detector for on-axis secondary electrons can either work in a stand-alone mode or in combination with the in-lens detector. Due to the symmetry of its deflection field, the beam separator causes no first-order chromatic aberrations to the primary beam and the spatial resolution is not deteriorated. A first experimental evaluation has demonstrated the enhanced capabilities of this system.

CMP is now the planarization method of choice in semiconductor manufacturing. However, CMP is still an immature process. Problems still exist with the uniformity and the stability of the CMP rate. These process variations stem from an incomplete understanding of the mechanism of CMP and the variation of CMP consumable s like slurry, pad and backing film. To compensate for these variations, send- ahead processing and too many measurements are usually required. Obviously, these affect CMP productivity. For better CMP productivity and accurate film thickness control, in-process monitoring is a promising solution. In this paper, a CMP tool with built-in thickness measurement is presented. Such a built-in CMP film thickness monitor must satisfy several requirements: 1) the measurements need to be made at specified chips in the wafer and at specified sites in the chip, 2) the measurements should be accurate, 3) multiple film stack measurements must be possible and 4) high-speed measurements must be possible. These four issues of the built-in film thickness monitor are discussed.

A critical aspect for the optimization of advanced CMP process development is minimizing defects. Given the complexity of the CMP process, the requirements for defect reduction are increasing. New materials, processes, and consumables lead to unanticipated defect types. In addition, comprehensive defectivity studies must involve patterned wafers since many of the process have defects and issues unique to patterned wafers. A novel defect reduction methodology is described utilizing wafer inspection tools for advanced CMP process development which has been implemented at Applied Materials. This methodology is based on a wafer inspection tools which provide classified defect counts not simply total defect count. A wafer inspection system is used in combination with a high throughput defect- review SEM (SEMVision). This combination of tools provide rapid defect classification and source identification for process development and defect elimination. The WF736 generates classification during the inspection with no loss in throughput. The SEMVision allows for further detailed analysis and classification. In addition, patterned wafers are utilized for thorough defect capture and process studies. The methodology provides critical information for improved process development and analysis, as well as enhanced time efficiency. Three applications are presented: tool and process development, defect learning for new materials, and process maintenance.

This paper details the analysis of vibration monitoring for end-point control in oxide CMP processes. Two piezoelectric accelerometers were integrated onto the backside of a stainless steel polishing steel polishing head of an IPEC 472 polisher. One sensor was placed perpendicular to the carrier plate and the other parallel to the plate. Wafers patterned with metal and coated with oxide material were polished at different speeds and pressures. Our results show that it is possible to sense a change in the vibration signal over time during planarization of oxide material on patterned wafers. The horizontal accelerometer showed more sensitivity to change in vibration amplitude compared to the vertical accelerator for a given polish condition. At low carrier and platen rotation rates, the change in vibration signal over time at fixed frequencies decreased approximately 1/2 to 1 order of magnitude. At high rotation speeds, the vibration signal remained essentially constant indicating that other factors dominated the vibration signal. These results show that while it is possible to sense changes in acceleration during polishing, more robust hardware and signal processing algorithms are required to ensure its use over a wide range of process conditions.

Optical metrology equipment has been widely used as the process qualification gauge for chemical mechanical polish and planarization (CMP) processes. However, most of the effort has concentrated on blanket-film wafers. Recent advancements in the optical metrology equipment have provided the ability to monitor both dielectric and metal CMP processes on production wafers in order to provide an in-line, real time characterization technique for performance and yield enhancement. This paper describes a methodology of using circuit features in the die as measurement sites for revealing the fundamentals of CMP. By measuring the oxide thickness on top of one or several similar circuit features and repeating the measurements through out the wafer, the oxide removal profile during CMP process can be easy plotted against the measurement sites. By carefully selecting the measurement feature, the polish removal profile at the edge of the wafers can be correlated with the results form similar test on blanket-film wafers. The results of using this technique to characterize existing CMP processes, identify the product-yield limiting factors in CMP processes, verify the improvement of a new CMP process and monitor the process variations for both dielectric and metal CMP processes have been discussed in detail. With the assistance of this measurement technique the correlation between the polish rate profiles of blanket pilot test wafers and the oxide loss profiles for production wafers can be easily identified. And, as another quantifiable result, the learning curve for process development and yield improvement can be significantly reduced.

Several techniques to predict pad failure during tungsten CMP were investigated for a specific consumable set. These techniques include blanket polish rate measurements and metrics derived from two endpoint detection schemes. Blanket polish rate decreased significantly near pad failure. Metrics from the thermal endpoint technique included change in peak temperature, change in the time to reach peak temperature, and the change in the slope of the temperature trace just prior to peak temperature all as a function of pad life. Average carrier motor current before endpoint was also investigated. Changes in these metrics were observed however these changes, excluding time to peak process temperature, were either not consistent between pads or too noisy to be reliable predictors of pad failure.

We present an overview on yield enhancement in a semiconductor manufacturing environment. We discuss about the technical and strategic aspects of this field. On the technical side we deal with yield metrics definitions and yield analysis tools. The strategic side includes the work of quantifying and prioritize yield loss issues. Communication of yield to other organizations, that will be involved in the team work for the search of root cause identification and corrective and preventative action plans, is a key to a successful and sustained yield enhancement. The importance of moving from end-of-line yield enhancement standpoint to a more in-line view is also outlined.

Current manufacturing processes require rapid, inexpensive and reliable techniques for optical inspections of machinery, products and components. Holography and holographic interferometry in spite of their attractive features are rather rarely used for industrial inspections due to relative complexity, costs, lengthy multi-stage procedures, need of dark roms and vibration insulation. Personnel skilled in optics ins also required. Thus holography is usually regarded as poorly compatible with practical industrial environment.

A development monitor system capable of highly accurate control of pattern width has been established. This system is composed of a unique monitor pattern on the process wafer, the 0th order diffraction light measuring unit, and the image analysis and process control unit. In the conventional development process in which no monitor system is employed, the CD variation in 200nm line width was about 15nm when +/- 5 percent dose error exist. However, using the new system, 1nm of CD variation was obtained. In this article, a high-sensitivity monitor pattern is proposed and its performance in controlling 200nm line and space patterns in the development process is reported.

When a collimated beam of light is reflected by an approximately flat, mirror polished object and a screen is placed in the reflected beam some distance away for the object, a 'mirror image' or Makyoh topogram of the object is formed on the screen. For objects with surface height variations, the topogram will not have a uniform intensity distribution, but even small height variations will show up strongly amplified as dark or bright patches/lines. Makyoh topography has now been used for a number of years as a sensitive tool for the inspection of mirror polished surfaces, and in particular, semiconductor wafer surfaces. The main drawbacks of conventional Makyoh topography are: 1) Ambiguity of interpretation because almost identical Makyoh topograms can result from an object with some given surface height profile and constant reflectivity, an object with constant surface height and a given non-uniform reflectivity profile, or an object with both height variations and a non- uniform reflectivity profile. 2) Lack of quantitative interpretation, for example surface height values cannot be obtained from the contrast in conventional topograms.

As the geometries of semiconductors shrink the sensitivity to metal contamination becomes more apparent. This makes the ability to detect a broad range of metals at levels form 10⁸ to 10⁹ at/cm² very important. The advent of Copper processing in many cleanrooms also raises the concern of cross-contamination and highlights the need for a fast, sensitive, and easy to use detection tool. The use of a TXRF machine in the silicon wafer fabrication area provides the ability to measure metals at levels ranging from 5E11 to 1E9 at/cm² without multiple processing steps.

We have been developing cryogenic detectors for astro- particle physics applications including search for Dark Matter, neutrino physics and x-ray astronomy. Most recently we started the development of high resolution x-ray detectors based on superconducting tunnel junctions and superconducting phase transition thermometers/transition edge sensors for microanalysis applications. Both types of sensors are being investigated as well as the cryogenic setup for applications on a scanning electron microscope.

With the increasing packaging density of electronic components in the integrated circuits (IC) as well as on the printed circuit boards the problems with heat dissipation also increase. Electronic speckle pattern interferometry (ESPI) is a rapidly developing optoelectronic method of nondestructive laser metrology supported with computer evaluations. It permits measurements of deformations in the micrometer and submicrometer ranges produced by an electrical signal, heating, mechanical stress or another load. Though these method seems very friendly for testing microelectronic components, composite materials, miniature devices, circuit boards, wafers etc., it has several drawbacks which prevent its application in real industrial environment: complexity, bulkiness and high costs of optical setups, difficulties in aligning of the optical elements. There are problems in working outside the laboratory especially due to high sensitivity of ESPI devices against environmental vibrations and daylight. We present several methods ESPI based on which a family of devices was built. Their unique properties permit to avoid all drawbacks mentioned above. These devices are extremely simple and compact. They are easily aligned and operated even by persons who are not skilled in optics. These devices are ideally suited for working outside the laboratory even by persons who are not skilled in optics. These devices are ideally suited for working outside the laboratory for example in a well-lit industrial environment. The innovative devices permit to measure deformations both in the plane of the object surface and perpendicular to it. A detailed description of the methods and devices given. Multiple examples of ESPI computer evaluations obtained in the novel devices with different small objects under test are presented. However these devices permit to work with much bigger objects if required. Our methods and devices are also suited for qualitative as well as quantitative analysis.

The plasma monitoring system HERCULES utilizes the Self Excited Electron Plasma Resonance Spectroscopy (SEERS) technique. It takes into account the non-linearity of the space charge sheath at the rf electrode, which provides harmonics with the modulated sheath width and high frequency oscillations in the bulk plasma. By using a general discharge model, SEERS provides volume averaged values of electron collision rate, electron density, and bulk power. It thus provides a very efficient real time data compression. The rf sensor head at the chamber walls is on ground potential and does not influence plasma- or process conditions. The sensor measures rf currents only, hence, there is no impact of polymer or other insulating layers on the measured signals. HERCULES is the first process control tool providing real-time accessibility to plasma parameters - based on an electrical measurement principles - for rf plasmas under industrial conditions. The efficient data handling being ready for use in production includes an internal process data bank and offers two ways to control the process: 1) independent of the etch tool, and 2) using a data coupling utility providing fast and easy access to wafer and lot data. Here, the second possibility was used based on a chamber log-sheet for lot and single wafer control. The major benefit of this choice is that data can be analyzed by lot and product using standard software. The SEERS tool demonstrated a high sensitivity and significant correlation of measured signals to variations of fundamental process parameters. It was found to be well suited to control stability of process equipment and to support process optimization and development. Important suppliers, e.g. Applied Materials and Lam Research, have supported the assessment and are interested in applying this process control tool.

The general principles of operation of passive and active pyrometry methods are considered. The usefulness of ratio, multi-ratio, approximation, and enhanced emissivity methods to unknown and changing emissivity situations is analyzed. A spectral functional for the emissivity is postulated to give the theoretical limit of accuracy of any passive method. A novel passive-active method, with accuracy better than 1 percent, for semiconductor wafer measurement is described and demonstrated through on-line measurement in Rapid Thermal Chemical Vapor Deposition process.

The work contains results of investigation on the phenomena of the electron emission and photoemission in thin oxide layers in which internal electric field has been generated. Study on secondary electron emission from complex many- layered emitters has led to the discovery of Malter's effect. Basing on it, the sample was a glass with semiconducting films evaporated on its both sides. The internal electric field was created by applying a negative voltage U_pol to the field electrode. The investigations were performed in the vacuum of the order 10^-6 Pa. As a result of applying U_pol and illumination, electrons and photoelectrons are released and recorded as voltage pulses in the multichannel pulse amplitude analyzer. The amplitude spectra N(U) equals f(U) for various U_pol were measured for not illuminated samples and illuminated ones. Electron emission yield dependence on the intensity of an internal field and illumination was measured. With increasing U_pol the count frequency of pulses grows monotonically. The electric field initiates electron collisions which proceed according to the impact ionization mechanism. Energy analysis of emitted electrons was performed by the retarding field method. Measurements of electron energy in field induced emission showed that about 80 percent of electrons have energy up to 10 eV.

Electrostatic discharge (ESD) due to electrostatic chuck (ESC) during ion implantation was observed in our fab. This defect could burn out the inter-layer dielectric and jeopardize the circuit performance. the yield impact on 0.35 micrometers product could be 40 percent. The defect distributed around the wafer edge and has a ring-type map. This defect occurred right after ESD implantation. The fringe field of the electrostatic chuck is the key reason why ring-type electrostatic discharge damage happened right after ion implantation. Our experimental result also showed that the junction characterization and surface conductivity will influence the probability of ESD damage caused by electrostatic chuck of ion implanter.

In this paper, we demonstrate the way in which techniques available on a scanning transmission electron microscope (STEM), particularly Z-contrast imaging and energy- dispersive x-ray microanalysis, can be applied successfully in the characterization and failure analysis of super-micron semiconductor manufacturing technologies. Following a general description of the techniques, two separate examples are given: Firstly, the detailed characterization of a low temperature coefficient of resistance SiCCr thin film where a complex microstructure covering a total thickness of approximately 100 angstrom is revealed and described. Secondly, we describe the way in which STEM was used to detect and observe nanometer-sized PtSi spiking in doped epilayers - the root cause of an NMOS sub-threshold leakage issue.

Effect of plasma enhanced chemical vapor deposition W-N diffusion barrier on characteristics of Cu based multilevel interconnect with fluorine doped silicon oxide (SiOF) was investigated. AFM results show that surface roughness of Cu film on the SiOF/Si increases 7.27 angstrom to 78.82 angstrom, whereas that of the Cu on the W-N/SiOF/Si, exhibiting smoother surface, increases from 12.49 to 45.31 angstrom after annealing at 500 degrees C for 30 min. Also, the resistivity of Cu/W-N/SiOF/Si system is lower than that of Cu/SiOF/Si after post-annealing. The stress evolution during the annealing at 200-500 degrees C reveals that the Cu and SIOF films have tensile stresses and the W-N film has low compressive stress. Therefore, Cu/W-N/SiOF/Si interconnect has lower tensile than that of Cu/SiOF/Si due to the low compressive stress of the W-N. C-V measurements show that in the Cu/SiOF/Si capacitor the threshold voltage shifts to -0.5 V after annealing at 500 degree C for 30 min. These results mean that the Cu atoms are diffused into the SiOF after post annealing and these Cu atoms act as positive ions in the SiOF. However, in the Cu/W-N/SiOF/Si the W-N prevents the diffusion of Cu atoms into the SiOF and the out diffusion of F from the SiOF.

Rapid and cost effective technology development is required in order to meet competitive time to market constraints for modern semiconductor products. TCAD tools are indispensable for meeting both time and cost targets by pinpointing the required development effort and thereby reducing the development work required. In this study, the requirement is to increase the substrate breakdown voltages and thereby reducing the development work required. In this study, the requirement is to increase the substrate breakdown voltages of both npn and pnp bipolar transistors for a complimentary vertical bipolar process from 120V to 155V. A design of experiment approach to both device layout and process technology development is used to ensure that both layout and process sensitivities are rigorously considered in designing-in the manufacturability of the technology at the development stage. TCAD tools are used to show that the increased breakdown voltages can be achieved purely by optimizing the device layout. A layout DOE is performed to guarantee that there is no marginality relating to the device layout. Monte Carlo analysis then performed to determine the process steps that the breakdown voltage is most sensitive to. A process DOE is then run to ensure that there is no marginality relating to the process.

Plasma induced charging damage and oxide degradation after metal and poly etch and photoresist strip were studied using unpatterned oxide wafer technique. The time dependence of plasma induced charging, internal oxide damage oxide damage and charging 'fingerprint' were investigated for poly etch, metal etch processes. Comparison of oxide charging monitor results and SPIDER antennae structures data for photoresist strip process is presented.

Sheet resistance measurements are often used as process control monitors and are a key part of resistor measurements for SPICE models. These are normally Ohmic in nature. However it can be seen that buried layer resistors are strongly affected by the applied bias conditions in a similar mode to JFET operation. Two standard resistor structures have been studied to investigate this effect: the bar resistor and the van der Pauw, 2D and 3D-device simulation have been used to model the self-modulation and to produce recommendations for optimized routine measurement.

The search for better yields in IC manufacturing calls for a smarter use of the vast amount of data that can be generated by a world class production line.In this scenario, in-line inspection processes produce thousands of wafer maps, number of defects, defect type and pictures every day. A step forward is to correlate these with the other big data- generator area: test. In this paper, we present how these data can be put together and correlated to obtain a very useful yield predicting tool. This correlation will first allow us to calculate the kill ratio, i.e. the probability for a defect of a certain size in a certain layer to kill the die. Then we will use that number to estimate the cosmetic yield that a wafer will have.

Semitool, HYT/Pacific Scientific and MOS4YOU/Philips Semiconductors decided to investigate in close cooperation the process control and process optimization through particle reduction on a Semitool Magnum wet clean system, by use of an In-Situ Particle Monitor (ISPM). This is a new application for ISPM, for Semitool and for Philips. The goal of the cooperation is to evaluate the ISPM, to interpret the data generated and to improve the overall performance of the wet clean system. The ISPM detected wafers which were not cleaned properly as well as wafers which were not properly dry etched in a previous production step. Furthermore the ISPM allowed us to improve the cleaning process, by improving the cleaning cycle of the chemical. Hereby, the ISPM proved to be a valuable tool for process control and process improvement. As particles are the main source for yield loss,the impact of a particle reduction program on yield is straightforward.

Usually, thick passivations avoid access to voltage contrast localization of electrical opens and shorts. In many cases, depassivation is not a suitable method, since it might influence the failure structure by preparation artifacts. FIB allows both to do in-situ voltage contrast imaging, to put certain parts of the circuitry on ground and to depassivation locally. In-situ failure characterization is also performed by FIB-cross-sectioning and imaging, as it is shown in the following few representative examples.

It has recently been shown that for very large chips, especially those with some incorporated redundancy, the chip's floorplan may affect its yield. When selecting a floorplan, the designer should, therefore, consider the expected yield in addition to the traditional objectives such as area, performance, and routing complexity. This paper studies the two seemingly unrelated objectives of routing complexity minimization and yield maximization, and justifies the need for a trade-off analysis when determining the floorplan. We will focus on the analysis of large memory ICs with redundant modules, for which several alternative floorplans may exist.

Time to yield entitlement is known as one of the key issues for the new technology introduction and production ramp-up. The term 'entitlement' refers to the target where a technology achieves maturity, that is consistently good performance in terms of yield. Within this scope, we present the strategy followed to 'entitle' the 0.3 microns technology into our manufacturing line. Complementary approaches were simultaneously used to optimize the sped of the yield learning cycle: baseline yield analysis, a line monitor program and standard low yield failure analysis. The record times achieved for the yield entitlement have shown the efficiency of the approach. The paper gives the detail of the result obtained with each type of analysis and also how they were managed to implement corrective and preventive action plans in a fast way.

This paper describes an automated manufacturability assessment and yield prediction software platform that has been developed, installed and used in a semiconductor manufacturing environment. the system is applied to characterize all incoming new products by extracting a large number of design attributes from their layout. Be checking the similarity to products that have already shown acceptable levels of yield, the risk of starting high volume production for new products is evaluated. The system also accurately predicts product yield on functional-block and layer level which is indispensable for the understanding of product dependent yield loss and rapid yield learning. The system proves to be a very valuable addition to the conventional yield analysis methodologies.

A model based on information theory, which allows yield managers to choose the optimal strategies for yield management in microelectronic manufacturing, is presented. The data reduction rate per experimentation cycle and data reduction rate per unit time serve as benchmarking metrics for yield learning. These newly defined metrics enable managers to make objective comparisons of apparently unrelated technologies. Four yield analysis tools -- electrical testing, automatic defect classification, spatial signature analysis and wafer position analysis -- are examined in detail to suggest an optimal yield management strategy for both the R and D and volume production environments.

The technique of analog integrated circuits statistical analysis is suggested. This technique enables to determine the interrelation between integrated circuit yield on the one hand and the dimensions of elements on the other hand. The idea is based on the common use of experimental statistical analysis and statistical modeling and on the introduction of the concept of the integrated circuit intermediate parameters. The results of statistical analysis of two analog integrated circuits has been cited as an example of suggested technique. They show that there exist optimal dimensions of integrated circuits elements by yield maximum criteria and the values of optimal dimensions of elements depend on process technology level and the requirements for integrated circuits output parameters.

The structural and electrical properties of BF₂⁺ implanted PECVD tungsten nitride thin film were investigated. After BF₂⁺ implantation with 40keV and 1 X 10¹⁷ B ions/cm², W-B⁺-N layer was formed at the surface region of W-N films. The ternary layer maintained the microcrystalline state and prevented nitrogen out-diffusion form W-N thin film after annealing at 800 degrees C for 30 min. The overall electrical resistivity of W-B⁺-N/W-N thin film is 200 (mu) (Omega) cm, which is higher than that of W-N thin film because of forming the ternary phase. BF₂⁺ implanted tungsten nitride thin film improved thermal stability against Cu diffusion more than W-N thin film.

Yield prediction using scanning electron microscope- automatic defect classification has the advantage of accuracy as compared with that using optical ADC because SEMs have higher resolving power and give us more information of particle/pattern-defect shape and surface texture than optical microscopes. We have proposed a method to predict die and wafer yield using SEM-ADC, it features (1) defect sampling which is performed in terms of die groups, (2) defect classification which enable us to get killer rates of defects, and (3) yield prediction taking account of the effects of prior level defects.