PROCEEDINGS VOLUME 3883
MICROELECTRONIC MANUFACTURING '99 | 22-23 SEPTEMBER 1999
Multilevel Interconnect Technology III
MICROELECTRONIC MANUFACTURING '99
22-23 September 1999
Santa Clara, CA, United States
Copper Interconnect Technology
Proc. SPIE 3883, Copper contamination effect on the reliability of devices in the BiCMOS technology, 0000 (11 August 1999); doi: 10.1117/12.360578
Proc. SPIE 3883, Challenges of damascene etching for copper interconnect, 0000 (11 August 1999); doi: 10.1117/12.360584
Proc. SPIE 3883, IMP copper seed layer formation with TaN barrier for deep submicron, 0000 (11 August 1999); doi: 10.1117/12.360585
Proc. SPIE 3883, Influence of IMP copper flash layer on the properties of copper films deposited by metal organic chemical vapor deposition, 0000 (11 August 1999); doi: 10.1117/12.360586
Dielectrics, Contacts, Vias
Proc. SPIE 3883, Polymer residue formation in vias caused by plasma etching of underlying titanium-rich films, 0000 (11 August 1999); doi: 10.1117/12.360587
Proc. SPIE 3883, ILD thermal stability in deep-submicron technologies: from thin to ultrathin dielectric films, 0000 (11 August 1999); doi: 10.1117/12.360588
Interconnect Process Integration
Proc. SPIE 3883, Integration of a high-Q spiral inductor into an existing digital CMOS backend, 0000 (11 August 1999); doi: 10.1117/12.360572
Proc. SPIE 3883, Integration of Flowfill and Forcefill for cost-effective via applications, 0000 (11 August 1999); doi: 10.1117/12.360573
Proc. SPIE 3883, Capping layers, cleaning method, and rapid thermal processing temperature on cobalt silicide formation, 0000 (11 August 1999); doi: 10.1117/12.360574
Proc. SPIE 3883, Defect reduction methodologies for damascene interconnect process development, 0000 (11 August 1999); doi: 10.1117/12.360575
Lithography and Etching for Interconnect Technology
Proc. SPIE 3883, Development and integration of a new metal structuring process for 256 MDRAMs, 0000 (11 August 1999); doi: 10.1117/12.360576
Proc. SPIE 3883, Lithographic CD variation in contact, via, local interconnect, and damascene levels, 0000 (11 August 1999); doi: 10.1117/12.360577
Barrier Layers
Proc. SPIE 3883, Ultrathin integrated ion metal plasma titanium and metallorganic titanium nitride liners for sub 0.18 um W based metallization schemes for >500 MHz microprocessors, 0000 (11 August 1999); doi: 10.1117/12.360579
Proc. SPIE 3883, Integrated IMP Ti and MOCVD TiN for 300-mm W barrier and liner for sub-0.18-um IC processing, 0000 (11 August 1999); doi: 10.1117/12.360580
Proc. SPIE 3883, Enabling and cost-effective TiCl4-based PECVD Ti and CVD TiN processes for gigabit DRAM technology, 0000 (11 August 1999); doi: 10.1117/12.360581
Proc. SPIE 3883, Novel metallization scheme using nitrogen passivated Ti liner for AlCu-based metallization, 0000 (11 August 1999); doi: 10.1117/12.360582
Poster Session
Proc. SPIE 3883, Comparing the electrical characteristics and reliabilities of BJTs and MOSFETs between Pt and Ti contact silicide processes, 0000 (11 August 1999); doi: 10.1117/12.360583
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