PROCEEDINGS VOLUME 4181
MICROELECTRONIC MANUFACTURING | 18-19 SEPTEMBER 2000
Challenges in Process Integration and Device Technology
IN THIS VOLUME

0 Sessions, 40 Papers, 0 Presentations
MICROELECTRONIC MANUFACTURING
18-19 September 2000
Santa Clara, CA, United States
Lithography Issues I
Proc. SPIE 4181, Evolution of semiconductor process technology, 0000 (18 August 2000); doi: 10.1117/12.395712
Proc. SPIE 4181, Subwavelength optical lithography, 0000 (18 August 2000); doi: 10.1117/12.395721
Proc. SPIE 4181, Feasibility of very low k1(=0.31) KrF lithography, 0000 (18 August 2000); doi: 10.1117/12.395744
Proc. SPIE 4181, Pattern placement errors: application of in-situ interferometer-determined Zernike coefficients in determining printed image deviations, 0000 (18 August 2000); doi: 10.1117/12.395748
Proc. SPIE 4181, MEEF measurement and model verification for 0.3-k1 lithography, 0000 (18 August 2000); doi: 10.1117/12.395749
Lithography Issues II
Proc. SPIE 4181, Benchmarking of advanced CD-SEMs against a new unified specification for sub-0.18-um lithography, 0000 (18 August 2000); doi: 10.1117/12.395750
Proc. SPIE 4181, Effects of advanced illumination schemes on design manufacturability and interactions with optical proximity corrections, 0000 (18 August 2000); doi: 10.1117/12.395751
Proc. SPIE 4181, Deciphering and encoding product overlay: hidden errors, 0000 (18 August 2000); doi: 10.1117/12.395713
Proc. SPIE 4181, Automated OPC optimization using in-line CD-SEM, 0000 (18 August 2000); doi: 10.1117/12.395714
Proc. SPIE 4181, Advanced lithography kits: serifs and hammerhead, 0000 (18 August 2000); doi: 10.1117/12.395715
Proc. SPIE 4181, Investigations on the impacts of misalignment in the integration of 0.18-u multilevel interconnect, 0000 (18 August 2000); doi: 10.1117/12.395716
Proc. SPIE 4181, Novel electrical alignment structure, 0000 (18 August 2000); doi: 10.1117/12.395717
New Materials
Proc. SPIE 4181, Thickness-dependent optical and dielectric behaviors of low-k polymer thin films, 0000 (18 August 2000); doi: 10.1117/12.395718
Proc. SPIE 4181, Design and process issues affecting performance of optical interconnects on ICs, 0000 (18 August 2000); doi: 10.1117/12.395719
Proc. SPIE 4181, Optical coherent control in materials with stripe phase, 0000 (18 August 2000); doi: 10.1117/12.395720
Integration I
Proc. SPIE 4181, High-performance vs. low-power technology roadmaps: how are they different?, 0000 (18 August 2000); doi: 10.1117/12.395722
Proc. SPIE 4181, Planarization approaches to via-first dual-damascene processing, 0000 (18 August 2000); doi: 10.1117/12.395723
Proc. SPIE 4181, Etching characteristics of organic low-k dielectrics in the helicon-wave plasma etcher for 0.15-um damascene architecture, 0000 (18 August 2000); doi: 10.1117/12.395724
Proc. SPIE 4181, Modeling of the removal rate in chemical mechanical polishing, 0000 (18 August 2000); doi: 10.1117/12.395725
Integration II
Proc. SPIE 4181, Process development of 50-A IMP Ti with <2% thickness uniformity for 300-mm iLB, 0000 (18 August 2000); doi: 10.1117/12.395726
Proc. SPIE 4181, Isothermal test as a WLR monitor for Cu interconnects, 0000 (18 August 2000); doi: 10.1117/12.395727
Proc. SPIE 4181, Effect of stress and dopant redistribution on trench-isolated narrow devices, 0000 (18 August 2000); doi: 10.1117/12.395728
Proc. SPIE 4181, Yield-limiting NMOSFET gate depletion in a deep submicrometer CMOS process, 0000 (18 August 2000); doi: 10.1117/12.395729
Proc. SPIE 4181, Backwafer optical lithography and wafer distortion in substrate transfer technologies, 0000 (18 August 2000); doi: 10.1117/12.395730
Device Scaling
Proc. SPIE 4181, Scaling considerations for MOSFET devices with 25-nm channel lengths, 0000 (18 August 2000); doi: 10.1117/12.395731
Proc. SPIE 4181, Correlation between the reliability of ultrathin ISSG SiO2 and hydrogen content, 0000 (18 August 2000); doi: 10.1117/12.395732
Proc. SPIE 4181, Evaluation of Schottky contact parameters in MSM-photodiode structures, 0000 (18 August 2000); doi: 10.1117/12.395733
Proc. SPIE 4181, Measuring thicknesses of native oxide, crystalline-silicon, and buried oxide layers and the interface roughnesses of SOI, 0000 (18 August 2000); doi: 10.1117/12.395734
Poster Session
Proc. SPIE 4181, Microstructuring with 193-nm laser radiation, 0000 (18 August 2000); doi: 10.1117/12.395735
Proc. SPIE 4181, Is lithography ready for 300 mm?, 0000 (18 August 2000); doi: 10.1117/12.395736
Proc. SPIE 4181, Efficient resist edgebead removal for thick I-line resist coating application on TEL Mark 7 track sytem, 0000 (18 August 2000); doi: 10.1117/12.395737
Proc. SPIE 4181, Prospective technology for system-on-a-chip: N2 implant followed by VHP O2 reoxidation, 0000 (18 August 2000); doi: 10.1117/12.395738
Proc. SPIE 4181, Low-k etch/ash for copper dual damascene, 0000 (18 August 2000); doi: 10.1117/12.395739
Proc. SPIE 4181, Increasing degree of homogeneity of electrical parameters of neutron-transmuted silicon, 0000 (18 August 2000); doi: 10.1117/12.395740
Proc. SPIE 4181, Field effects in the dielectrics coated by ITO films, 0000 (18 August 2000); doi: 10.1117/12.395741
Proc. SPIE 4181, Influence of the varyband layer of the amorphous hydrogenated silicon-germanium on the current-volt characteristics of the n+(a-Si:H)-i(a-Si1-xGex:H)-n+(a-Si:H)-structures, 0000 (18 August 2000); doi: 10.1117/12.395742
Proc. SPIE 4181, Laser-induced structure defects and their use for modification of properties of (Cd,Hg)Te epitaxial layers end CdTe cyrstals, 0000 (18 August 2000); doi: 10.1117/12.395743
Proc. SPIE 4181, Design and fabrication of a GXGA microdisplay chip, 0000 (18 August 2000); doi: 10.1117/12.395745
Proc. SPIE 4181, Low-energy neutral processing and process characterization, 0000 (18 August 2000); doi: 10.1117/12.395746
Proc. SPIE 4181, Technology of electroplating copper with low-K material a-C:F for 0.15-um damascence interconnection, 0000 (18 August 2000); doi: 10.1117/12.395747
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