PROCEEDINGS VOLUME 4867
ITCOM 2002: THE CONVERGENCE OF INFORMATION TECHNOLOGIES AND COMMUNICATIONS | 29 JULY - 1 AUGUST 2002
Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications IV
IN THIS VOLUME

0 Sessions, 12 Papers, 0 Presentations
Session 1  (3)
Session 2  (2)
Session 3  (3)
Session 4  (4)
ITCOM 2002: THE CONVERGENCE OF INFORMATION TECHNOLOGIES AND COMMUNICATIONS
29 July - 1 August 2002
Boston, MA, United States
Session 1
Proc. SPIE 4867, Net-aware bitstreams that upgrade FPGA hardware remotely over the Internet: creating intelligent bitstreams that know where to go, what to do when they get there, and can report back when they're d, 0000 (2 July 2002); doi: 10.1117/12.455326
Proc. SPIE 4867, Constraint-directed CAD tool for automatic latency-optimal implementation of 1D and 2D Fourier transforms, 0000 (2 July 2002); doi: 10.1117/12.455338
Proc. SPIE 4867, Single instruction set architectures for image processing, 0000 (2 July 2002); doi: 10.1117/12.455451
Session 2
Proc. SPIE 4867, Design flow for the reconfigurable HW platform XPP, 0000 (2 July 2002); doi: 10.1117/12.455385
Proc. SPIE 4867, Implementing a dynamically reconfigurable ATM switch on the VIRTEX FPGA of the FPX platform, 0000 (2 July 2002); doi: 10.1117/12.455401
Session 3
Proc. SPIE 4867, Framework for development and distribution of hardware acceleration, 0000 (2 July 2002); doi: 10.1117/12.455459
Proc. SPIE 4867, Optimizing parallel programs for hardware implementation, 0000 (2 July 2002); doi: 10.1117/12.455467
Proc. SPIE 4867, Defect-tolerant fine-grained parallel testing of a cell matrix, 0000 (2 July 2002); doi: 10.1117/12.455473
Session 4
Proc. SPIE 4867, Parameterizing reconfigurable designs for image warping, 0000 (2 July 2002); doi: 10.1117/12.455482
Proc. SPIE 4867, Minimizing energy dissipation of matrix multiplication kernel on Virtex-II, 0000 (2 July 2002); doi: 10.1117/12.455487
Proc. SPIE 4867, Reconfigurable platform for development of embedded systems, 0000 (2 July 2002); doi: 10.1117/12.455387
Proc. SPIE 4867, Reconfigurable logic design case, 0000 (2 July 2002); doi: 10.1117/12.469748
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