PROCEEDINGS VOLUME 5042
ADVANCED MICROELECTRONIC MANUFACTURING | 27-28 FEBRUARY 2003
Design and Process Integration for Microelectronic Manufacturing
ADVANCED MICROELECTRONIC MANUFACTURING
27-28 February 2003
Santa Clara, CA, United States
Advanced RETs
Proc. SPIE 5042, Layout optimization at the pinnacle of optical lithography, 0000 (10 July 2003); doi: 10.1117/12.485245
Proc. SPIE 5042, Dense only phase-shift template lithography, 0000 (10 July 2003); doi: 10.1117/12.485244
Proc. SPIE 5042, Assessing technology options for 65-nm logic circuits, 0000 (10 July 2003); doi: 10.1117/12.485256
Proc. SPIE 5042, Generalization of the photo process window and its application to OPC test pattern design, 0000 (10 July 2003); doi: 10.1117/12.497476
Technology Modeling, CAD, and Optimization
Proc. SPIE 5042, Technology CAD for integrated circuit fabrication technology development and technology transfer, 0000 (10 July 2003); doi: 10.1117/12.485267
Proc. SPIE 5042, Performance-impact limited-area fill synthesis, 0000 (10 July 2003); doi: 10.1117/12.487732
Proc. SPIE 5042, Simulation-based data processing using repeated pattern identification, 0000 (10 July 2003); doi: 10.1117/12.485457
Proc. SPIE 5042, Model-assisted placement of subresolution assist features: experimental results, 0000 (10 July 2003); doi: 10.1117/12.485421
Proc. SPIE 5042, OPC on real-world circuitry, 0000 (10 July 2003); doi: 10.1117/12.485484
DFM and Information Management
Proc. SPIE 5042, Characterization and modeling of intradie variation and its applications to design for manufacturability, 0000 (10 July 2003); doi: 10.1117/12.497477
Design, Design Objectives, and Validation
Proc. SPIE 5042, Lithography-driven layout of logic cells for 65-nm node, 0000 (10 July 2003); doi: 10.1117/12.485349
Proc. SPIE 5042, Improved manufacturability by OPC based on defocus data, 0000 (10 July 2003); doi: 10.1117/12.485251
Proc. SPIE 5042, LithoScope: an advanced physical modeling system for mask data verification, 0000 (10 July 2003); doi: 10.1117/12.487630
Proc. SPIE 5042, Investigation of product design weaknesses using model-based OPC sensitivity analysis, 0000 (10 July 2003); doi: 10.1117/12.485263
Devices, Layouts, and Patterning
Proc. SPIE 5042, Device characteristics of sub-20-nm silicon nanotransistors, 0000 (10 July 2003); doi: 10.1117/12.485268
Proc. SPIE 5042, NBTI improvement for pMOS by Cl-contained 1st oxidation in 20A/65A dual-nitrided gate oxide of 0.13-um CMOS technology, 0000 (10 July 2003); doi: 10.1117/12.485249
Proc. SPIE 5042, Library-based process test vehicle design framework, 0000 (10 July 2003); doi: 10.1117/12.485264
Proc. SPIE 5042, Design-to-process integration: optimizing 130-nm X architecture manufacturing, 0000 (10 July 2003); doi: 10.1117/12.485258
Proc. SPIE 5042, Using the CODE technique to print complex two-dimensional structures in a 90-nm ground rule process, 0000 (10 July 2003); doi: 10.1117/12.485529
DFM and Information Management
Proc. SPIE 5042, New stream format: progress report on containing data size explosion, 0000 (10 July 2003); doi: 10.1117/12.485260
Proc. SPIE 5042, Optimization of the data preparation for variable-shaped beam mask writing machines, 0000 (10 July 2003); doi: 10.1117/12.485261
Proc. SPIE 5042, Compression algorithms for dummy-fill VLSI layout data, 0000 (10 July 2003); doi: 10.1117/12.485247
Image Quality and Design Rules
Proc. SPIE 5042, Precision control of poly-gate CD by local OPC for elimination of microloading effect on 0.13-um CMOS technology, 0000 (26 June 2003); doi: 10.1117/12.485250
Poster Session
Proc. SPIE 5042, Creation and verification of phase-compliant SoC IP for the fabless COT designers, 0000 (10 July 2003); doi: 10.1117/12.485257
Proc. SPIE 5042, Statistical data assessment for optimization of the data preparation and manufacturing, 0000 (10 July 2003); doi: 10.1117/12.485262
Proc. SPIE 5042, Lithographic tradeoffs between different assist feature OPC design strategies, 0000 (10 July 2003); doi: 10.1117/12.485326
Proc. SPIE 5042, Resolution enhancement technology requirements for 65-nm node, 0000 (10 July 2003); doi: 10.1117/12.485486
Proc. SPIE 5042, PsmLint: bringing AltPSM benefits to the IC design stage, 0000 (10 July 2003); doi: 10.1117/12.485253
Proc. SPIE 5042, Optimizing manufacturability for the 65-nm process node, 0000 (10 July 2003); doi: 10.1117/12.485248
Technology Modeling, CAD, and Optimization
Proc. SPIE 5042, Physical and timing verification of subwavelength-scale designs: I. Lithography impact on MOSFETs, 0000 (10 July 2003); doi: 10.1117/12.499089
Poster Session
Proc. SPIE 5042, Optimized cobalt silicide formation through etch process improvements, 0000 (10 July 2003); doi: 10.1117/12.485242
Design, Design Objectives, and Validation
Proc. SPIE 5042, Effective multicutline QUASAR illumination optimization for SRAM and logic, 0000 (10 July 2003); doi: 10.1117/12.504321
Poster Session
Proc. SPIE 5042, Modification of existing chip layout for yield and reliability improvement by computer-aided design tools, 0000 (10 July 2003); doi: 10.1117/12.504322
In-Depth Seminar
Design, Design Objectives, and Validation
Proc. SPIE 5042, OPC methods to improve image slope and process window, 0000 (10 July 2003); doi: 10.1117/12.515190
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