A review of recent results concerning the low frequency noise in modern CMOS devices is given. The approaches such as the carrier number and the Hooge mobility fluctuations used for the analysis of the noise sources are presented and illustrated through experimental data obtained on advanced CMOS generations. The application of low frequency noise measurements as a characterization tool for large area MOS devices is also discussed. The main physical characteristics of random telegraph signals (RTS) observed in small area MOS transistors are reviewed. The impact of scaling down on the low frequency noise and RTS fluctuations in CMOS silicon devices is also addressed. Experimental results obtained on 0.35-0.12 μm CMOS technologies are used to predict the trends for the noise in future CMOS technologies e.g. 0.1μm and beyond. The formulation of thermal noise underlying the low frequency 1/f or RTS fluctuations in MOSFETs is also recalled for completeness.

An overview of the theoretical 1/f noise models is given. Analytical expressions showing the device geometry and bias dependence of 1/f noise in all conduction regime are summarized. Recent experimental studies on 1/f noise in MOS transistors are presented with special emphasis for PMOS from a 90 nm CMOS technology. Gate and drain noise sources are investigated. It is shown that in subthreshold regime drain current noise agrees with carrier number fluctuation model whereas in strong inversion the evolutions can be described by mobility fluctuation model. Gate current noise shows 1/f and white noise. White noise is very close to shot noise, and we have a quadratic variation of 1/f noise with gate current. Coherence measurements show that the increase of drain noise at high gate biases can be attributed to tunneling effects. Input-referred gate noise and the volume trap density can be used as figure of merit. Discrepancies with the ITRS roadmap are discussed.

We have measured the back channel low frequency noise of 0.6um*2.3um SOI nMOS transistors with a buried oxide thickness of 170 nm as a function of frequency (f), back gate bias (Vbg ), and temperature (T). For a temperature range of, noise measurements were performed at frequencies of, with top gate grounded and Vbg-Vbgth=4V, where Vbgth is the back gate threshold voltage. After zero-bias X-ray irradiation, the noise power increases, in agreement with previous work on the noise response of bulk MOSFETs. The temperature and frequency dependences of the 1/f noise of back channel SOI nMOS transistors shows thermally-activated charge exchange between the Si channel and defects in the buried oxide. Comparison is made with the Dutta and Horn model of 1/f noise. Devices on one particular wafer appear to show a mixture of 1/f noise and noise due to diffusion of a hydrogen-related species.

We investigate the impact of body biasing on the low frequency noise (LFN) performances of NMOS transistors from a transistors 130 nm CMOS technology. The body-to-source voltage V_BS was varied from - 0.5 to + 0.5 V for reverse and forward mode substrate biasing. A detailed electrical characterization was performed and the benefits of the body bias analysed in terms of current and maximum transconductance variations. Noise measurements were first performed at low drain bias V_DS = 25 mV and V_BS = 0 V in order to discuss the noise model. Results are in agreement with the carrier number fluctuation theory. Bulk bias dependence of the LFN was investigated at V_DS = V_DD = 1.2 V. Significant noise reduction is observed in the subthreshold regime when applying a forward body bias. In strong inversion, the noise level is found to be approximately independent of the substrate bias V_BS.

This paper reviews the recent results of the flicker noise characterization and modeling of MOSFETs for RF IC design. The dependences of flicker noise characteristics to process parameters, such as the thickness and quality of gate oxide, and the device parameters, such as the channel length/width and fingers, have been summarized to better understand the flicker noise bahavior and develop physical and accurate flicker noise models. The physical origin of the flicker noise and the issues of the existing compact models in predicting the flicker noise characteristics have been also discussed. Furthermore, the impact of flicker noise to the phase noise of RF circuits is studied while looking for either process or circuit approaches to reduce the influence of flicker noise contribution to the circuit noise. Finally, some modeling approaches are proposed to improve existing compact flicker noise models to predict the noise behavior of RF circuits well.

This paper presents a non-quasi-static (NQS) thermal noise model of the MOS transistor that is valid in all modes of operation, from weak to strong inversion, and up to frequencies which are near or above the NQS cut-off frequency. It is shown that in addition to the well-known induced gate noise (IGN) there is also an induced substrate noise that is generated and that the source and drain noises are also affected. All prior publications on the subject only deal with IGN in strong inversion regime. It is shown that significant differences are obtained for moderate and weak inversion operation. The paper starts with a brief review of NQS model valid in all modes of operation. It then presents a general thermal noise model using four noisy current sources. The power spectral and cross power spectral densities of these noise sources are computed. A first-order approximation is then derived and compared to the complete model. Noise excess factors for the drain and the gate noise are then calculated and the correlation coefficient between the drain and the gate noise is obtained. It is shown that this correlation factor is always null in conduction (VD = VS), and varies in saturation between j0.6 in weak inversion to j0.4 in strong inversion. To our knowledge, it is the first time that a complete HF thermal noise model of the MOST is presented, that is valid in all modes of inversion and up to and above the NQS cut-off frequency.

We study the the thermal noise of short-channel NMOS transistors in a commercially available 0.13 micron CMOS technology. The experimental results are modeled with a non-quasi-static RF model, based on the principle of channel segmentation. The model is capable of predicting both drain and gate current noise accurately, without fitting any parmeters to the measured noise data. An essential ingredient of the model is the gate resistance, which is shown to dominate the gate current noise. In our optimized device layouts, this gate resistance is mainly determined by the silicide-to-polysilicon contact resistance.

Parameters limiting the improvement of high frequency characteristics for deep sub micron MOSFETs (bulk and SOI) with the downscaling process of the channel gate length are analyzed experimentally. The high frequency performances of MOSFETs are generally characterized by the specific transit frequencies ft, f_max. ft and/or f_max, what is the good factor of merit to quantify the performance of a transistor ft, which corresponds to the transit frequency (when the gain is equal to 1) of the current gain, is an interesting criterion for high speed digital applications (speed and high swing) while f_max, which is defined as the transit frequency of the unilateral power gain is the best criterion for analogue microwave applications (amplifier, oscillators, etc.). f_max corresponds also to the transit frequency of the maximum available power gain (MAG) that is a realistic parameter of the optimization of microwave amplifiers. Moreover, at the opposite of ft, f_max includes the contribution of the gate resistance, which degrades the high frequency noise performance. The different contributions of the extrinsic and intrinsic parameters on these transit frequencies will be detailed. We will support this analysis by experimental results obtained from several deep sub micron SOI and bulk MOSFETs technologies. We will focus essentially this presentation on the different technological ways of optimization on the high frequency performance of MOSFETs and particularly concerning its high frequency noise characteristics.

For many analog integrated circuit applications, the polysilicon emitter bipolar junction transistor (PE-BJT) is still the preferred choice because of its higher operational frequency and lower noise performance characteristics compared to MOS transistors of similar active areas and at similar biasing currents. In this paper, we begin by motivating the reader with reasons why bipolar transistors are still of great interest for analog integrated circuits. This motivation includes a comparison between BJT and the MOSFET using a simple small-signal equivalent circuit to derive important parameters that can be used to compare these two technologies. An extensive review of the popular theories used to explain low frequency noise results is presented. However, in almost all instances, these theories have not been fully tested. The effects of different processing technologies and conditions on the noise performance of PE-BJTs is reviewed and a summary of some of the key technological steps and device parameters and their effects on noise is discussed. The effects of temperature and emitter geometries scaling is reviewed. It is shown that dispersion of the low frequency noise in ultra-small geometries is a serious issue since the rate of increase of the noise dispersion is faster than the noise itself as the emitter geometry is scaled to smaller values. Finally, some ideas for future research on PE-BJTs, some of which are also applicable to SiGe heteorjunction bipolar transistors and MOSFETs, are presented after the conclusions.

The low-frequency noise observed on advanced junction bipolar transistors consist of 1/f noise as well as Random telegraph Signals (RTS). In relatively small emitter-base junction areas, RTS is seen in the spectra which can be differentiated from the typical generation-recombination (gr) noise through time domain analysis. For most cases, the 1/f noise can be modeled primarily with a current noise source in the base S_IB. There are cases, however, the noise originates primarily in the collector side due to S_IC, which has been neglected in modeling equations. We have designed two different measurement and analysis systems where the effect of S_IC and S_IB can be differentiated and separately modeled through correlated noise measurements that are performed at the collector and base or collector and emitter. Cross-power spectral density, as well as coherence is used to extract different noise components. Variable temperature low-frequency noise measurements to extract the different components of S_IB revealed that the diffusion noise due to mobility fluctuation, fluctuations in the recombination at the surface of the emitter/base depletion region, and fluctuations in the interfacial oxide tunneling barrier height, (and thus the tunneling probability of the carrier) are the components that need to be modeled. The results of the experimental data as well as modeling equations and techniques will be discussed.

The low frequency noise characteristics of double self-aligned InP/InGaAs and two types Si/SiGe heterojunction bipolar transistors (HBTs) were investigated. Spectral analysis shows no striking differences; the spectra are composed of a 1/f component and the white noise is always reached at low bias. A general trend for all the transistors was the presence of Lorentzian(s) component(s) for the smallest devices. The voltage coherence function was always one for SiGe transistors; and for the first time, it was found to be close to zero for InP devices. Concerning the 1/f noise level, both types of transistors have approximately a quadratic dependence on base current bias and an inverse dependence on the emitter area. Thus a comparison of the 1/f noise level has been made using the Kb parameter, and values around 10⁹ μm² for SiGe HBTs and around 10⁸ μm² for InP HBTs were found. These results are of same order of magnitude as the best published ones. The low frequency noise results suggest that excess noise sources are mainly located at the intrinsic emitter-base junction for the two type of SiGe devices, and for the for InP HBTs, a correlated noise source is located at the emitter periphery. To compare different devices and technologies, fc/fT where fT is the unity current gain frequency was studied as a function of collector current density and for some HBT technologies, fc/f_T α J_c. The effects of different processing conditions, designs and temperature were also investigated and will be discussed.

A gated lateral bipolar transistor is a bulk lateral BJT in parallel with a MOSFET at the surface. The base current components such as surface recombination and space charge recombination currents are two of the dominant noise sources in the lateral BJT. If the gate is biased such that the MOSFET is in the off-state by accumulating carriers underneath the oxide in the base surface, the noise contribution by these two base current (Ib) components can be better understood. The carrier accumulation in the base surface can be modulated with different gate bias, which in turn will affect the fluctuation of the surface recombination current component. In this paper, noise power spectral density of gated lateral PNP transistors, fabricated in Texas Instruments Standard Bipolar Process, has been discussed. The base current noise power spectral density (SIb) was extracted from the cross-correlation noise spectrum measured between the base and the collector circuits for different gate biasing conditions. Based on the frequency exponent dependence of the noise power spectral density, it was found that the noise in the low frequency range is in the form of 1/f noise. S_Ib was found to be the dominant noise source for these devices as the coherence between the base and collector power spectral density was very close to 1. S_Ib was extracted for a base current range of 8 nA to 1microA for a gate bias range of 0V to 40V. The SPICE noise model parameters, AF and KF were also determined for each case from the dependence of S_Ib on I_b. The noise was measured on devices with different base width values.

In this paper, the LFN in partially and fully depleted SOI CMOS technologies is overviewed. Static performances of the devices are first presented. Then we address, for different types of architectures, the drain current fluctuations in both linear and saturation regimes. A particular attention is paid to the floating body effect that induces a kink-related excess noise, which superimposes a Lorentzian spectrum on the flicker noise. The behavior of this effect with the frequency and the physical mechanisms explaining this excess niose, are discussed. The control of this noise overshoot by using a body contact or by applying a back gate voltage is also demonstrated. On the other hand, the LFN in DTMOS, in ohmic and saturation regimes, is studied and the impact of the use of a current limiter is thoroughly analyzed. Finally, the influence of the oxide thickness thinning on the noise is shown.

Timing jitter is a concern in high speed digital integrated circuits, the presence of timing jitter will degrade system performance in many high-speed applications. In the first part of this paper, we have simulated the timing jitter due to CMOS device noise in a nine stage CMOS differential ring oscillator, and a methodology to efficiently simulate timing jitter has been developed. Simulation results show the variation of absolute jitter due to flicker noise has a linear time dependence, while for white noise it has a square root time dependence, these are consistent with accepted theory. Two important parameters cycle jitter, and cycle to cycle jitter used to describe jitter performance can be obtained from simulation. Simulation results are also compared to experimental results. The methodology developed described in this paper is also applicable to other types of clock generators and oscillators such as LC oscillators, as well as other kinds of noise sources as power supply and substrate noise. In the second part this paper, we have employed this methodology and investigated the timing jitter in silicon BJT /or SiGe HBT ECL ring oscillators, and we have shown BJT /or SiGe HBT oscillators have lower jitter compared to their CMOS counterparts. As such silicon BJT and/or SiGe HBT ring oscillators are a potential choice for low jitter applications.

Phase noise in microwave transistors is studied both theoretically and experimentally using residual phase noise measurements. The experimental approach allows the exploration of many interesting features of phase noise generation in these devices, such as the dependence of phase noise versus microwave power or transistor low frequency loading, meanwhile nonlinear simulation is still necessary to optimise the microwave load and the whole oscillator circuit. The different behaviours described are illustrated in various microwave circuits, and particularly dielectric resonator oscillators, with some of them featuring state of the art performance.

Measurement-based, circuit-oriented non-linear noise modeling of microwave electron devices is still an open field of research, since existing approaches are not always suitable for the accurate prediction of low-frequency noise up-conversion to RF, which represents an essential information for the non-linear circuit analyses performed in the CAD of low phase-noise oscillators. In this paper a technology-independent, empirical approach to the modeling of noise contributions at the ports of electron devices, operating under strongly non-linear conditions, is proposed. Details concerning the analytical formulation of the model, which is derived by considering randomly time-varying perturbations in the basic equations of an otherwise conventional charge-controlled non-linear model, are presented, along with a discussion about the measurement techniques devoted to its experimental characterization. An example of application of the proposed Charge-Controlled Non-linear Noise (CCNN) model is considered in the case of a HBT transistor. Techniques devoted to the implementation of the obtained model in the framework of commercial CAD tools for circuit analysis and design are provided as well.

This paper reviews the development of the theory and measurement of recombination noise in semiconductor junction devices. It traces this development from van der Ziel's corpuscular models of noise in junction diodes and transistors through to recent models of shot-noise suppression and non-classical light emission from laser and light-emitting diodes due to Yamamoto and co-workers.

Generation-recombination (GR) noise in GaN and AlGaN thin films, GaN based Metal Semiconductor Field Effect Transistors (MESFETs), Heterostructure Field Effect Transistors (HFETs) and Schottky diode photodetectors was investigated. AlGaN thin films, AlGaN/GaN HFETs and Schottky barrier Al_0.4Ga_0.6N diodes exhibited GR noise with activation energies of 0.8 - 1 eV. AlGaN/GaN HFETs also presented GR noise with activation energies of 1 - 3 meV and 0.24 eV at cryogenic temperatures. No such noise was observed in thin doped GaN films and GaN MESFETs. GR noise with the largest reported activation energy of 1.6 eV was measured in AlGaN/InGaN/GaN Double Heterostructure Field Effect Transistors (DHFETs). We conclude that the local levels responsible for the observed noise in HFETs and DHFETs could be located in AlGaN barrier layers.

Trap assisted generation-recombination noise spectra of advanced n-channel MOSFETs are numerically simulated using the drift-diffusion transport model and focusing on the bimolecular electron transitions between the channel and gate oxide. Good agreement between measured and simulated data is observed in both the linear and saturated regime of operation under sub-threshold and inversion conditions. Reverse engineering of the measured noise data reveals the discrete trap distributions in the oxide responsible for the observed spectra.

Microwave noise technique is applied to study fast and ultrafast correlations in nitride and arsenide heterostructures containing a two-dimensional electron gas subjected to a strong electric field applied in the plane of electron confinement. The main attention is paid to experimental investigation of electron energy dissipation, hot phonons, and high-energy electrons shared by the adjacent layers (real-space transfer). The typical experimental values for the time of electron energy relaxation range from several picoseconds at low electric fields and low ambient temperatures to hundreds of femtoseconds at a high field. The measured dependence of the electron energy relaxation time on the bias is compared with those obtained through Monte Carlo simulation for different models. An essential contribution due to hot phonons and electron gas degeneracy is evidenced. Dependence of hot-phonon temperature on the electron temperature is deduced from the experimental results on the microwave noise and the dissipated power. The adjacent layers share the high-energy electrons unless the heterojunction barrier is high. Random transitions between the confined and the shared states cause microwave noise. The relaxation time of the occupancy fluctuations is estimated from the measured spectral intensity of current fluctuations. Hot phonons are found to reduce the threshold field for this noise source. The experimental data on AlGaN/GaN, AlGaAs/GaAs and AlInAs/GaInAs/AlInAs are compared.

The investigation of noise in electronic devices operating under large-signal conditions is attracting increasing attention in recent years. Theoretical analyses on this subject are typically performed in the framework of the impedance field method, implemented under the drift-diffusion approximation. As an alternative, a more general microscopic approach including a more detailed physical description of the systems is mandatory. This work reviews recent results of Monte Carlo simulations of electronic noise in bulk materials and submicron semiconductor structures subject to high-frequency large-amplitude periodic electric fields or applied voltages/currents. The peculiarity of the noise analysis under large-signal operation is that velocity or current/voltage fluctuations appear simultaneously with the regular response of the nonlinear medium or device, so that the regular response and noise spectra are overlapped in the whole frequency range of interest. Here, various correlation functions of fluctuations, their instantaneous and integrated spectral densities, etc. are calculated under large-signal operation for compound semiconductors, such as GaAs, and InN, as well as for GaAs Schottky-barrrier diodes and n+nn+ structures. A comparison with the results obtained under stationary conditions is performed. Under these large-signal cyclostationary working conditions, when the system response becomes nonlinear, several modifications and anomalies appear in the noise spectra with respect to static stationary conditions. In particular, an increase of the low-frequency noise and a resonant-like enhancement of the spectra near the fundamental frequency (and eventually high-order harmonics) of the applied signal is observed under some specific conditions. These anomalies are interpreted as a manifestation of dynamical effects under sufficiently high frequency and amplitude of the applied signal. Similarities and differences of the noise resonant-like enhancement around the fundamental frequency with noise upconversion processes are discussed.

The characteristic potential method(CPM), which has been successfully applied to calculate 1/f noise and thermal noise of multi-terminal homogeneous semiconductor resistors, is extended to calculate 1/f noise in inhomogeneous devices such as MOSFETs. The drain 1/f noise current of MOSFETs in the linear region is calculated using the CPM together with the well-known existing 1/f noise sources based on either Hooge's empirical model or McWhorter's model, and the calculated results are compared with the experimental results. It is shown that the difference of the 1/f noise behaviour between n-MOSFETs and p-MOSFETs in the linear region can be attributed to either the difference in their effective field dependence between the local electron mobility and the local hole mobility near the Si-SiO₂ interface in the inversion layer or the difference in degree of N_t(oxide trap density)dependence between the effective electron mobility and the effective hole mobility.

Models for 1/f noise, based on power spectral density synthesis of the 1/f form, are demonstrated. These include, first, a finite summation of independent random processes which have equal power and signalling rates, or mean waveform rates, that form a geometric series with a ratio of two. Second, a continuum of independent random processes where the power in a given random process is inversely proportional to the signalling rate, or mean waveform rate, and these rates form a continuum. The random processes can be that of a filtered random walk, signalling random process, generalized signalling random process or a shot noise process. It is shown that the pulse function associated with these random processes is relatively unimportant. It is shown that low frequency modulation of signal components which fragment off a wide-bandwidth random process can lead to 1/f noise.

Noise due to back-gate forward bias between substrate and source of a MOSFET is analyzed and simulated. Noise level is compared between two CMOS circuits with and without back-gate forward bias. It is found that the output noise introduced by the back-gate forward bias method is only a few nV/square root (Hz), which only slightly increases the device noise. A CMOS op-amp is designed utilizing back-gate forward bias technique utilizing a level shift current mirror for operation at ultra low-power in μW range. The designed amplifier dissipates power of 40 uW and operates at ± 0.4 V to achieve a gain of 77 dB. The noise in ultra low-power op-amp is also investigated. The total output noise density is about 30 μV/square root (Hz) in the ultra-low power op-amp design, which is lower than 65 μV/square root (Hz) of standard op-amp. The signal to noise ratio of the ultra low-power op-amp is 44 dB.

With the recent development of broadband and satellite communications, one of the main engines for the advance of modern Microelectronics is the fabrication of devices with increasing cutoff frequency and lowest possible level of noise. Even if heterojunction bipolar devices (HBTs) have reached a good frequency performance, the top end of high frequency low-noise applications is monopolized by unipolar devices, mainly HEMTs (High Electron Mobility Transistors). In particular, within the vast family of heterojunction devices, the best results ever reported in the W-band have been obtained with InP based HEMTs using the AlInAs/InGaAs material system, improving those of usual GaAs based pseudomorphic HEMTs. In field effect devices, the reduction of the gate length (Lg) up to the technological limit is the main way to achieve the maximum performances. But the design of the devices is not so simple, when reducing the gate length it is convenient to keep constant the aspect ratio (gate length over gate-to-channel distance) in order to limit short channel effects. This operation can lead to the appearance of other unwanted effects, like the depletion of the channel due to the surface potential or the tunneling of electrons from the channel to the gate. Therefore, in order to optimize the high frequency or the low-noise behavior of the devices (that usually can not be reached together) not only the gate-to-channel distance must be chosen carefully, but also many other technological parameters (both geometrical and electrical): composition of materials, width of the device, length, depth and position of the recess, thickness and doping of the different layers, etc. Historically, these parameters have been optimized by classical simulation techniques or, when such simulations are not physically applicable, by the expensive 'test and error' procedure. With the use of computer simulation, the design optimization can be made in a short time and with no money spent. However, classical modelling of electronic devices meets important difficulties when dealing with advanced transistors, mainly due to their small size, and the Monte Carlo technique appears as the only possible choice

We report the growth of high-mobility Si-doped GaN epilayers utilizing unique double buffer layer (DBL) structures, which consist of a thin buffer layer (TBL) and a thick GaN intermediate-temperature buffer layer (ITBL). In this study, three types of DBL were investigated: (i) thin low-temperature GaN buffer layer (LTBL)/GaN ITBL (type I); (ii) nitridated Ga metal film/GaN ITBL (type II); and (iii) AlN high-temperature buffer layer (HTBL)/GaN ITBL (type III). It is found that the electron mobilities of the GaN films are substantially improved with the use of DBLs. The sample grown using type II DBL has the highest room temperature electron mobility of 450 cm²V-1s-1, yet the sample grown with type III DBL exhibit the highest overall electron mobility of 520 cm²V-1s-1 at around 200K. The PL results show that the sample deposited on type III DBL exhibit the highest compressive stress at room temperature. The data suggest that the use of type III DBL leads to the relaxation tensile stress at the growth temperature resulting in the improvements in the crystallinity and defect properties. Due to the mismatch in the coefficients of expansion between GaN and sapphire the sample with the highest compressive stress at room temperature corresponds to the one with the lowest tensile stress at the growth temperature. It was shown that low tensile stress facilitates two-dimensional growth leading to improvements in the crystallinity and defect properties. This is supported by the experimental results of low-frequency noise measurements, which indicated substantial reduction in the flicker noise level as well as the elimination of deep-levels with the use of type III DBL.

The low frequency noise level is one of the key parameters, which determines the device potential for microwave applications. The fabrication of AlGaN/GaN HEMT on Si produces much more dislocations than on sapphire or SiC substrates. Therefore, it is important to analyse the influence of traps on the LF noise level of such devices. Devices under test are undoped AlGaN/GaN HEMT on silicon substrate. These non-passivated devices present gate geometries of 3.5μm by (2x75)μm and 1.5μm by (2x50)μm. At 300K, output characteristics Id-Vds present kink effect occurring at Vds around 6V and high values of Vgs. As this effect vanishes for temperature above 300K, deep traps are activated. LF drain noise measurements were performed in the ohmic regime. We have measured the low frequency drain noise spectral density :- for drain current of 2mA with Vgs varying from -2V to 0V, - for Vgs of 0V and -1V with Id from 2 to 6 mA. The dispersion of the drain noise level is about one order of magnitude difference. A typical spectrum is composed of 1/f noise which level is in the range of the ones measured on AlGaAs/GaAs HEMT and several generation-recombination components. Cut-off frequencies of G-R noise are typically lower than 100Hz. Therefore, the 1/f noise is screened by G-R noise at low frequencies and becomes preeminent for frequencies higher than 500Hz. The 1/f noise level verifies the Hooge relation. It is proportional to the square of Id. We have found that the α_H/N parameter (that is the normalized drain current spectral density fSid/Id²) is in the range of 3×10^-11 to 3×10^-10.

Low frequency noise measurements (f<10Hz) are a powerful tool for the investigation of the quality and reliability of electron devices and material. In most cases, however, the application of this technique is made quite difficult both because of the effect of external interferences (temperature fluctuations, EMI, mechanical vibrations, etc.) and because of the high level of flicker noise of the commercial instrumentation. In this paper the most remarkable results we obtained by using low frequency noise measurements for the characterization of the reliability of VLSI metallic interconnections and thin oxides are resumed. Moreover, we discuss the effects of the several sources of noise and interferences which contribute to reduce the sensitivity of the measurement chain. In particular, we demonstrate that by means of a proper design, dedicated instrumentation can be built which allows for a considerable reduction of the overall background noise. Examples will be given with reference to voltage and transresistance amplifiers (both AC and DC coupled), to programmable biasing systems (both current and voltage sources), to thermal stabilization systems and to data acquisition systems. Finally, we will discuss methods which may allow, in proper conditions, to accurately measure noise levels well below the background noise of the input preamplifiers coupled to the device under test. As the systems we discuss are characterized by moderate complexity and employ components readily available on the market, we trust that this paper may also serve as a simple guideline to anyone interested in exploiting the possibility of using very low frequency noise measurements by building his own instrumentation.

The low frequency noise (LFN) properties of the field-effect transistors (FETs) using polymers as the semiconducting material in thin-film transistor (TFT) structures are investigated and discussed in terms of the charge carrier transport. Results obtained from several research groups are summarized. Injection-drift limited model (IDLM) for charge transport in amorphous PFETs is discussed. IDLM has some advantages in comparison to the commonly used metal-oxide-semiconductor (MOS) transistor models. A general trend of proportionality between noise power density and the DC power applied to the polymer FET’s (PFET’s) channel is observed in the data from several research groups. This trend implies mobility fluctuation in PFET as the dominant noise source.

Low frequency noise characteristics of light-emitting diodes with InAs quantum dots in GaInAs layer are investigated. Two noise components were found in experimental noise records: RTS, caused by burst noise, and 1/f Gaussian noise. Extraction of burst noise component from Gaussian noise background was performed using standard signal detection theory and advanced signal-processing techniques. It was found that Hooge's empirical relation applied to diodes by Kleinpenning is applicable to the electric 1/f noise of quantum dot diodes as well. Two different spectra decomposition techniques are used to obtain burst noise spectra. Bias dependences of burst and 1/f noise are compared. It is concluded that the RTS noise and 1/f noise have different physical origins in light-emitting diodes with quantum dots.

Due to the enormous industrial interest of the SOI MOSFET technology, a proper understanding of the physics underlying the behavior of these devices is necessary in order to optimize their high frequency performance. In this work, we study the static, dynamic and noise characteristics of FDSOI MOSFET’s by means of numerical simulations validated by comparison with experimental data. For this purpose, we use a 2D Ensemble Monte Carlo simulator, taking into account, in an appropriate manner, the physical topology of a fabricated 0.25 μm gate-length FDSOI transistor. Important effects appearing in real transistors, such as surface charges, contact resistances, impact ionization phenomena and extrinsic parasitics are included in the simulation. This allows to accurately reproduce the experimental behavior of static and dynamic parameters (output and transference characteristics, gm/ID ratio, capacitances, etc.). Moreover, results are explained by means of internal quantities such as concentration, velocity or energy of carriers. The results of the Monte Carlo simulations for the typical four noise parameters (NFmin, Gass, Rn, \Gamma opt) of the 0.25 μm FDSOI MOSFET also show an exceptional agreement with experimental data. Once the reliability of the simulator has been confirmed, a full study of the noise characteristics of the device (noise sources, drain spectral densities, α, β and C parameters, etc.) is performed. Taking advantage of the possibilities of the Monte Carlo method as a pseudo-experimental approach, the influence on these noise characteristics of the variation of some geometry parameters (i.e., downscaling the gate length, thickness of the active layer or inclusion of HALO regions) is evaluated an interpreted in terms of microscopic transport processes.

Noise parameters of AlGaAs/GaAs and InGaP/GaAs HBTs were measured in microwave frequency range and modeled using the small-signal equivalent circuit approach. Correlated current noise sources in the base and collector currents with thermal noise in the circuit resistive elements were accounted for by the model and yielded good agreement with the measured data. This enabled an extraction of the different noise source contributions to minimum noise figure (NFmin) in AlGaAs/GaAs and InGaP/GaAs HBTs. Decomposition of the (NFmin) in to the different contributors showed that the main noise sources in investigated HBTs are correlated base and collector current shot noise. The observed minimum of NFmin versus frequency at lower collector current is explained by the reduction of the emitter/base junction shot noise component due to the spike in the emitter/base junction and associated accumulation of the quasi-thermalized electrons forming a space charge, which screens the electron transfer through the barrier. The bias (VCE) increase creates an efficient electric field in collector/base junction, capable of 'washing out' the accumulated charge. Such shot noise reduction in HBTs could be exploited in the LNA for the RF application.

The current-voltage characteristics and the low-frequency noise spectra of p-type Si - Porous Si - Al light emitting diodes were investigated. over 1 V forward biases a reasonable fit was obtained in the Fowler-Nordheim plot. At lower biases, however, an additional current-component appears, which shows a saturating character. This current component is ascribed to trap-assisted tunneling. Any attempts of accurately fitting the I-V characteristic by other known transport mechanisms failed, as reported earlier. The measured noise spectra show 1/f character. While the biasing current was varied from a about 30 microAmps up to several mAs, the noise level remained constant within the measuring error, i.e. the voltage noise is independent of the bias. This is contradictory to the results obtained on uniform resistors, where the noise power scales with I², or V². On this reason the observed noise is attributed to the saturating trap-assisted tunneling.

A model for the 1/f noise in passive components undergoing time-varying bias is proposed. One-port devices exhibiting 1/f noise are considered, e.g. carbon or polysilicon resistors. Starting from the Hooge’s formula, that holds when the component is operated under DC bias, it is shown that the noise current is simply proportional to the product between the conductivity fluctuation and the time-dependant voltage applied to the component. In other words, the 1/f noise in passive components under time-varying bias arises from the intermodulation between the stochastic process 'conductivity fluctuation' and the voltage applied to the component. Detailed calculations of both autocorrelation function and power spectrum of the resulting noise current are given; different time dependences of the voltage applied to the component are considered. Of particular relevance is the case of sinusoidal voltage; in this case the resulting noise current is a cyclostationary stochastic process and its behaviour can be conveniently described by the cyclic autocorrelation functions or by the cyclic power spectra. A circuit is built to measure the actual power spectra of the noise current of carbon resistors under constant or periodic voltage bias, in order to verify the results obtained from the proposed model. Very good agreement between theory and experiment is observed, and this fact supports the proposed model for 1/f noise in passive components under time-varying bias. The conclusion is that the physical origin of 1/f noise in passive components does not depend on external bias, nor in DC nor when a time-varying signal is applied to the component.

InAlAs/InGaAs HEMTs have demonstrated exceptional performance for low-noise high-frequency applications. However they have still some drawbacks to be removed, like the kink effect, which limits their applications by leading to a decrease in the gain and an enhancement in the noise level for high-enough values of the drain-to-source voltage. This effect is typically associated with the pile up of holes (generated by impact ionization) in the source-gate portion of the channel. In this work we investigate the noise properties of a 100 nm T-gate recessed In_0.52Al_0.48As/In_0.53Ga_0.47As HEMT in the presence of kink effect. For the calculations we make use of a 2D ensemble Monte Carlo (MC) simulator that incorporates all the microscopic processes at the basis of this effect. Impact ionization, which leads to the appearance of holes responsible for the kink, is included using the Keldysh approach with parameters adjusted to reproduce the impact ionization coefficients in bulk materials. Hole recombination is also considered, with a characteristic time τ ranging between 0.01 and 1 ns. The accumulation of holes in the source-gate region leads to a decrease of the potential barrier controlling the current through the channel, which is further opened and, as a consequence, the drain current increases. This phenomenon appears accompanied by a significant raise of the noise in the device that spoils its performance. The aim of this work is to analyze this excess noise and explain its physical origin by means of MC simulations. Impact ionization and hole trapping mechanisms lead to fluctuations of the hole concentration in the channel. Since these fluctuations are strongly coupled to the drain-current fluctuations by the high transconductance of the transistor, with the onset of the kink effect an important increase of the noise takes place, with a characteristic cutoff frequency related to the impact ionization rate and the hole recombination time. This is clearly observed in the calculated current correlation functions and corresponding spectral densities, that will be presented at the conference.

Phase noise models that describe the near-carrier spectrum in an accurate but insightful way are needed, to better optimize the oscillator design. In this paper we present a model to describe the effect of flicker noise sources on the phase noise of an oscillator, that can be applied both to linear oscillators and to nonlinear structures like relaxation and ring oscillators, so extending previous works that considered only the effect of the flicker noise superimposed to the control voltage of a VCO. In the phase noise of an oscillator we can separate the effect of high frequency noise sources, that can be described by a short-time-constant system, and the effect of low frequency noises (mostly flicker sources), described by a system with time constants much slower than the oscillation period. Flicker noise has been considered to cause a change in the circuit bias point; this bias point change can be mapped in a shift of the oscillation frequency by exploiting Barkhausen conditions (for linear oscillators) or obtaining this link by simulations. The power spectral density of the oscillator can then be obtained as the probability distribution of the oscillation frequency, starting from the flicker noise probability distribution. If the effect of high frequency noise sources is also taken into account, the overall oscillator spectrum can be obtained as a convolution of the spectrum due to flicker sources with the Lorentzian-shaped spectrum due to white noise sources, in analogy with the description of inhomogeneous broadening of laser linewidth.

Hooge'e empirical equation has been widely used to describe l/f or flicker noise in electron devices, where the characteristics of different devices are represented by Hooge's parameter. There have been various explanations for l/f noise and theories used to calculate Hooge's parameter. We present here an alternative interpretation of Hooge's empirical equation based on temperature fluctuations in electron devices. The concept of temperature fluctuations about a steady state equilibrium value is not only expected but in itself not new, temperature is only an average value. We employ a detailed balance description of heat flux to and from a heat sink and frequency dependent solutions to the diffusion equation where the high frequency variations are strongly attenuated to describe these temperature fluctuations. This method follows our previous treatment of temperature fluctuations and noise in electron devices with high power dissipation by transmission line techniques. Temperature variations even with very low power dissipation and at thermal equilibrium can modulate the conductivity of semiconductor layers and channel's of JFET's and HEMT's. A description of Hooge's empirical equation is given by these temperature fluctuations and Hooge's parameter is shown to be simply related to the ratio of the total number of conduction electrons and total number of atoms in the sample. This new, simple and practical understand of l/f noise suggests that appropriate heat sinks are required to minimize l/f noise and consequently phase noise and timing jitter in high frequency and high speed electronic systems.

The established description of linear, noise-generating systems in electronics uses mathematical techniques which were originally designed for linear, time-invariant systems. Noise spectra are often extracted from model descriptions in the time-domain by application of the Fourier-transform to the autocorrelation function of the output signal. Recently, it was pointed out that this description might be incomplete, since the parameters of noise-generating systems fluctuate, i.e. they vary with time. Therefore, the theory of linear time-variant systems (LTV-systems) should be applied rather than the theory of time-invariant systems. This was done for a very simple linear two-pole system. It turned out that even in this simple system novel, unexpected parts of the spectrum appeared in the output signal. In the submitted paper, this theory is expanded to linear, noise-generating four-poles and other n-ports. The mathematics of LTV-systems are well known since the fifties. It appears, however, as if their application to fluctuating noise-generating systems were limited to the analysis of narrow-band noise in the transmission channels of radio-links. The theory will, therefore, be adapted to electronic circuits which are fed by noise, and which have inner noise sources. It will be applied to a simple model of an integrated ohmic resistor in order to show the (so far unexpected) effect of the time-variance of parameters to the noise spectrum.

Linear, noise-generating systems in electronics are usually described by mathematical techniques which were originally designed for linear, time-invariant systems, e.g. output noise spectra are computed by application of the Fourier-transform to the autocorrelation function of the output signal. Recently, it was pointed out that this description might be incomplete, since the parameters of noise-generating systems fluctuate, i.e. they vary with time. Therefore, rather than using the theory of time-invariant systems, the theory of linear time-variant systems should be applied. This theory will be adapted to electronic circuits which are fed by noise, and which have inner niose soruces. It will be applied to simple electronic circuits like a simple equivalent circuit of an integrate ohmic resistor, in order to show the effect of the time-variance of parameters to the noise spectrum.

The noise performance of sub-quarter micrometer gate length FETs is determined by using physical simulators. The hydrodynamic transport model equations are linearized and efficiently solved in two dimensions to determine the small-signal parameters and the minimum noise figure up to frequencies near the device cut-off frequency. For higher frequencies, the noise performance is obtained by using a 2D Monte Carlo code which fully takes into account the non-stationary transport properties and quantization effects. The relation between the terminal noise currents and the internally generated noise at the different device regions are determined. Different device stuctures are simulated and the obtained results are compared with experimental data.

The aim of this work was to optimize the shape of the cross-shaped Hall devices with regard to noise generated on sensing contacts. We have performed systematical experimental and numerical study of the influence of the geometry of the cross shaped Hall devices on the electrical low frequency noise measured on the sensing and driving current contacts. Based on our numerical calculations of the current density distribution (Finite Elements Method) we have designed several samples with various geometry/shape and dimensions in the 10 μm-200 μm range. Hall devices were fabricated on GaAs-based pseudomorphic heterostructures. Presented experimental results are in good agreement with our calculations of the noise power density based on electrical network theory and references therein. These results enable us to optimize the geometry of the devices giving us in the best case the reduction of the low frequency noise power density by ca -10 dB as compared to a standard Greek cross of identical size. This purely geometrical effect is independent of the sample physical structure and depends only on the sample shape. These results can be applied to any planar Si or III-V based semiconductor Hall device.

A physically-based transient microplasma based model for low frequency noise in pn diodes is discussed and implemented in SPICE simulator. The simulation indicates that the model correctly describes the non-monotonic behavior of both the DC and the noise characteristics of diode at the onset of avalanche breakdown. Since the model is based on a new microplasma switching theory, the results of simulation confirm the findings of this theory. These are, as follows for the microplasma. Its switching threshold is the condition of equality of free- to space charge concentration in depletion layer. Its on-current is approximately twice the threshold current. It is initialized by the charge generation due to few recombination centers in microplasma region at high avalanche multiplication due to impact ionization, while the microplasma turn-off is due to carrier diffusion from microplasma region into the depletion layer at low, but larger than 1, avalanche multiplication.

Three standard 1/f noise models for MOSFETs are actually implemented in software packages: SPICE, HSPICE and recently BSIM3v3l. The aim of this paper is to show the limitation of each of these implementations by comparison between noise simulations and noise measured data. We demonstrated that 1/f noise model implemented in SPICE and HSPICE can not predict correctly noise in all operating regimes which limit their usefulness for design purposes. We show that BSIM3v3 allows the better fitting with experimental noise results in all operating regimes.

Random noise radar is rapidly emerging as a promising technique for high-resolution probing and imaging of obscured objects and interfaces. The University of Nebraska-Lincoln has developed and field-tested coherent ultra wideband polarimetric random noise radar systems that show great promise in their ability to estimate Doppler and image target and terrain features. Theoretical studies and extensive field tests using these systems confirm their ability to respond to and utilize phase information from the received signals. This paper summarizes our recent developments in coherent random noise radar imaging and discusses future research directions in this area.