Lithographic technology has progressed through a number of "waves," beginning with contact printing and progressing to today's DUV step-and-scan exposure methods. Measurement capabilities have also evolved commensurate with changes in the exposure technology and feature sizes. The greatest measurement challenges today are related to gate CD control requirements, as these have been greatly accelerated during the past 10 years. Scatterometry represents a new method that may help to address this need, but something else is likely required for measurement of line-edge roughness (LER). More direct measurements of parameters such as lens aberrations, are also required. Overlay measurement will also be challenged to meet the needs of future lithographic technologies, and solutions must address the interplay between lens aberrations and overlay errors. Next-generation lithographic technologies will require a host of new metrology capabilities, and the late availability of the means for measurement could delay the introduction of the new technologies.

Because a photomask is typically a block of quartz partially covered a thin metal coating it charges significantly under an electron beam making CD metrology difficult and often imprecise. A solution to this problem can be found by performing the measurement in the presence of a low pressure of gas in a variable pressure scanning electron microscope (VPSEM). The gas is ionized by the emitted secondary electrons so producing both positive and negative ions which drift to the charged surface and neutralize it. This process is self controlling and requires no critical adjustments by the operator. With charging removed metrology can then be performed over a wide range of beam energies using either secondary or backscattered electron signals with excellent precision and accuracy. The presence of the gas atmosphere also eliminates beam induced contamination effects. If a chemically active precursor gas is injected into the system then the electron beam can also be used to edit and repair damaged masks.

Phase shift techniques introduced in photolithography to further improve resolution produce a new set of challenges for inspection. Unlike the high contrast provided by patterned and unpatterned areas on a binary mask, phase errors do not provide significant contrast changes, since the phase change is imparted by a difference in material thickness. Surface topology measurements can be used to identify phase defects, but methods for surface topology inspection are typically slow or can damage the surface to be measured. In this study, Spatial Heterodyne Interferometry (SHI) has been considered as a possible method for high-speed non-contact phase defect detection. SHI is an imaging technique developed at Oak Ridge National Laboratory that acquires both phase and amplitude information from an optical wavefront with a single high-speed image capture. Using a reflective SHI system, testing has been performed with a mask containing programmed phase defects of various sizes and depths. In this paper, we present an overview of the SHI measurement technique, discuss issues such as phase wrapping associated with using SHI for phase defect detection on photolithographic masks, and present phase defect detection results from die-to-die comparisons on a 248 nm alternating aperture phase shift mask with intentional phase defects.

We report on the metrological characterization of photomask standards which were developed within a project with industrial partners in Germany to be used as reference standards for different type of linewidth or CD metrology instruments. It was the objective to develop high quality mask standards which would allow to perform CD calibrations with smallest possible uncertainties and to use the standards within the project consortium as well as to make the standards available to interested third parties. The design of the standards consists of line as well as box structures, isolated as well as group patterns, each in different tones and in x/y-orientation. The structures are all placed on a regular measurement grid to be easily accessible by automated CD metrology systems. Target CD values are going down to 0.2 μm with smallest CD steps of 20 nm and line to space ratio within groups is varied between 1:1 and 1:5. Additionally, there are larger CD structures and clear fields and different pitch structures on the mask. This contribution will concentrate on the description of the methods and instrumentation used at the PTB for investigation and calibration of the standards. Different methods of optical transmission microscopy as well as low energy scanning electron microscopy and scanning probe microscopy were applied which all were developed to provide traceable linewidth calibration values. This implies, that suitable physical models for the interaction of the different probes with the photomask structures had to be developed for a meaningful interpretation of the measurement signals for all type of CD metrology methods. This analysis also has to take into account the influences of structure imperfections, like edge slope and line edge roughness.

This paper introduces the capability of measuring overlay (OL) errors (current level to prior level errors and neighboring field errors) and critical dimension (CD) errors simultaneously on a Critical Dimension Scanning Electron Microscope (CD SEM). In the past OL errors and CD errors have been measured on different tools sets. CD errors have always been measured on SEMs and OL errors have always been measured on optical tools. In both cases, measurements were obtained on separate target designs. The key to this paper is in the design of the targets. We combine, in one target design, the ability to extract OL and CD errors simultaneously. Current OL targets designs are limited by the resolution of that type of tool which is on the order of 1um, this means that current OL target designs are created at ground rules larger than this (typically 2-3um in size) and at ground rules much larger than the circuit design. A target design that allows the OL and CD to be measured at the ground rules of the circuit would be a much more desirable measurement and takes advantage of the SEM's strengths which include resolution. Additionally, a target design that allows current level to prior level OL, neighboring field OL and CD errors to be measured simultaneously would be extremely desirable. The key is designing the targets for cases where prior level information can be seen on the SEM, this can be performed on many levels throughout chip construction, probably more than half of all levels. This methodology will significantly reduce the time it takes to build parts, improve technical performance and save tool cost.

We describe an approach to pattern metrology that enables the simultaneous determination of critical dimensions, overlay and film thickness. A single optical system captures nonzero- and zero-order diffracted signals from illuminated grating targets, as well as unpatterned regions of the surrounding substrate. Differential targets provide in situ dimensional calibration. CD target signals are analyzed to determine average dimension, profile attributes, and effective dose and defocus. In turn, effective dose and defocus determines all CDs pre-correlated to the dose and focus settings of the exposure tool. Overlay target signals are analyzed to determine the relative reflectivity of the layer pair and the overlay error between them. Compared to commercially available pattern metrology (SEM, optical microscopy, AFM, scatterometry and schnitzlometry), our approach promises improved signal-to-noise, higher throughput and smaller targets. We have dubbed this optical chimera MOXIE (Metrology Of eXtremely Irrational Exuberance).

Although lithography equipment and alignment capabilities have evolved significantly since the early stepper days of the 1980’s, the techniques for generating overlay mix and match matrices have remained virtually unchanged. The underlying assumption for traditional mix and match matrices is that the lens signature is the dominant influence in total overlay, and that metrology errors need to be averaged out of the raw data. As step and scan systems were introduced in mid 1990s, improved lens quality has reduced the lens signature errors significantly. However, improvements in stepping accuracy and precision did not keep pace with the rapid reduction in lens distortions. As a result, lens distortion signatures, combined with stepping and scanning repeatability issues, render the traditional “lens distortion matrix” methods for generating mix and match matrices invalid. In this paper several metrology sampling layouts were generated, and demonstrated that with appropriate sampling across known degrees of freedom, it is possible to create a mix and match matrix and modeling more appropriate for 65 nm node alignment tolerances. The mix and match approach captures worst case overlay errors in the matching matrix, and also identifies the root causes of the mix and match error sources between scanners.

Optical methods are often thought to lose their effectiveness as a metrology tool beyond the Rayleigh criterion. However, using advanced modeling methods, the conventional resolution limitations encountered in well-defined edge-to-edge measurements using edge thresholds do not apply. In fact, in this paper we present evidence that optics can be used to image and measure features as small as 10 nm in dimension, well below the imaging wavelength. To understand the limits of optical methods we have extensively studied both linewidth and overlay metrology applications. Although overlay applications are usually thought to involve pitch or centerline measurements of features from different process levels, some target designs present optical proximity effects which pose a significant challenge. Likewise, line width measurements require determination of the physical edges and geometry which created that profile. Both types of measurements require model-based analysis to accurately evaluate the data and images. In this paper we explore methods to optimize target geometry, optical configurations, structured illumination, and analysis algorithms with applications in both critical dimension and overlay metrology.

One of the contributions to pattern placement/misalignment may come from the mask making process itself, in chromeless masks. This contribution will be important at 90 nm and smaller nodes. Hence it is necessary to estimate this contribution and find ways to minimize this. In this paper an effort has been made to measure this misalignment accurately. A series of box in box structures for overlay measurement, on KLA and CD SEM, were designed on the reticle. The structures had an outer box of etched chrome and an inner box with 180 degree phase. The edge of the chrome was used as the edge of the outer box. The line printed at the phase intersection was used as the edge of the inner box. Each of these structures were put in with a pre-determined value of X and Y misregistrations. The CD SEM structures were smaller in size but designed the same way as KLA structures. Such structures were put at 4 corners of the die. Overlay measurements were carried out using the optical overlay machine as well as CD SEM. An average misalignment of 11 nm and 1 nm were found in the X and Y directions respectively. When the results from each die corner was analyzed, it was found that the X misalignment had two different distributions. Also, exposure parameters such as focus and partial coherence for best misalignment measurement points were investigated. It is concluded that for obtaining accurate misalignment data, measurements should be conducted at a focus where the two opposite phase edges pattern at similar width. Also, a higher partial coherence is recommended as aberrations such a coma have more profound influence at lower partial coherence and this could contaminate the true misalignment data.

Recently the overlay accuracy has got seriously severe. For the accurate overlay, signal intensity and waveform from the topographical alignment mark has been examined by signal simulation. Actually these results have given good agreements with actual signal profiles, but it is difficult to select particular alignment marks in each mask level by the signal simulation. Even after mass production, many mark candidates leave in kerf area. To help the selection, we propose a mark TCAD system. It is a useful system for the mark selection with the signal simulation in advance. In our system, alignment mark signal can be very easily simulated after input of some process parameters and process of record (POR). The POR is read into the system and a process simulator makes stacked films on a wafer. Topographical marks are simulated from the stacked films and the resist pattern. The topographical marks are illuminated and reflected beams are produced. It is simulated how the reflected beams are imaged through inspection optics. We show two applications. This system is not only to predict and show a signal waveform, but also helpful to find optimum marks.

The downscaling of IC design rule has increasingly imposed tighter overlay tolerances together with high cost of lithography equipment. Foundries are required to optimize tools utilization in order to be cost effective. To run with the same process flow using different exposure tools, the effect of the different process parameters needs to be characterized. This paper explores the feasibility of using the same W-CMP process for two different alignment systems employing different alignment marks. An evaluation of the alignment performance was done using marks placed in the scribe line of Tower’s products. Exposures were performed using two different DUV scanners at BEOL layers, with process splits performed prior to the W-CMP phase. Robustness of alignment mark is critical, as the scanner’s alignment system requires accurate signal to precisely align a pattern layer to a pervious layer. Data taken by the scanners on various tool/mark/recipe combinations is analyzed to provide indication of the overlay performance robustness to the process parameters. To investigate the effect of different W-CMP processes on alignment marks in back-end processing, an evaluation was performed through which both mark design and process parameters were varied. The robustness of typical long-term process variation at the W-CMP step in a production environment was evaluated.

With the refined lithography techniques that exist today, it is critical for overlay measurement tools to perform with great measurement precision. Tool induced shift, TIS, is one of the key factors taken into consideration when evaluating the performance of an overlay measurement tool. TIS can be observed as a numerical value, and the measurement value is corrected by the TIS value. However, in an overlay measurement tool with TIS, the measured values could be shifted due to an interaction between TIS and a film stack structure of wafer. Therefore, it is essential to minimize the TIS values. We extend our study on the lens surface aspheric error, which is known to be one of the root causes of TIS. As this point of view, we constructed our overlay measurement tool, NRM-3100, and were able to decrease TIS values.

Perhaps never before in semiconductor microlithography has there been such an interest in the accuracy of measurement. This interest places new demands on our in-line metrology systems as well as the supporting metrology for verification. This also puts a burden on the users and suppliers of new measurement tools, which both challenge and complement existing manufacturing metrology. The metrology community needs to respond to these challenges by using new methods to assess the fab metrologies. An important part of this assessment process is the ability to obtain accepted reference measurements as a way of determining the accuracy and Total Measurement Uncertainty (TMU) of an in-line critical dimension (CD). In this paper, CD can mean any critical dimension including, for example, such measures as feature height or sidewall angle. This paper describes the trade-offs of in-line metrology systems as well as the limitations of Reference Measurement Systems (RMS). Many factors influence each application such as feature shape, material properties, proximity, sampling, and critical dimension. These factors, along with the metrology probe size, interaction volume, and probe type such as e-beam, optical beam, and mechanical probe, are considered. As the size of features shrinks below 100nm some of the stalwarts of reference metrology come into question, such as the electrically determined transistor gate length. The concept of the RMS is expanded to show how multiple metrologies are needed to achieve the right balance of accuracy and sampling. This is also demonstrated for manufacturing metrology. Various comparisons of CDSEM, scatterometry, AFM, cross section SEM, electrically determined CDs, and TEM are shown. An example is given which demonstrates the importance in obtaining TMU by balancing accuracy and precision for selecting manufacturing measurement strategy and optimizing manufacturing metrology. It is also demonstrated how the necessary supporting metrology will bring together formerly unlinked technology fields requiring new measurement science. The emphasis on accuracy will increase the importance and role of NIST and similar metrology organizations in supporting the semiconductor industry in this effort.

The measurement of line-edge roughness (LER) has recently become a topic of concern in the litho-metrology community and the semiconductor industry as a whole. The Advanced Metrology Advisory Group (AMAG), a council composed of the chief metrologists from the International SEMATECH (ISMT) consortium’s Member Companies and from the National Institute of Standards and Technology (NIST), has a project to investigate LER metrics and to direct the critical dimension scanning electron microscope (CD-SEM) supplier community towards a semiconductor industry-backed, standardized solution for implementation. The 2003 International Technology Roadmap for Semiconductors (ITRS) has included a new definition for roughness. The ITRS envisions root mean square measurements of edge and width roughness. There are other possible metrics, some of which are surveyed here. The ITRS envisions the root mean square measurements restricted to roughness wavelengths falling within a specified process-relevant range and with measurement repeatability better than a specified tolerance. This study addresses the measurement choices required to meet those specifications. An expression for the length of line that must be measured and the spacing of measurement positions along that length is derived. Noise in the image is shown to produce roughness measurement errors that have both random and nonrandom (i.e., bias) components. Measurements are reported on both UV resist and polycrystalline silicon in special test patterns with roughness typical for those materials. These measurements indicate that the sensitivity of a roughness measurement to noise depends importantly both on the choice of edge detection algorithm and the quality of the focus. Measurements are less sensitive to noise when a model-based or sigmoidal fit algorithm is used and when the images are in good focus. Using the measured roughness characteristics for UV resist lines and applying the ITRS requirements for the 90 nm technology node, the derived expression for sampling length and sampling interval implies that a length at least 8 times the node (i.e., 720 nm) must be measured at intervals of 7.5 nm or less.

One of the many technology decisions facing the semiconductor industry for the 45 nm node (and beyond) is the selection of the best critical dimension (CD) metrology equipment to meet the needs of process equipment suppliers and semiconductor manufacturers. In an effort to address this need we fabricated advanced metrology structures using the Nanowriter e-beam writing tool at the Center for X-Ray Optics (CXRO) at Lawrence Berkeley National Laboratory. The structures include lines and holes both in resist and etched into substrates. The smallest isolated CDs are 16 nm, while the smallest holes are less than 50nm. We used these samples to characterize a variety of metrology technologies. In this paper we discuss the capability of those technologies to measure structures having dimensions representative of the 45 nm and 32 nm nodes.

CD-SEM and scatterometry are two of the top candidates for CD metrology in 90 nm node. In this study, Optical Digital Profilometry (ODP) based scatterometry was used to evaluate four topics: CD SEM and ODP process resolution comparison, ODP duty ratio limitation study, Poly AEI undercut sensitivity, STI ODP to TEM profile and trench depth matching. The scatterometry results were compared to CD-SEM and TEM results to develop the correlation of different metrology techniques. Scatterometry is able to provide robust uniformity measurement with additional information compared to CD-SEM. The additional information included sidewall angle, photoresist thickness, A°RC layer thickness, and under-layer film thickness. Actual data showed that this extra information was essential to trouble shoot the CD uniformity issue, separate the scanner, track, and thin film deposition impact on final CD uniformity. Scatterometry can be used not only as a metrology tool to measure CD uniformity, but also a useful analytical tool to find out the cause of CD non-uniformity. In small FEM study, scatterometry demonstrated its high resolution and precision. It can clearly identify the CD shift of less than 0.5 nm with exposure energy shift of 0.1mJ. This high resolution enabled a clearer definition of process window, and monitoring of small process shift in the actual production. From the experimental results, current optical tool with ODP technology was well qualified for duty ratio > 30 iso line measurement, detecting Poly undercut, STI profile and depth TEM matching.

For 90 nm technology and below, we need to fight for every nanometer to improve the CD uniformity (CDU). New materials, especially for low-k material, bring about not only complicated integration challenges, but also new metrology difficulties such as SEM image focus failure if using low landing energy (300V) on charging wafer (e.g. -300V). The wafer global charging will also distort the CD SEM magnification and result in CD measurement error. CD SEM venders propose that the distortion be corrected by voltage contrast focus. In order to compare and quantify the measurement error correction with and without using retarding voltage focus, ArF resist non-uniform charging wafers (~ -300V) and low charging wafers (~ -7V) were prepared. Low landing energy like 300V is one of the solutions for ArF resist shrinkage. However, as the low landing energy (300V) meets the high global charging wafer (-300V), SEM cannot get sufficient secondary electron signal to construct image. Therefore, two landing voltages 500eV and 800eV were chosen for the evaluation. Three pitches 1600 nm, 460 nm and 230 nm were investigated. Two indexes are used to evaluate the wafer global charging effect on CD and CDU. One is within-wafer pitch uniformity for determining the CD SEM magnification error. The other is ArF-resist-shrinkage amplitude used to estimate the effective landing energy at charging area. The experimental results show that the pitch uniformity difference with and without using retarding focus can be larger than 2.5 nm. Similar phenomenon is also found for the line width uniformity. Resist shrinkage amplitude is significantly reduced at the highly charged area. Both results show that accurate focus procedure, i.e. retarding voltage focus employing first, is the key to reduce the CD metrology tool measurement error and improve CDU.

The widths of 284 lines in a 193 nm resist were measured by two methods and the results compared. One method was scanning electron microscopy (SEM) of cross-sections. The other was a model-based library (MBL) approach in which top-down CD-SEM line scans of structures are compared to a library of simulated line scans, each one of which corresponds to a well-defined sample structure. Feature edge shapes and locations are determined by matching measured to simulated images. This way of determining critical dimensions makes use of known physics of the interaction of the electron beam with the sample, thereby removing some of the ambiguity in sample edge positions that are assigned by more arbitrary methods. Thus far, MBL has shown promise on polycrystalline silicon samples [Villarrubia et al., Proc. SPIE 4689, pp. 304-312 (2002)]. Resist lines, though important in semiconductor manufacturing, pose a more difficult problem because resist tends to shrink and charge upon electron beam exposure. These phenomena are not well characterized, and hence are difficult to include in the models used to construct libraries. Differences between the techniques had a systematic component of 3.5 nm and a random component of about 5 nm. These differences are an upper bound on measurement errors attributable to resist properties, since they are partly attributable to other causes (e.g,. linewidth roughness).

In the present paper, we use a new photo goniometric method capable to measure the entire diffracted pattern of a sub micron grating at fixed wavelength very rapidly. The complete reflectance pattern is obtained versus incidence angle (0-80°) and azimuth angle (0-360°). Regression software based on RCWA simulations has been developed. It is used to adjust automatically the grating profile with an unprecedented rapidity. Regressions have been applied to our polarimetric measurements versus incidence angle θ and versus azimuth angle φ. Results are compared to those provided by spectroscopic ellipsometry (SE) and scanning electron microscopy (SEM). We show that fixed incidence angle specular reflection coefficients versus azimuth angle R(φ) curves are very sensitive to the profiles especially when the CD is reduced mainly because of the occurrence of diffracted orders matching the CD at given azimuths even if the wavelength is much larger than the CD. Mid space illumination measurements in a large angular aperture (0<θ<80° and 0<φ<180°) can be also used to deduce profile information. We show that specular reflection coefficients can be fitted in the entire angular aperture to provide precise structural shapes. Out of specular contribution which is measured simultaneously can also be used in the analysis. We show that it is more sensitive to the grating imperfections than the specular contribution.

Isolated and dense patterns were formed at process layers from gate through to back-end on wafers using a 90 nm logic device process utilizing ArF lithography under various lithography conditions. Pattern placement errors (PPE) between AIM grating and BiB marks were characterized for line widths varying from 1000nm to 140nm. As pattern size was reduced, overlay discrepancies became larger, a tendency which was confirmed by optical simulation with simple coma aberration. Furthermore, incorporating such small patterns into conventional marks resulted in significant degradation in metrology performance while performance on small pattern segmented grating marks was excellent. Finally, the data also show good correlation between the grating mark and specialized design rule feature SEM marks, with poorer correlation between conventional mark and SEM mark confirming that new grating mark significantly improves overlay metrology correlation with device patterns.

Scatterometry is now an accepted technique for linewidth measurement in semiconductor manufacturing. To reduce the evaluation time when using real-time optimization procedures, we introduce an effective-medium approach to simulate the optical signatures of subwavelength line-and-space gratings. Such gratings behaves approximately like uniaxial crystals whose optical properties are completely described by two refractive indices. We propose an algebraic method for their calculation up to second order in pitch/wavelength for the extraordinary index, and up to 4th order in pitch/wavelength for the ordinary index. The formulas are valid for any angle of incidence and can be used with standard matrix formalism to calculate the optical properties of any arbitrary layer stack. We deduce the formulas for the indices. The comparison of effective medium-calculations to rigorous coupled wave simulations for spectral measurements (polarized reflectometer and spectroscopic ellipsometer) shows excellent agreement. The sensitivity of scatterometry to tilt of the structures is very low for all measurement parameters except phase difference. It is shown that left and right tilt cannot be distinguished at all with spectral measurements with non-conical incidence of light.

Of the many parameters used in characterizing the performance of a CD-SEM, resolution is one of the more difficult to define and measure. Most of the evaluation techniques heretofore applied are prone to operator bias, making comparisons between different machines, and even long-term monitoring of the same machine, difficult. The technique presented here is based on the common method of obtaining a “contrast” versus spatial frequency curve, or modulation transfer function, by calculating the two-dimensional Fourier transform of an SEM image. The resolution is defined, similar to the Sparrow method in light optics, as the point at which the signal contrast goes to zero, coincident with the highest passable spatial frequency, a somewhat less arbitrary definition than that of Rayleigh. The crux of the method is in the techniques used to extract the data from the noise to obtain this zero crossing point. This paper both describes the significance, and presents the procedure, for a “one-click” method of evaluating resolution. The algorithm relies on methods of numerical, rather than image, analysis, with averaging and smoothing techniques used to circumvent the often large inherent signal-to-noise ratio, thereby obtaining more consistent results than previous methods; such as measuring spaces between objects, calculating amplitude ranges (e.g., 10-90, 20-80, or 25-75), or matching contours to Fourier transform cutoffs by eye. The method has also been found to be less sensitive to image brightness and visual contrast differences than these and some more sophisticated methods. The processing methodology; including flat top-Gaussian windowing, frequency specific averaging, and extrapolated smoothing techniques; used to minimize or eliminate transform artifacts, signal processing bandwidth limitations, and signal-to-noise issues; respectively, are described.

The requirement for state-of-the-art performance by overlay metrology at the 65nm technology node drives the development and design of new optical metrology solutions. The use of measurement modeling is increasing, affecting the tool concepts, tolerances, and calibrations, as well as the overlay target design. In this article, we present our overlay metrology simulation platform, developed in-house, and its central role in optical performance modeling. The simulation validation tests are presented using standard overlay test wafers. The impact of residual optical aberrations with different overlay targets is simulated, emphasizing the degree of control needed to support overlay measurement methodology.

The control and minimization of resist line edge (or width) roughness (LER or LWR) is increasing in importance. It requires first a complete and reliable characterization scheme of LER, including frequency dependency, and then an investigation and understanding of its origins and methods for improvement. A new characterization method, introduced by Demokritos and based on the offline analysis of top-down SEM pictures, has been evaluated and compared to more conventional inline measurements. This enables us to include additional parameters that quantify the spatial aspects of LER, next to the classical LER 3σ value. The spatial frequency dependence can also be determined from the inline measurements. Both techniques are applied to several test cases: the impact on LER of changing softbake (SB) and post-exposure bake (PEB) temperature, and changing aerial image contrast (AIC). Also, the improvements in an etch optimization experiment are quantified. The majority of the work is concentrating on 193nm resists, but initial experiments with a 157nm resist will be shown. This work has led to a better understanding of some of the contributors to line edge roughness and gives the possibility to quantify process improvements in a better way.

This paper describes a novel approach to improving across-wafer CD uniformity through the litho-etch sequence. Our approach is to compensate for systematic CD perturbations by employing all available control authority though the litho-etch process sequence. In particular, we find that the most effective control input for regulating spatial variations in CD is found in the post exposure bake (PEB) process step. More precisely, we construct offset models that relate the PEB temperature profiles of multi-zone bake plates to their zone offsets using wireless, in-situ temperature sensors from OnWafer Technologies. A second model relating across-wafer CD to PEB bake plate zone offsets is then identified from CD data measured by CD-SEM. The CD-to-offset model and the temperature-to-offset model are used with knowledge of the resist sensitivity to determine optimal bake plate zone offsets which minimize post-etch CD variation. This is done using constrained quadratic optimization techniques. Partial experimental work and simulation results show the promise of our approach. We demonstrate through simulation that across-wafer CD variation can be significantly reduced for 150nm technology node and beyond.

The on-chip variation (OCV) should be critically controlled to obtain the high speed performance in logic devices. The variation from proximity dominantly contributes to OCV. This proximity effect can be compensated by applying well-treated optical proximity correction (OPC). Therefore, the accuracy of OPC is needed, and methods to enhance its result have to be devised. The optical proximity behaviors are severely varied according to the material and optical conditions. In point of material, the proximity property is affected by species of photo-resist (PR) and change of post exposure bake (PEB) conditions. 3σ values of proximity variation are changed from 9.3 nm to 15.2 nm according to PR species. Also, proximity variations change from 16.2 nm to 13.8 nm is observed according to PEB condition. Proximity variations changes of 11.6 nm and 15.2 nm are measured by changing the illumination condition. In order not to seriously deteriorate OPC, these factors should be fixed after the OPC rules are extracted. Proximity variations of 11.4 nm, 13.9 nm and 15.2 nm are observed for the mask mean-to-targets (MTT) of 0 nm, 2nm, and 4nm, respectively. The decrease the OPC grid size enhances the correction resolution and the OCV is reduced. The selective bias rule is generated by model using grid size of 1 nm and 0.5 nm. For the nominal CD of 87 nm, proximity variations are measured to be 14.6 nm and 11.4 nm for 1 nm and 0.5 nm grid sizes, respectively. The enhancement amount of proximity variations are 9.2 nm corresponding to 39% improvement. The CD uniformity improvement for adopting the small grid size is confirmed by measuring the CD uniformity on real SRAM pattern. CD uniformities are measured 11nm and 9.1nm for grid size of 1 nm and 0.5 nm, respectively. 22% improvement of the CD uniformity is achieved.

In addition to being more accurate and non-destructive compared to CD-SEM metrology, scatterometry provides more information that is usable for Advanced Process Control (APC). The integrated Optical Digital Profilometry (iODP) scatterometry tool included in the TEL Clean Track product line is designed to give not only a quick in-line pattern characterization but also to allow possible identification and correction of the parameters responsible for the process variation. In the case of a trapezoidal approximation of the resist profile, three partially independent responses such as top CD, sidewall angle and height of the pattern are available. If the process drifts, it is likely that the pattern shape will behave differently depending on the parameter responsible for the variation. A design of experiment was run on a 100nm process with different resist softbake (PAB), exposure, focus and post-exposure bake (PEB) conditions. The data measured by iODP was then analyzed using a multivariate technique. A Projection to Latent Structures (PLS) model was built between the processing conditions and the profile measurement enabling the separation of three groups of profile variation. Additional experiments have shown that variations of bottom antireflective thickness can be separated from the other process parameters.

As critical-dimension shrink below 0.13 μm, the SPC (Statistical Process Control) based on CD (Critical Dimension) control in lithography process becomes more difficult. Increasing requirements of a shrinking process window have called on the need for more accurate decision of process window center. However in practical fabrication, we found that systematic error introduced by metrology and/or resist process can significantly impact the process window analysis result. Especially, when the simple polynomial functions are used to fit the lithographic data from focus exposure matrix (FEM), the model will fit these systematic errors rather than filter them out. This will definitely impact the process window analysis and determination of the best process condition. In this paper, we proposed to use a calibrated first principle model to do process window analysis. With this method, the systematic metrology error can be filtered out efficiently and give a more reasonable window analysis result.

The National Institute of Standards and Technology (NIST) is currently developing a photomask linewidth standard (SRM 2059) with a lower expected uncertainty of calibration than the previous NIST standards (SRMs 473, 475, 476). In calibrating these standards, optical simulation modeling has been used to predict the microscope image intensity profiles, which are then compared to the experimental profiles to determine the certified linewidths. Consequently, the total uncertainty in the linewidth calibration is a result of uncertainty components from the optical simulation modeling and uncertainty due to experimental errors or approximations (e.g., tool imaging errors and material characterization errors). Errors of approximation in the simulation model and uncertainty in the parameters used in the model can contribute a large component to the total linewidth uncertainty. We have studied the effects of model parameter variation on measurement uncertainty using several different optical simulation programs that utilize different mathematical techniques. We have also evaluated the effects of chrome edge runout and varying indices of refraction on the linewidth images. There are several experimental parameters that are not ordinarily included in the modeling simulation. For example, the modeling programs assume a uniform illuminating field (e.g., Koehler illumination), ideal optics and perfect optical alignment. In practice, determining whether Koehler illumination has been achieved is difficult, and the optical components and their alignments are never ideal. We will present some techniques for evaluating Koehler illumination and methods to compensate for scattered (flare) light. Any such experimental elements, that are assumed accurate in the modeling, may actually present significant components to the uncertainty and need to be quantitatively estimated. The present state of metrology does not permit the absolute calibration of linewidth standards to the level of uncertainty called for in the semiconductor roadmap. However, there are applications for a linewidth standard and calibration strategies which do not require a NIST certified calibration (e.g., determining measurement precision). In this paper we present various critical elements of a systematic and thorough evaluation of the key components of linewidth uncertainty as well as our methods for evaluating and reducing modeling and experimental uncertainties.

The edge roughness of straight lines has received intense focus in the past, whereas the edge roughness of contact holes has been relatively unexplored. Reductions in contact hole roughness can be shown to offer improvements in electrical breakdown voltages, or potentially the opportunity for reduced cellsize. This paper introduces two CD-SEM algorithms for characterizing the amplitude and frequency of contact hole edge roughness. When combined, these two metrics proved capable of detecting differences within four wafer pairs with varying dimension and processing. Increased roughness amplitude was shown to correlate to electrical breakdown failures.

Defect inspection of Quartz-PSMs is challenging, as the optical contrast for defects within the quartz substrate is small. The performance of three phase contrast algorithms is studied with a variety of defect test masks. For alternating phase shift masks key parameters such as optimum focus offset, defect sensitivity for different feature sizes, as well as defect sensitivity with respect to defect printability criteria are studied. In the studied range for two of the algorithms the defect sensitivity is independent of the feature size, whereas the third algorithm exhibited a decrease in sensitivity with decreasing feature sizes. In focus runs performed on large feature sizes a single optimum focus offset is observed, whereas for small feature sizes a two-path inspection using a positive and negative focus offset is found necessary. With respect to defect printability all critical 180° defects were found. For the newest of the three algorithms good inspectability of chrome-less PSMs is achieved.

DUV lithography induced sub-pellicle particle formation continues to be a significant problem in semiconductor fabs. We have previously reported on the identification of various defects detected on reticles after extended use. This paper provides a comprehensive evaluation of various molecular contaminants found on the backside surface of a reticle used in high-volume production. Previously all or most of the photo-induced contaminants were detected under the pellicle. This particular contamination is a white “haze” detected by pre-exposure inspection using KLA-Tencor TeraStar STARlight with Un-patterned Reticle Surface Analysis, (URSA). Chemical analysis was done using Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS) and Raman spectroscopy.

Nano-scale linewidth measurements are performed in semiconductor manufacturing, the data storage industry, and micro-mechanical engineering. It is well known that the interaction of probe and sample affects the measurement accuracy of linewidth measurements performed with atomic force microscopy (AFM). The emergent ultra-sharp carbon nanotube tips provide a new approach to minimizing the distortion of the measured profile caused by interaction with the finite probe tip. However, there is nearly always a significant tilt angle resulting when the nanotube is attached to an ordinary probe. As a result, we can obtain an accurate sidewall image of only one side of the linewidth sample rather than two sides. This somewhat reduces the advantage of using nanotube probes. To solve this problem, a dual image stitching method based on image registration is proposed in this article. After the first image is obtained, which provides an accurate profile of one side of the measured line, we rotate the sample 180° to obtain the second image, which provides an accurate profile of the other side of the line. We keep the sidewall data for the better side of each image and neglect the data taken for the other side of each image. Then, we combine these better two sides to yield a new image for which the linewidth can be calculated.

Initial characterization of the damascene process was obtained with the new coherent gradient sensing (CGS) interferometer on 200 and 300 mm wafers. The current study represents an extension of earlier work by taking advantage of the greater spatial resolution and data density of the CGS technique relative to more typical non-contact capacitance or laser scanning techniques. The comprehensiveness of the data provides insight into the uniformity of curvature and stress across the wafer. Measurements using the CGS technique were completed at multiple processing steps with principal emphasis being placed upon 300 mm dual damascene processing. It is shown that the greatest changes in wafer stress/topography occur as the wafer progresses through PVD barrier/seed, copper plate, copper anneal, and copper CMP. Of special interest in these studies is the formation of non-visual mechanical defects at a die level scale. Such measurements of valuable wafer properties are useful in not only process development, but also in process monitoring.

Focusing on smaller features for optical inspection or damage repair, smaller wavelengths are used to increase resolution or energy density. Objectives designed for 157nm will use calcium fluoride optics and the objectives need to be evaluated and optimized actinic, at wavelength. Measurement set-up and imaging results are presented through a catadioptric type of micro-objective. The set-ups and measurements are done at the 157nm wavelength as to include all actinic material effects. The imaging set-up uses a custom illuminator to image 130nm features, 500 times enlarged, onto a back-thinned CCD camera in real time. The knowledge of the spatial coherence characteristics of the light source together with the through-focus imaging of structures at various angles allows for the reconstruction of the wave aberrations of the lens. The lens is also measured and optimized using an interferometric set-up and phase shifting techniques.

Overlay metrology for production line-monitor and advanced process control (APC) has been dominated by 4-corner box-in-box (BiB) methods for many years. As we proceed following the ITRS roadmap with the development of 65 nm technologies and beyond, it becomes apparent that current overlay methodologies are becoming inadequate for the stringent requirements that lie ahead. It is already apparent that kerf metrology of large scale BiB structures does not correlate well with in-chip design-rule features. The recent introduction of the Advanced Imaging Metrology (AIM) target, utilizing increased information content and advanced design and process compatibility, has demonstrated significant improvements in precision and overlay mark fidelity (OMF) in advanced processes. This paper compares methodologies and strategies for addressing cross-field variation of overlay and pattern placement issues. We compare the trade-offs of run-time intra-field sampling plans and the use of off-line lithography characterization and advanced modeling analysis, and propose new methodologies to address advanced overlay metrology and control.

Two types of overlay targets have been designed and evaluated for the study of optical overlay metrology. They are in-chip and arrayed overlay targets. In-chip targets are three-bar two-level targets designed to be placed in or near the active device area of a chip. They occupy a small area in the range of 5 μm² to 15 μm² and have line widths, which are nominally device dimensions. The close proximity of the line features result in strong proximity effects. We have used two well-established theoretical models to simulate and study the effects of proximity on overlay measurements. In this paper, we also present a comparison of optical overlay results with scanning electron microscope measurements. Arrayed targets have also been designed to improve and enhance the optical signal for small critical dimension features. We have also compared theoretical simulations of arrayed targets to experimental results. In these comparisons we observe a significant variation in the location of the best focus image with respect to the features. The through-focus focus-metric we have implemented in the current work to determine the best focus image shows interesting properties with potential applications for line width metrology and process control. Based on simulation results, the focus-metric is sensitive to changes in line width dimensions on the nanometer scale.

We have developed a method for calculating the statistical effects of spatial noise on the overlay measurement extracted from a given overlay target. The method has been applied to two kinds of overlay targets on three process layers, and the new metric, Target Noise, has been shown to correlate well to the random component of Overlay Mark Fidelity. A significant difference in terms of robustness has been observed between AIM targets and conventional Frame-in-Frame targets. The results fit well into the spatial noise hierarchy presented in this paper.

The appropriate definition and identification of total measurement uncertainty from a group of metrology tools is becoming ever important as process tolerances continue to shrink in today's data storage and semiconductor manufacturing environments. The precision-to-tolerance ratio needs to be properly defined and minimized in order to maintain capable process control. The task of identifying components contributing the total measurement uncertainty therefore poses a major challenge for both the metrology tool manufacture's and the system owners on the customer side. In this paper, two models are proposed to perform the estimation of total measurement uncertainty component and the corresponding precision-to-tolerance ratio estimation with the methodology of the analysis of variance. Two models are developed to suit the measurement characteristics difference. The first is a crossed model designed for the nondestructive measurements and the second is a nested model developed for the measurement environments where sample destruction is unavoidable. The models analyze precision components from an individual tool as well as the entire tool group so that the error from matching is accounted for. Optical overlay and CDSEM tools were both selected for study and the measurement data were used for precision analysis. The error contribution from the bias identification was performed using a CDAFM as a reference and a CDSEM as tool under test. The methodologies developed in this paper serve as a guide for the metrology tool manufacturers and tool users to systematically estimate the total measurement uncertainty and the related improvement for precise process control.

We report on investigations including calibration of a 100 nm pitch structure, the NanoLattice by VLSI Standards, with a special metrological scanning electron microscope (SEM) and a scanning force microscope (SFM). The SEM used is called electron optical metrology system (EOMS) and basically consists of a dedicated low voltage e-beam column which is mounted on top of a large vacuum chamber with an integrated, laser-controlled precision 2D stage. The key feature of this instrument is the advantage to combine sub-nm-resolution object position measurement by vacuum laser interferometry with a high resolution e-beam probe of about 5-10 nm. Correlation methods combining the laser interferometer and secondary electron intensity profile data are used to analyze global pitch as well as local pitch deviations. The EOMS measurements confirm an excellent pitch uniformity. Preliminary estimations yield sub-nanometric mean pitch uncertainties for the 100 nm grating period over the whole active area of 1 mm x 1.2 mm. Additional SFM investigations were performed by a modified NanoStation III (SIS GmbH, Germany) which has been especially adapted for high stability measurements. In this way, the instrument allows to determine pitch homogeneity and line edge roughness (LER) of the structures with high reproducibility. Preliminary results show a good agreement with EOMS measurements.

As optical lithography has been pushed down to its theoretical resolution limit, the application of very high NA and aggressive Resolution Enhancement Techniques (RETs) are required in order to ensure necessary resolution and sufficient process window for DRAM cell layouts. The introduction of these technologies, however, leaves very small process window for core and peripheral layouts. In addition, new generation DRAM devices demand very precise CD control of the core and peripheral layouts. It implies that the time has come to keep a very watchful eye on the core and peripheral layouts as well as DRAM cells. Recently, Process Window Qualification (PWQ) technology has been introduced and is known to be very useful to estimate process window of core and peripheral layouts. Also, novel measurement system which can compare SEM image with CAD data is being developed and it can be of great help to evaluate OPC accuracy and feed back the CD deviation to OPC modeling. Last but not least, New Mask Qualification (NMQ) is proposed to verify very low K1 lithography by comparing with relatively high K1 lithography. In this paper, most effective OPC verification methodologies for sub-100nm node are discussed.

The Advanced Metrology Advisory Group (AMAG) is a council composed of the chief CD-metrologists from the International SEMATECH Manufacturing Initiative (ISMI) consortium’s Member Companies and from the National Institute of Standards (NIST). The AMAG wrote and, in 2002, with CD-SEM supplier involvement, updated the “Unified Advanced CD-SEM Specification for Sub-130nm Technology (Version 2002)” to be a living document which outlines the required performance of advanced CD-SEMs for supplier compliance to the 2003 International Technology Roadmap for Semiconductors, and also conveys member companies’ other collective needs to vendors. Through applying this specification during the mid-2003 timeframe, a benchmarking effort of the currently available advanced CD-SEMs has been performed. These results are presented here. The AMAG Unified Specification includes sections outlining the test methodologies, metrics, and wafer-target requirements for each parameter included in the benchmark, and, when applicable, prescribes a target specification compatible with the ITRS and methodologies compatible with the demands of 90nm technology. Parameters to be considered include: •Precision, Repeatability and Reproducibility •Accuracy, Apparent Beam Width and Resolution •Charging and Contamination •Tool-to-Tool Matching •Pattern Recognition and Navigation Accuracy •Throughput •Instrumentation Outputs •Tool Automation and Utility •Precision and Accuracy of Profile Measurement •Precision and Accuracy of Roughness Measurement. Previous studies under this same project have been published, with the initial version of the International Sematech Unified Specification in 1998, and multi-supplier benchmarks in 1999 and 2001. The results for the 2003 benchmark will be shown and compared to the ITRS, and composite viewpoints showing these 2003 benchmark results compared to the past results are also shown, demonstrating interesting CD-SEM industry trends.

The decrease in critical dimension (CD) of integrated circuits (IC) always challenges metrology tools capabilities. In less than ten years we will reach the limit of CMOS technology with typical printed gate length less than 20 nm and physical gate length of less than 15nm. Advanced R&D departments must already address today all the issues related to so small devices otherwise the roadmap requirements would not be fulfilled. Indeed most of the issues are directly related to metrology capabilities such as precise control of the shape of etched features, sidewall roughness, wafer CD uniformity, and mask inspection (. . .). All these parameters will represent a bottleneck for advanced patterning if metrology tools are unable to measure them with a precision better than few nanometers. In this paper we show that 3D metrology is mandatory to succeed in reaching future roadmap requirements. We address in details the CD AFM technique capabilities which is a potential candidate for advanced patterning metrology. The experimental data are compared with today’s reference: cross-sectional analysis (X-SEM). We also discuss on other techniques such as scatterometry and top view CD-SEM which are also candidates for 3D metrology.

Spectroscopic scatterometry is an optical metrology technique based on light scattering aiming at measuring geometrical dimensions, such Critical Dimension (CD) but also height or depth, side-wall angle and even more tiny details in a line profile. Scatterometry tool measures and analyzes the spectrum scattered or diffracted from a periodic target patterned on a wafer. Scatterometry is strongly considered as an alternative or as a complementary technique to CDSEM for 90 nm and below technology nodes. Like other optical metrology techniques, scatterometry measurements are rapid, non-destructive and highly repeatable. Actual tools have been assessed for dense to semi-isolated lines CD metrology and profiling. Developments are now targeting hole measurement. 2D-scatterometry (scatterometry on 3D patterns) becomes mature and begins to be used in advanced fab for CD control after lithography. This paper focuses on the capability of the spectroscopic scatterometry method to determine holes features and to try to give theoretical limits of method. Scatterometry uses an optical tool for spectra recording and a software tool including an advanced electromagnetic simulator and an optimization loop for data extraction. The first part of this study reports on the influence of bi-periodic structures in the experimental analysis of holes measurements. Then a limitation in holes density is defined. The second part of this study is a theoretical analysis based on simulation of the sensitivity of scatterometry with respect to various holes parameters. Following parameters are generally taken into account: holes diameter, holes ellipticity (elliptical ratio), holes roundness, holes depth and tilt angle for non-circular holes. We determine the respective influence of these parameters on ellipsometric spectra.

The influence of line-edge roughness (LER) on transistor performance was investigated experimentally and the preciously proposed guideline for CD and LER measurements was examined. First, regarding the transistor-performance measurements, a shift of roll-off curves caused by LER within a gate pattern was observed. Moreover, the effect of transistor-width fluctuation originating from long-period LER was found to cause a variation in transistor performance. Second, regarding LER and CD metrology, the previously reported guideline was validated by using KrF and ArF resist-pattern samples. It was found that both CD and LER should be evaluated with the 2-μm-long inspection area. Based on this guideline, a comprehensive approach for evaluating LER and CD for transistor fabrication process is presented. The authors consider that this procedure can provide useful information for the 65-nm-node technology and beyond.

We use the LER measurement capabilities of the Applied Materials NanoSEM 3D CD-SEM for the determination of LER for different manufacturing steps of the DRAM gate layer for the 90 nm technology node and below (after develop, after hard mask-open and final inspection steps). The system allows the fully automatic measurement of the LER as a 3 sigma value for top as well as bottom LER and yields also information about the spatial frequency along the line edge. We demonstrate precision of LER measurements (3 sigma) of less than 10% of the LER for resist structures as well as for etched structures with random or artificial LER within a range from 4 to 20 nm LER. The results agree with the requirements of the ITRS roadmap for structures down to 70 nm. We show on etched poly wafers containing artificial LER that the identification of discrete frequencies is possible down to LER values of below 5 nm (3 sigma). Based on these result we investigate LER on product wafers and show that the LER of left and right line edge, repsectively, are independent of each other. Additionally, no significant discrete frequencies are detected for all process steps under investigation, although the LER amplitude varies significantly in dependence of process conditions.

As aspect ratios become higher, features become smaller, and requirements for planarity tighten, Atomic Force Microscopy (AFM) has begun to replace profilometry for topographic measurements such as trench and via depths, step height, and micro-planarity measurements, both in development and in production. In this paper, we describe the application of a new, high throughput AFM for line monitoring in the STI and trench capacitor modules. We focus on two key applications: the post-CMP height difference between the active area and the isolation area in the STI module, and the post-etch depth of a DRAM trench capacitor. We begin by describing the two initial AFM applications. Next, we introduce a statistical approach for determining optimal lot sampling for these applications. From the gap between throughput of our current AFMs, and statistically determined sampling requirements, we validate the need for a high throughput AFM. Next, we describe the design of such an AFM, recently developed by KLA-Tencor, and its expected benefits. Finally, we discuss the economic benefit to Infineon of detecting metrology problems in-line, without the delay and cost of cross-sectional SEM analysis.

Line edge roughness (LER) remains a predominant measure of pattern quality used to evaluate processing parameters throughout the many steps of fabricating microelectronics. In the effort to minimize LER, a critical component is a metrology capable of rapid and non-destructive characterization of fluctuations in the position of the pattern, or line, edge. Previously, we have demonstrated a non-destructive metrology capable of sub-nm precision in the measurement of pitch and linewidth termed Critical Dimension Small Angle X-ray Scattering (CD-SAXS). Here, we explore the capability of CD-SAXS to measure line edge fluctuations using the diffuse scattering from diffraction peaks. Models of varying forms of line edge roughness are used to explore the effects of different types of line edge roughness on CD-SAXS results. It is found that the frequency and the degree of correlation of the roughness between patterns greatly influences the scattering pattern predicted. Model predictions are then compared to CD-SAXS results from a photoresist grating.

As DRAM (Dynamic Random Access Memory) device continuously decreases in chip size, an increased speed and more accurate metrology technique is needed to measure CD (critical dimension), film thickness and vertical profile. Scatterometry is an optical metrology technique based on the analysis of scattered (or diffracted) light from periodic line and space grating and uses 2θ angular method (ACCENT Optical Technologies CDS-200). When a light source is irradiated into the periodic pattern, the scattered intensity signal of zero-th order as a function of incident angle is measured. By analyzing these scattered signals, various parameters of the periodic pattern such as CD, vertical profile, mapping of substrate structure, film thickness and sidewall angle can be determined. Advantages of scatterometry are that drastic decreased measuring time and acquirement of CD, vertical profile, film thickness and sidewall angle by just one measurement. In this paper we will discuss various applications of scatterometry to sub-100nm DRAM structures of straight line and space and curved line and space patterns. Details of the correlation with CD-SEM (Scanning Electron Microscope) of standard metrology tool and repeatability of measured CD values will be discussed. As diverse applications, results of in-field, in-wafer and wafer-to-wafer CD monitoring, STI (Shallow Trench Isolation) depth monitoring and matching of vertical profile with V-SEM (Vertical SEM) will be also presented.

A new focused ion beam and electron beam based approach to metrology is used for accelerated process development of Chemical Mechanical Planarization (CMP) related back end processes. The technology is studied with the intention of employing it in rapid process development and high volume manufacturing. A structural metrology approach will include monitoring several features including low-k dielectric and Cu thickness as a function of pattern density. The study here will focus primarily on the film thickness of post-CMP low-k dielectric. The unique capabilities of the tool to cut, image and measure in a fully automated fashion, makes it necessary for us to evaluate the total process of sample preparation and measurement involved in this approach to metrology. We are therefore introducing the concept of total process precision to supplement a total measurement uncertainty analysis. In this paper we will report upon the analysis of work done to quantify this approach. This will involve a quantitative comparison of the tool metrology with a cross-sectional analysis SEM which is the most common best practice today.

For the 100nm technology node, the electrical measurement technique continues to play an important role as a metrology tool for generating large volumes of unbiased and statistically significant CD data. However, the ECD offset of approximately 35 to 40nm between the SEM CD after etch and the electrically measured CD obtained with the current standard ELM process, is a potential limitation for applying ELM to feature sizes below 65nm. Is this ECD offset process related or have we reached the limitation of the metrology technique fundamental to ELM? These are questions we attempt to answer in this paper. This paper attempts to answer these questions by looking at the fundamentals of the metrology technique and the influence of substrate material on the ECD offset. A calibration of the offset is performed by benchmarking ECD against different CD-SEM measurement algorithms. We re-examine the basic assumption that is fundamental to the electrical measurement technique and examine if this still holds true when the CD has become smaller although the substrate thickness has remained constant? In conclusion we report the parameters influencing the ECD to physical measurement bias and the limitations of this measurement technique.

We present a technique to produce isolated lines and trenches with arbitrary widths in the range of 12 nm to 500 nm, arbitrary heights and depths in the range of 100 nm to 2 μm, 90-degree sidewall angle, and top corner radii as small as 5 nm. These structures are ideal candidates as Critical Dimension (CD) absolute standards. The sidewall angle can further be varied to create an arbitrary sidewall angle that can be accurately measured.

Currently, CD-SEMs are the tool of choice for in-line gate length measurements for most semiconductor manufacturers. This is in large part due to their flexibility, throughput, and ability to correlate well to physical measurements (e.g., XSEM). However, scatterometry is being used by an increasing number of manufacturers to monitor and control gate lengths. But can a scatterometer measure such small critical dimensions well enough? This paper explores this question by analyzing data taken from wafers processed using 90 nm node technology. These wafers were measured after gate formation (gate final CD) using a CD-SEM as well as a scatterometer. They were then processed into the back-end-of-line and measured electrically. This electrical measurement, called L_poly, is an important parametric device measurement and is used to screen product before it reaches final electrical test. It is therefore critical for the in-line metrology immediately after gate formation to have excellent correlation to L_poly. Analysis shows that the scatterometer correlates well to both in-line CD-SEM measurements across multiple structures as well as electrical L_poly measurements. More importantly, the scatterometer is shown to be approximately equivalent to the CD-SEM when both are correlated to L_poly. Since several scatterometry targets with different pitches were measured, the amount of correlation as a function of pitch is also investigated. Because traditional methods of correlation, such as Ordinary Least Squares (OLS), have severe limitations, Total Measurement Uncertainty (TMU) analysis is used as a highly effective assessment methodology. This paper also shows how TMU analysis is used to improve the scatterometry model and understand the relative contributions from obstacles that hinder the achievement of even better correlations.

Scatterometry is a novel optical metrology that has received considerable attention in the silicon industry in the past few years. Based on the analysis of light scattered from a periodic sample, scatterometry technology can be thought of as consisting of two parts known as the forward problem and the inverse problem. In the forward problem, a scatterometer “signature” is measured. The signature is simply the measured optical response of the scattering features to some incident illumination, like laser light. In the inverse problem, the signature is analyzed in order to determine the parameters (such as linewidth, thickness, profile, etc) of the scattering features. Typically a rigorous electrodynamic model is used in the solution to the inverse problem, but due to the complexity of the model there is no direct analytic solution. Instead, a variety of numerical methods to solve the inverse problem have been proposed and utilized. The earliest widely used method of solution to the inverse problem involved the generation of a “library” of scatter signatures corresponding to discrete parameter combinations of the structure being measured. Once the library was generated, it was then searched in order to determine the best match to the measured signature. The parameters of the best match were then reported as the parameters of the measured signature. As the technology matured, other methods such as model optimization techniques also emerged. In fact, a variety of alternate techniques have been explored and reported, but a general study comparing the results (and hence the strengths and weaknesses) of the various techniques has yet to be performed. In this research, we shall report results from using several different solutions to the inverse problem on two applications (patterned resist and etched poly). The solution methods shall include the classic library search method as well as three common optimization methods. The results will show that each technique has strengths and weaknesses. For example, the library search methods are generally the most robust but also the most time consuming, and the optimization methods, while fast, are prone to reporting a local but not global minima.

In recent years scatterometry has been shown to demonstrate very impressive long term repeatability of better than 1.5nm when measuring a simple resist stack. However, does this impressive precision hold true for a more complicated stack such as that of Shallow Trench Isolation (STI)? Furthermore what benefits does scatterometry metrology bring compared to CD-SEM and X-SEM metrology for STI characterization and monitoring? In this work, we examine the impact of critical attributes fundamental to scatterometry metrology, such as grating parameter sensitivity and library optimization, for the STI layer of a CMOS process using KLA-Tencor’s SpectroscopicCD. We report the results from an optimized library to characterize the STI process after trench etch and the sensitivity of the metrology will also be discussed. Finally, the efficiency of this technique is demonstrated by reference to the monitoring results for a period of approximately five months.

Polysilicon recess etch process control in deep trench arrays of a DRAM requires reliable measurements of the recess depth directly in the trench array. Until now Atomic Force Microscopy (AFM) has been used for post etch depth measurements. However, with decreasing lateral trench dimensions, AFM may approach its limits especially with respect to the available bottom travel length. Consequently, alternative metrology methods are of interest. Scatterometry is an optical, model based measurement technique which potentially allows a full reconstruction of the measured structure. The measurement of the polysilicon recess presents a number of challenges: (1) the recess depth (150nm to 300nm) is much smaller than the total height of the complete structure (several microns), (2) spacer-like sidewall layers are present, while (3) unpredictable effects may be present (e.g. voids in the polysilicon fill) and would be difficult to include into a grating model. In addition, for measurements within the trench array 3D capability is required. In this work we analyze the capability of 2D and 3D scatterometry for polysilicon recess depth process control. We evaluate parameter sensitivities, parameter correlations, measurement robustness, depth correlation to the trench array, precision and accuracy for a wide range of process variations by comparing results obtained by scatterometry to those obtained by AFM and SEM cross sections. We show that a simplified grating model provides accurate measurements in lines/spaces structures (2D). However, in trench arrays (3D) the trench depth sensitivity is critical.

This paper compares two metrology methodologies, ECD (Electrical CD) and SCD (Spectroscopic CD), for the 45nm-node-like gate level. Measurements were taken on both metrology tools, for different features, and the data was processed to reflect the exposure tool’s fingerprint within the exposure field. ACLV (cross chip line-width variation) and through-focus measurements were also collected. There is a DC bias between the ECD and SCD. The cross slit and cross scan average plots are very similar between the two methods. The correlation between ECD and SCD gave R² of 0.95 and 0.92 for 220nm and 480nm pitches respectively. Results showed that SCD is a viable candidate to replace ECD for characterizing the exposure system for the 45nm node. Data also showed that there are fundamental differences between the two methods that cannot be attributed to random errors. These differences account for less than 1nm at 3 σ.

With critical dimensions (CD) of integrated circuits shrinking to tens of nanometers, accurate metrology of three-dimensional feature shapes at different stages of the lithographic process becomes crucial to circuit performance. We propose Critical Shape Metrology (CSM), a CD-SEM-based technique that extracts accurate feature shape information from images obtained during routine in-line wafer inspection. Intensity profiles from CD-SEM images of known materials are compared in real time to profiles in an off-line generated Monte-Carlo SEM simulation library for the same materials with various model shapes. When the best match is found, metrics like bottom CD, top CD, sidewall angle, foot size and angle, and corner rounding can be obtained with high accuracy. The proposed technique takes advantage of the high resolution and throughput of low-voltage CD-SEMs, and does not require any additional tool calibration beyond the standard calibrations performed for conventional top-down CD metrology. While similar to optical scatterometry in concept, this technique allows for measurement of both isolated targets and dense arrays. Examples of performance on etched polysilicon and resist lines of different shapes are included and compared to SEM cross-sections and CD-AFM data.

This study presents a new and unique method to reconstruct 3D profile from tilt images of SEM for semiconductor device pattern called 'Inverse Stereo Matching'. This method is based on 'the shape from shading' and it’s more stable than the conventional stereo matching method in case of low S/N in sidewall of tilt images, and it is able to reconstruct gradual change of sidewall shape that is difficult for the conventional stereo matching to reconstruct in detail. Additionally, this study presents a new method using 'MPPC Indices' to compensate errors of local shape in reconstruction 3D profile caused by the particular characteristic of secondary electron.

The measurement of edge roughness has become a hot issue in the semiconductor industry. Major vendors offer a variety of features to measure the edge roughness in their CD-SEMs. However, most of the features are limited by the applicable pattern types. For the line and space patterns, features such as Line Edge Roughness (LER) and Line Width Roughness (LWR) are available in current CD-SEMs. The edge roughness is more critical in contact process. However the measurement of contact edge roughness (CER) or contact space roughness (CSR) is more complicated than that of LER or LWR. So far, no formal standard measurement algorithm or definition of contact roughness measurement exists. In this article, currently available features are investigated to assess their representability for CER or CSR. Some new ideas to quantify CER and CSR were also suggested with preliminary experimental results.

International SEMATECH (ISMT) and the National Institute of Standards and Technology (NIST) are working together to improve the traceability of AFM dimensional metrology in semiconductor manufacturing. Due to the unique metrology requirements and the rapid change in the semiconductor industry, relevant standards are often not available. Consequently, there is often no traceable linkage between the realization of the SI (Systeme International d’Unites, or International System of Units) unit of length -- the meter -- and measurements in the fab line. To improve this situation, we have implemented a Reference Measurement System (RMS) using a next-generation critical-dimension atomic force microscope (CD-AFM). We performed measurements needed to establish a traceability chain and developed uncertainty budgets for pitch, height, and critical dimension (CD) measurements. At present, the standard uncertainties are estimated to be approximately 0.2% for pitch measurements, 0.4% for step height measurements, and 5 nm for CD measurements in the sub-micrometer range. Further improvement in these uncertainties is expected with the use of newer samples for scale and tip calibration. We will describe our methodology for RMS implementation and the major applications for which it has been used. These include measurements on new NIST/ISMT linewidth standards, a reference tool for CD-scanning electron microscopes (SEMs), metrology on photo-masks, CD-SEM benchmarking, and 193 nm resist shrinkage measurements. As part of the NIST/ISMT linewidth standards project, we are performing an extensive comparison experiment of AFM and TEM (transmission electron microscopy) measurements of linewidth.

193 nm resist shrinkage due to critical dimension scanning electron microscope (CD-SEM) measurements is a well-known but unresolved metrology issue in microlithography. Although there have been numerous studies on this subject, there are few publications on the 193 nm resist shrinkage finger-print carried over to etched features, i.e., the CD shrinkage carryover effect. This paper reports the results of our CD-SEM measurement study. We observed that the CD changes due to measurement were still present after etch and were often greater than 15% of the feature size. The shrinkage result implies that the action of CD-SEM measurement is destructive to the patterned circuitry. An improved CD-SEM measurement methodology is required to reduce circuitry damage. The study also revealed that minimal shrinkage carryover (less than 1%) could be obtained when the CD-SEM measurement condition was optimized. These results also indicate that measurement of CD shrinkage on post-etch patterns can offer a very effective method to characterize pre-etch resist shrinkage.

Copper damascene process and interlayer dielectrics with ultra-low permittivity have been introduced for manufacturing future devices with higher function speed. As materials with permittivity values lower than 2.2 are required, several kinds of porous materials have been proposed as candidates. However, these porous materials have been observed to shrink easily during CD (critical dimension) measurements with a CD-SEM. To solve this problem, the mechanism of shrinkage and the solution for damage-free SEM observation condition was studied. The shrinkage caused by different electron beam irradiation conditions in a CD-SEM (S-9260, Hitachi High-Technologies Corporation) was investigated with an atomic force microscope (AFM). The result shows that the shrinkage depends on the energy and the dose of electron irradiation. In addition, the change of chemical states and composition caused by electron beam irradiation was analyzed and the shrinkage mechanism was studied. The optimum electron beam irradiation conditions for damage-free measurement are proposed based on experimental results.

Previous results have demonstrated that the most significant line slimming occurs during the initial measurement and is a strong function of landing energy. Since it is difficult to accurately estimate the initial CD value (M0), many test protocols rely on the measurement change between the first and second measurement pass (M1-M2), to evaluate line slimming. However, since the slimming behavior of ArF resist systems has been shown to be exponential and dependant upon the resist formulation, using M1-M2 as the metric for comparing between CD SEM suppliers can severely underestimate the impact of a particular system setup on line slimming. The experiments reported here represent an attempt to assess the impact of the initial measurement (M0-M1) on line slimming. A series of experiments were designed to assess the impact of landing energy on line slimming for ArF photoresist. To validate the results of the experiments, an etched poly wafer was used as a control sample to ensure that metrology differences noted on the ArF resist between a high voltage 800 eV and an Ultra-Low Voltage (ULV) 100 eV condition arose purely from the interaction of the E-beam with the resist. The most significant line slimming was observed to occur during the first measurement at 800 eV, with greater than 10 nm of slimming observed on a nominal 120nm lines), followed by relatively stable slimming performance thereafter. The 100 eV condition demonstrated a significantly reduced level of slimming as a result of the first measurement; if there was any slimming, it could not be distinguished from the uncertainty in the estimate of the initial CD (M0). Measurements were also performed dynamically and at the ULV 100 eV condition slimming was indistinguishable from contamination induced linewidth growth, leading to an initial value closely matching the unperturbed linewidth (M0). The superior ArF line slimming performance at ULV is consistent with numerous published results, and demonstrates the need to assess slimming by a meaningful metric through a comparison of the initial measurement (M1) at high and low voltages, or by a comparison of the initial measurement M1 with the unperturbed linewidth (M0). The results of the experiments conducted point to a need for Low Impact Resist Measurement performance, which is fulfilled by Ultra-Low Voltage Metrology.

As feature geometries decrease, the budgeted error for process variations decreases as well. Keeping these variations within budget is especially important in the area of gate linewidth control. Because of this, wafer-to-wafer control of gate linewidth becomes increasingly necessary. This paper shows results from 300 mm wafers with 90 nm technology that were trimmed during the gate formation process on an etch platform. After the process that opened the gate hard mask and stripped the resist, the wafers were measured using both an integrated scatterometer and a stand-alone CD-SEM. The measurements were then used to determine the appropriate amount to be trimmed by the Chemical Oxide Removal (COR) chamber that is also integrated onto the etch system. After the wafers were trimmed and etched, they were again measured on the integrated scatterometer and stand-alone CD-SEM. With the CD-SEM as the Reference Measurement System (RMS), Total Measurement Uncertainty (TMU) analysis was used to optimize the Optical Digital Profilometry (ODP) model, thus facilitating a significant reduction in gate linewidth variation. Because the measurement uncertainty of the scatterometer was reduced to a level approaching or below that of the RMS, an improvement to TMU analysis was developed. This improvement quantifies methods for determining the measurement uncertainty of the RMS under a variety of situations.

In this paper we investigate the impact of bake plate temperature variability throughout the entire bake trajectory on resulting critical dimension. For a poorly-controlled bake plate, it is found that the correlation between the temperature profile and CD distribution is high throughout the entire bake cycle, including the steady state sector. However, for a well-controlled, multiple-zone bake plate, the correlation is only significant during the transient heating sector, since in those cases the steady state plate behavior has already been optimized for CDU performance. An estimate of the potential improvement yet to be gained by improvement of transient heating uniformity is calculated.

Tool matching and optimal process control are critical requirements for success in semiconductor manufacturing. It is imperative that a tool’s operating conditions are understood and controlled in order to create a process that is repeatable and produces devices within specifications. Likewise, it is important where possible to match multiple systems using some methodology, so that regardless of which tool is used the process remains in control. Agere Systems is currently using Timbre Technologies’ Optical Digital Profilometry (ODP) scatterometry for controlling Nikon scanner focus at the most critical lithography layer; logic gate. By adjusting focus settings and verifying the resultant changes in resist profile shape using ODP, it becomes possible to actively control scanner focus to achieve a desired resist profile. Since many critical lithography processes are designed to produce slightly re-entrant resist profiles, this type of focus control is not possible via Critical Dimension Scanning Electron Microscopy (CDSEM) where reentrant profiles cannot be accurately determined. Additionally, the high throughput and non-destructive nature of this measurement technique saves both cycle time and wafer costs compared to cross-section SEM. By implementing an ODP daily process check and after any maintenance on a scanner, Agere successfully enabled focus drift control, i.e. making necessary focus or equipment changes in order to maintain a desired resist profile.

Advanced Process Control (APC) on overlay is in use for high-volume production fabs with enough data available to statistically filter out noise contributions. In a foundry that is characterized by multiple products, each with a low production volume, very limited data is available per product. With the proposed advanced process control system we want to solve the issues related to this low amount of data by using data from lots that have a different history, e.g. lots that are exposed on other machines or lots from other products. To be able to do this production data is first corrected for machine contributions by use of monitor data for each machine. The resulting estimated process induced errors are maintained for all products and all layers in a database with reference to used machines, layers, product type and process family. The process induced errors for each lot are selected from the database by sharing available data that is expected to behave most similar. The proposed advanced process control system is partially implemented in production for a couple of layers. Simulations are run on more layers to test the data sharing concept. The simulation results are in reasonable agreement with actual product measurements and predict that the advanced process control system performs similar for lots for which the proposed data sharing concept is used as for lots for which the identical context is available.

High-resolution contamination inspection for advanced reticles remains crucial in light of the increasing trend of progressive defects such as crystal growth, haze, fungus, precipitate etc., introduced with DUV lithography, especially for low k1 processes. In most fab environments, routine incoming and re-qualification inspections for photomasks have been implemented. But although this high-resolution inspection provides necessary high-sensitivity, on advanced photomasks it often introduces inspection challenges. Aggressive OPCs and dense primary and secondary geometries are some of the many factors that can result in false-defect problems for the inspection systems. Thus, inspection needs to be desensitized. As an effort to identify a methodology to provide the inspectability while maintaining the necessary high-sensitivity, a characterization has been performed to evaluate a new combination-mode inspection. This technical paper will list the details of this special contamination inspection technique that will allow users to maintain the same high inspection throughput while providing similar or higher resolution inspection for these advanced reticles with superior inspectability.

A series of experiments were performed to determine if the ThermaWave INTEGRA CCDi reflectometer combined with Timbre Technologies’ Optical Digital Profiler (ODP) software could meet the requirements for lithography cell integration and process control of critical 0.13-micron Flash memory applications. Shallow Trench Isolation (STI), First Poly Gate, Stacked Gate and Aluminum Interconnect layers were examined as a part of this study. ODP models were developed for each of these applications and their output was compared to Critical Dimension Scanning Electron Microscopy (CDSEM) and cross-section SEM to demonstrate adequate correlation to incumbent metrology techniques. ODP is shown herein to correlate to CDSEM while providing the throughput required to measure every wafer without creating a bottleneck for the lithography cell. Experimental results also suggest that, in many cases, ODP can deliver profile determination beyond the fundamental capability of standard in-line metrology techniques.

Critical Dimension of gate pattern in CMOS process is the most important parameter for transistor performance and Organic BARC is generally used for controlling gate CD by reducing the substrate reflectivity. After gate etch process, small poly-silicon block defects are formed and those are derived from BARC material. After S/W nitride deposition and etch process the defects become larger and formed block defects of Belly Button type. These “Belly Buttons” are blocking the active area of transistor, make the device characteristic worse and lead to yield loss. To reduce Belly Buttons, we have evaluated various BARC resist filtration methods including new filtration material and smaller size filter in 0.18~0.35 μm CMOS gate pattern process. It was possible to reduce Belly Buttons dramatically using optimized resist filtration method and we finally got the yield up.

With an ever-increasing demand of stringent overlay control as a result of aggressive device scaling, lithographers are facing more challenges to maintain the inter-layer pattern registration accuracy. One of the critical factors is related to the integrity of monitor patterns (keys) when wafers undergo various process steps. It was reported that mis-reading of overlay registration could be induced by asymmetric film deposition on monitor keys. Lithographers go after more and more accurate controls on overlay performance as the overlay budget being constantly squeezed in face of ever increasing device density. Therefore, Fidelity between electric devices and registration inspection monitor key becomes one of concerned factors. Lots of papers addressed observations of overlay mis-reading induced by asymmetric film deposition on monitor key. In this report, both new mechanisms and new solutions are revealed. The mechanism of metal film stress induced scaling errors was identified. Besides, different kinds of metallic film configurations were conducted and shown to reduce previous scaling errors dramatically. Furthermore, a variety of new overlay keys without film-stress dependency were designed to overcome this issue. Both approaches reduced the mis-reading from tremendous to slight shift. This mis-alignment deviation is expected to be more severe during the migration from 200nm wafer to 300nm wafer as a result of a larger distance from wafer center to wafer edge. Those characterizations addressed in this report provide helpful information to the understanding of the overlay shift mechanism as well as solutions for better control.

Infrared spectroscopic ellipsometry (IRSE) metrology is an emerging technology in semiconductor production environment. Infineon Technologies SC300 implemented the first worldwide automated IRSE in a class 1 clean room in 2002. Combining properties of IR light -- large wavelength, low absorption in silicon -- with a short focus optics -- no backside reflection -- which allow model-based analysis, a large number of production applications were developed. Part of Infineon IRSE development roadmap is now focused on depth monitoring for arrays of 3D dry-etched structures. In trench DRAM manufacturing, the areal density is high, and critical dimensions are much lower than mid-IR wavelength. Therefore, extensive use of effective medium theory is made to model 3D structures. IR-SE metrology is not limited by shrinking critical dimensions, as long as the areal density is above a specific cut-off value determined by trenches dimensions, trench-filling and surrounding materials. Two applications for depth monitoring are presented. 1D models were developed and successfully applied to the DRAM trench capacitor structures. Modeling and correlation to reference methods are shown as well as dynamic repeatability and gauge capability results. Limitations of the current tool configuration are reviewed for shallow structures.

New photoresist chemistries, new process equipment, smaller design pitches and shrinking process windows all pose new challenges to resist and lithography process quality control. Controlling 193-nm resist defectivity is particluarly challenging, since the size of potential yield-critical defects shrinks in relative proportion to the size of the pitch. Standard defect density control strategies -- which involve taking liquid particle measurements of the resist at the vendor site, as well as inspecting unpatterned wafers coated with the resist -- are insufficient in identifying critical defect issues with 193-nm resists. Thus, they can no longer meet the advanced quality requirements of IC manufacturers. In this paper, we discuss a successful defect reduction project implemented at Infineon Technologies Dresden involving several resist vendors and the use of high-resolution inspection on patterned wafers. The importance of defect control on patterned wafers in addition to standard quality checks was clearly demonstrated. Based on the results presented in this paper, we believe that resist vendors should establish a defect control methodology that uses patterned wafers as a criterion for resist development and to ensure quality control.

A new generation of compact Fluorine lasers has been developed for repetition rates up to 2 kHz. The output powers are in the range of 3 W at 157 nm. Due to the introduction of new concepts for the laser tube and the pulsed power module it was possible to increase the maximum repetition rate from 1 kHz to 2 kHz without any loss in the performance of the laser output parameters. The pulse-to-pulse stability of the laser energy is improved in comparison to previous laser generations. The results of long term tests and measurements of the laser output characteristic will be reported in detail. The state-of-the-art of compact excimer lasers will be presented and an outlook for future trends will be given.

Shallow Trench Isolation (STI), is a critical process module in the manufacture of advanced CMOS devices. To achieve proper control of the STI process, multiple parameters such as film thickness, etched trench depth, and critical dimension (CD) must be measured with a high degree of precision and accuracy. Historically, these varied parameters were required to be measured independently using different metrology techniques/tools. Film thickness required measurement via reflectometry or ellipsometry, etched trench depth required measurement via profilometer or Atomic Force Microscope (AFM), and CD required measurement via low voltage Scanning Electron Microscope (CD-SEM). This paper will demonstrate the use of Spectroscopic Ellipsometry, via KLA-Tencor’s SpectraCD tool, to simultaneously provide all critical parameters of interest for the STI process, with a single in-line measurement. This metrology technique has been developed and evaluated for process control and product disposition at STI etch, on 130nm generation logic devices manufactured in two Texas Instruments’ fabrication facilities -- the DMOS 5 200mm facility and the DMOS 6 300mm facility. A brief description of the SpectraCD measurement theory and STI profile measurement solution for both dense and isolated structures will be given. Details will be provided on the use of real time regression to accelerate metrology model development. This will be followed by data generated from actual STI production material. Precision-to-tolerance (P/T) ratios well below 0.1 will be demonstrated for all parameters of interest on the STI etch measurements. Measurement matching across multiple SpectraCD tools, well within 130nm node process tolerances, will be demonstrated. Correlation of these measurements to other baseline metrology techniques (profilometer, Spectroscopic Ellipsometer or SE, CD-SEM) will also be presented. Finally, a discussion of the Return-on-Investment (ROI) that may be realized from combining three separate measurements into a single measurement will be provided.

The requirement to extend existing lithography equipment working levels and life has required manufacturers and end users to extend their filtration requirements beyond airborne base gases. Due to the effect acid gases can have on optics, masks, reticles, steppers, wafers, and metrology tools, they have become a more important molecular airborne contaminate to remove from inside a fab. SO₂ is known to be especially problematic within the cleanroom and exposure tool environment. However, a host of other molecular acids can also be found, some of which are present at considerably higher concentrations; the most prevalent of which are oxides of nitrogen, NO_x. Although the removal of NO_x contaminants is currently not considered to be as critical as SO₂, its presence can have a significant impact on acid gas sensitive applications. Several of these applications are addressed in this work in order to point out that NO_x contaminants do pose a problem, especially when considering the performance of acid gas chemical filters. More importantly, this preliminary work puts forth the recommendation that in addition to SO₂, the concentration of other acid gases should be taken into account when acid gas chemical filter efficiency and life estimates are being made.

Shrinking design rules and the introduction of new materials and processes in the formation of Cu interconnects in damascene modules have given rise to new and previously unknown killer defect mechanisms. These failure mechanisms are very challenging to detect, identify, and eliminate. The ability to characterize buried defects, such as defective vias, previous layer defects, or integration issues detected by optical defect inspection tools as well as electron-beam inspection tools has become mandatory. Out of the several cross-section tools available to the lab, the one that best addresses the in-line applications requirements is known as the DualBeam (FIB/SEM). The ion beam allows cross-sectioning while a coincident electron beam allows for high resolution imaging of the cross-section. Using the FEI Defect Analyzer 300 DualBeam system, this process has been automated for in-line usage. Defects can be navigated to using defect files generated by the inspection tools. The wafer production line is now enabled to easily mill cross sections in-line and determine root causes, something that is often not possible from top down information alone. For volume in-line use on defects, additional requirements must also be met: compatibility with clean room environment, navigation on full wafers to relocate the defects detected by the inspection tools, throughput, ease of use, low impact on wafers so that they can be returned to the line. All of this must allow the gathering of data at numerous cross-sections on buried defects in order to perform the same type of Pareto analysis as is traditionally done after defect review of top-down visible defects. Example use cases will be presented to demonstrate how this methodology is being developed in a manufacturing environment to help understand previously unexplained yield losses and to deliver results with a rapid response time. Applications on defects detected with electron beam inspection in copper or tungsten interconnects, will be described. The interest of such a methodology on more traditional defects after optical inspection will also be stressed.

Alignment performance and overlay control of metal layer from W-CMP process highly depends on the process influence on the alignment mark. While in a manufacturing environment, there could be introduced many changes into W-CMP process for defect reduction, cost reduction and yield improvement to further guarantee our success in this highly competitive industry. This study characterizes the CMP effect, especially erosion and dishing effect, polishing selectivity on alignment mark profile, which results in different alignment performance. We illustrate that how we seek solution to achieve an optimal alignment performance with the existing mark in according to different CMP slurry process by further fine tuning W-CMP process, such as over-polishing, final polish. The CMP effect on different alignment mark types is also evaluated; future alignment mark selection and design based on future CMP process, film deposition can thus be proposed. This work explains a good working method of optimizing alignment for process, fine tuning process for alignment mark, feed-backing solutions for mark selection while taking into considerations of cost, throughput, defect, yield.

Timbre's Optical Digital Profilometry (ODP) system is a scatterometry-based metrology. In lithography applications, the critical dimension (CD) is often patterned photoresist (PR) on an anti-reflective coating (ARC). When a patterned PR is exposed to the broadband light of the optical metrology tool, a change in reflectance may occur. For "sensitive" film stacks, the changing optical signals then produce changing ODP CD, sidewall angle, and film thickness measurements. This report summarizes the results of several resist and ARC stacks subjected to the repeated broadband light exposure of a Therma-Wave CCD-i reflectometry system. The purpose is to determine which resist-ARC stacks are significantly affected by repeated measurement exposure, and to quantify these effects. Our analysis shows that very little metrology exposure-induced change occurs for ArF resists. For KrF resists, the change is closely related to the type of KrF resist used; acetal-types incur large spectral changes upon repeated exposure, whereas ESCAP (Environmentally Stable Chemically Amplified Photoreist) resists measurements are very stable. Significant reduction of metrology induced spectral and CD change as achieved by incorporating a long-pass filter into the system. The changes due to a single measurement are negligible, however, they can be substantial for a sensitive material when characterizing metrology repeatability. Thus, it is recommended to use stable materials, such as oxide gratings, for metrology characterization.

Polarization is an important and useful degree of freedom to explore defect SNR (Signal-to-Noise Ratio) improvement on repetitive memory devices. Sub-wavelength repetitive memory cell structures, especially in process layers of high-refractive-index dielectric and conducting materials, act as polarizer, resulting in a strong dependency of the optical response on polarization direction. In this study, STI layers of two typical memory products, Dynamic and Flash RAM, were selected to investigate defect detection capabilities with different polarization state of illumination light for different layouts. Several defect types, including void and scratch, are investigated. SNR improvement is observed primarily through linear polarization that is parallel to the pattern layout. Flash memory devices exhibit stronger birefringence than DRAM devices.

Traditionally the defects, detected by inspection tools (optic & EBI), have been reviewed through DR-SEM or CD-SEM. Nevertheless, when physical defects are characterized using conventional in-line SEM it is hard to re-detect electrical defects because of the restricted working range in e-beam control. To detect and review electrical defects on contact layer EBI tools were used due to the in-line SEM limitation on electrical defect reviews. However the quality of the image was not acceptable to characterize type of defects due to its low resolution (20~30nm). In this article, the review condition of electrical defect was studied under the various electric conditions on Self Align Contact (SAC) layer. In order to achieve the optimum condition, a wide range of negative and positive conditions were applied using acceleration voltage, I-probe current, cap voltage and scan rate. Under stable weak negative charge conditions, 100% review of electrical and contact bottom defects were achieved. Furthermore, we found the high I-probe current and the appropriate acceleration voltage are main factors which increase the capability to re-detect the electrical defect. In this article, we figure out which defect is electrical defect and non-electrical defect applying to diverse electric conditions on the wafer.

Line edge roughness (LER) poses a serious problem for the performance of MOSFET devices. In this work, we experimentally investigated the influence of LER on MOSFET devices. The conditions giving LERs were prepared with four kinds of photoresists, namely, a KrF resist and three ArF resists. We applied seven post-applied-baking (PAB)/post-exposure-baking (PEB) conditions for one of the ArF resists used in this work. We not only measured critical dimension (CD) and LER but also analyzed LER spectra with a commercially available CD SEM. As a result, we obtained the important knowledge that LER became larger as CD became finer and the trend became more marked for the transistors with larger LER. We experimentally found that LER of 9 nm at the gate length (L_g) of 50 nm increased off-state leakage (I_off) of MOSFET, and the fluctuation of threshold voltage (V_th). Finally, we verified that LER of less than 7 nm at L_g of 50 nm is required to prevent the increase of I_off, and that in the case of L_g of 70 nm, the fluctuation of V_th did not increase even if LER was as much as 7.5 nm.

A new method of detecting a T-topped profile in resist patterns is described. This method can determine a T-topped tendency from only a single top-down CD-SEM image. The idea is based on the relationship between the cross-sectional pattern profile and the shape of the bright area near the pattern edge in the top-down image. Two kinds of index for a T-topped tendency are defined using line-edge roughness, width of the bright area, and the correlation coefficient between the left and right borders of the area. Both indices agreed well with actual cross-sectional profiles of various resist patterns. In addition, it is found that these indices can be used to estimate defocus in the photolithography process.

An improved overlay mark design was applied in high end semiconductor manufacturing to increase the total overlay measurement accuracy with respect to the standard box-in-box target. A comprehensive study has been conducted on the basis of selected front-end and back-end DRAM layers (short loop) to characterize contributors to overlay error. This analysis is necessary to keep within shrinking overlay budget requirements.

Electron beam-based wafer pattern inspection systems have the major advantage of allowing for the inspection of internal electric properties. However, charge-up of the wafer resulting from the use of an electron beam significantly influences inspection and remains a challenging issue. As an alternative approach to strict charge control, the authors propose a new inspection method that is capable of error-free, one-time inspection for recipe preparation, and which provides high-efficiency defect review and low error ratio inspection. Inspection is carried out at a higher-than-expected sensitivity, and defect candidate images are stored by a defect image analyzer (DIA). After inspection, the stored information contains both actual defects and nuisance defects. The distribution of candidate defects is displayed on a wafer map and the operator reviews the stored images and high-resolution review images on demand in order to check whether defects are true or nuisance defects. If necessary, the operator then adjusts the detection sensitivity and the system re-judges the stored data, displaying the modified wafer map to screen. In this way, the proposed system is robust against sensitivity drift caused by charge-up, and offers efficient, low error ratio inspection.

In lithography, the alignment error can be categorized into three factors. The first factor is called as Tool Induced Shift (TIS). The second is Wafer Induced Shift (WIS) and the third is the interaction between TIS and WIS. About TIS, we have defined a new evaluation criterion. About WIS, we have shown an error analyzer to quantify and compensate the alignment error using Atomic Force Microscope (AFM) and optical simulation. We have called this analyzer as 'Alignment Offset Analyzer'. This analyzer has the following features. The topography of an alignment mark and resist surface on the alignment mark are measured individually by the AFM. The two topography data are wrapping over in a signal simulator. Using the wrapped topography, an alignment signal and an alignment measurement offset are calculated. Since the alignment offset can also be calculated before exposure sequence, the alignment offset can be inputted to exposure tool without send-ahead wafers. This time we report the accuracy of the Alignment Offset Analyzer. The alignment offset measured by an exposure tool and the calculated one above mentioned showed a good agreement, and the difference was several nm.

As Integrated Circuit (IC) manufacturing moves towards smaller design rules and shorter product life cycles, the automatic application of Scanning Electron Microscopy (SEM) becomes more critical in advanced wafer fabrication processes. In most of the advanced IC manufacturers, automatic SEM defect review has been integrated into the IC fabrication process flow. Hence, a review methodology that can provide faster, accurate and reliable information on the yield limiting defects in an automated way, will definitely reduce the time to root cause analysis and thus improve yield and fab productivity. This paper provides a study of how the fab productivity was improved through the implementation of 45°-tilt Automatic Defect Re-detection (ADR) using the in-line defect review Applied Materials SEMVision. In addition to automatic review benefits, using the 45°-tilt capability also provides extra information necessary for root-cause analysis and yield improvement.

The production prototype of an electron beam inspection system based on projection electron microscopy (EBI-PEM) has been developed. Inspection performances of the EBI-PEM were evaluated using the programmed defect standard wafer delivered by SELETE. We confirmed the EBI-PEM had the same inspection speed, 9 cm²/h, as the conventional electron beam inspection system based on scanning electron microscopy (EBI-SEM) under the following conditions: pixel size of 50 nm and defect capture rate of more than 80%. Furthermore, the EBI-PEM achieved an inspection speed of 36 cm²/h. This inspection speed is four times higher than that of the EBI-SEM. The EBI-PEM would be an effective tool for inspection subsequent to the 90 nm technology node generation.

The measurement precision required for 65 nm technology node is 0.4 nm. However, ITRS has reported that the present CD-SEM has not had sufficient capability for 65 nm technology node. It is necessary to analyze the error factor of measurement precision thoroughly, in order to improve CD-SEM performance. Then, the items to be improved and the control method of tools for the measurement precision required for 65 nm technology node were examined. The error factors of CD measurement were divided into short-term repeatability, long-term variation, and tool matching. In factor analysis of short-term repeatability, the main factors of short-term repeatability were the image quality/measurement method and wafer load/unload. And it became clear that the interaction between local CD variation and scan shift accuracy had a remarkable effect on short-term repeatability. We established a method of monitoring tool condition in order to calculate long-term variation and tool matching with high accuracy. According to the experimental results of two tools for four weeks, the main factors of long-term variation and tool matching were initial variation and CD offset. From calculation of measurement precision using these results, measurement precision of the present CD-SEM has sufficient capability for hp90. It is reasonable to expect that improvement of these error factors will lead to the attainment of capability sufficient for hp65 measurement precision in the future.

Photo process defect reduction is one of the most important factors to improve the process stability and yield in sub-0.18um DUV process. In this paper, a new approach to minimize the Deep-UV (DUV) Chemically Amplified Resist (CAR) and Bottom Anti-Reflective Coating (BARC) induced defect known as UFO (UnidentiFied Object) defect will be introduced. These defects have mild surface topography difference on BARC; it only exists on the wide exposed area where there is no photoresist pattern. In this test, Nikon KrF Stepper & Scanner and TEL Clean track were used. Investigation was carried out on the defect formulation on both Acetal and ESCAP type of photoresist while elemental analysis was done by Atomic Force Microscope (AFM) & Auger Electron Spectroscopy (AES). Result indicated that both BARC and photoresist induce this UFO defect; total defect quantity is related with Post Exposure Bake (PEB) condition. Based on the elemental analysis and process-split test, we can conclude that this defect is caused by lack of acid amount and low diffusivity which is related to PAG (Photo Acid Generator) and TAG (Thermal Acid Generator) in KrF photoresist and BARC material. By optimizing photoresist bake condition, this UFO defect as well as other related defect such as Satellite defect could be eliminated.

Advanced scanners need an extremely high accuracy wafer alignment system, and nowadays it is also necessary that the alignment marks occupy a smaller area in order to expand the available area for IC patterns. Therefore, narrower lines with a smaller pitch must form the alignment marks. In this paper, a higher Numerical Aperture (NA) and lower aberration alignment optical system are studied for these requirements. At first the small alignment marks are shown, and suitable NA in the optical system is then discussed. As a result, the necessity for higher NA is shown. As for low aberration, the necessary specification of wavefront aberration is discussed. Assuming it is possible to suitably select the NA and the illumination NA in the optical system, the results of simulation -- that simulate image signals and perform image processing -- are reported. These results show the optical system that has aberration causes position shift, so that the specification of wavefront aberration is estimated in order that the position shifts may be sufficiently small. To make sure that with such a strict specification the system will be possible, a trial optical system has been made. Finally the techniques of manufacturing and the results of evaluation are reported.

Barometric pressure variations are known to affect the coating process resulting in photo resist film thickness variations in lithography track coat processes. The results of an internal TEL evaluation showed a strong correlation between barometric pressure variations and photo resist film thickness variations (as shown in introduction section). Based on those results, a "Barometric pressure compensation system" was developed to estimate and automatically correct for potential film thickness variations which would otherwise result from barometric pressure variations. An Inline system installed on a photo resist track at IBM was used to gather data for a variety of resist systems. A strong correlation was observed between barometric pressure variations and film thickness variations, and the effectiveness of automatic correction for this effect was demonstrated. In the case of KrF Escap-type resists (Resist A), the film thickness and barometric pressure are expressed in a primary approximate expression; the slope is -0.11nm/hPa, and the correlation coefficient (R²) is 0.93. As for the case of KrF Acetal-type resists (Resist B), the slope is -0.12 nm/hPa, and the correlation coefficient (R²) is 0.89. Through the use of the "Barometric pressure compensation system," photo resist film thickness variations were reduced from 2.7 nm (daily coating processed by the same recipe) to 0.6 nm for Resist A and from 5.0 nm to 1.4 nm for Resist B. The studies conducted showed that the "Barometric pressure compensation system" provides significantly improved photo resist film thickness control during variations in barometric pressure, and demonstrated that the technique can be applied effectively to a variety of photo resist materials.

Line edge (or width) roughness (LER or LWR) of photoresists lines consists a serious issue in shrinking the CDs of the gates to dimensions of a few tens of nanometers. In this paper, we address the problem of the reliable LER characterization as well as the association of LWR with the CD variations. The complete LER characterization requires more parameters than the rms value σ since the latter neglects the spatial aspects of LER and does not predict the dependence on the length of the measured line. The further spatial LER descriptors may be the correlation length ξ and the roughness exponent α, which can be estimated through various methods. One aim of the present work is to perform a systematic comparative study of these methods using model edges generated by a roughness algorithm, in order to show their advantages and disadvantages for a reliable and accurate determination of the spatial LER parameters. In particular, we compare the results from (1) the study of the height-height correlation function (HHCF), (2) the Fourier (or power spectrum, PS) analysis and (3) the variation of rms value σ with measured line edge L [σ(L) curve]. It is found that the HHCF can be considered approximately a rescaled version of σ(L) and that the value of σ becomes almost independent on the measured edge length for lengths larger than ten times the correlation length. As regards the PS, it is shown that the finite length of the edge may affect harmfully the reliable estimation of α and ξ. Finally, we confirm theoretically and generalize an experimental observation regarding the relationship between LWIR and the σ of the CD variations within a die of a wafer. It is shown that they behave in a complimentary way as line length increases so that the sum of their squares remains constant and equal to the square of the LWR σ of the infinite line.

As design rules shrink and process windows become smaller, it is increasingly important to monitor exposure tool focus and exposure in order to maximize device yield. Economic considerations are forcing us to consider nearly all methods to improve yield across the wafer. For example, it is not uncommon in the industry that chips around the edge of the wafer have lower yield or device speed. These effects are typically due to process and exposure tool errors at the edge of the wafer. In order to improve yield and chip performance, we must characterize and correct for changes in the effective focus and exposure at the edge. Monitoring focus and exposure on product wafers is the most effective means for correction, since product wafers provide the most realistic view of exposure tool interactions with the process. In this work, on-product monitoring and correction is based on optical measurement using a compact line end shortening (LES) target that provides a unique separation of exposure and focus on product wafers. Our ultimate objective is indirect CD control, with maximum yield and little or no impact on productivity.

Transfer of a layer layout from a reticle onto a photoresist-covered wafer using stepper exposure systems, can prove to be a challenging process to handle. This task becomes even more challenging when reaching the backend stages of the process, where the wafer topography variations at the wafer edge reach their maximum values. In advanced processes, where superposition of the exposure system focus plane and the wafer plane is critical, the focus is measured for every field before exposure is carried out, and the focus position of the exposure tool corrected. This can become complicated when the wafer edge is approached, and the focusing system measures a point or points, which do not represent the majority of the field plane. The outcome of the above can be an out of focus field exposure, resulting in feature degradation on the wafer, which in turn will be translated directly to wafer yield loss. The aim of this paper is to describe the achievement of yield optimization on various wafer layouts through the evaluation of various stepper focus algorithms, verification systems used to check the effectiveness of the fix, the follow-up table concept used for ease of fix validation, and eventually, the probe yield results of the chosen focus algorithm compared to those achieved prior to the optimization.

Due to necessities of semiconductor manufacturing some of the most critical lithographic layers may utilize only dielectric anti-reflection coatings (DARC) and not the organic anti-reflective coatings in order to minimize substrate effects on critical dimension (CD) control and in order to position the process at a best possible node. As a result of this relationship, stricter limits of control of index of refraction and extinction coefficient are generally imposed on the DARC process. While the DARC process may utilize a gas flow adjustment in order to control the optical constants, one of the biggest obstacles becomes the film thickness metrology, which is most often used via either the Bruggeman or the Harmonic Oscillator models to measure the desired optical coefficients. Unfortunately, the control of optical properties to within a few percent is generally outside of the window of specifications of even the latest generation of film thickness metrology tools. Furthermore, with each subsequent exposure node, the wavelength of interest for the optical coefficients is also near the limit of the lamp or radiation source on the film thickness metrology tool thus creating additional noise and measurement instability. An interesting situation is depicted in this paper where the metrology variation in measurement of the optical coefficients for a single stack DARC film is greater than the variation of twenty process chambers. The metrology variation was confined in major part to consist of tool-to-tool variation and of tool changes after any work on the ellipsometer. A systematic way of reducing this measurement variation is presented which allows for introduction of a floating standard tied to the combined average performance of all metrology tools without necessarily using a golden tool or a golden set of wafers. At the same time, offsets are applied to each metrology tool thus ensuring a much tighter population. Although the described situation is not ideal, with the current specifications on measurement of optical coefficients it is one of few methodologies necessary for adequate process control without the expenditure for a new toolset.

Due to the continuous shrinking of the design rules and, implicitly, of the lithographic process window, it becomes more and more important to implement a dynamic, on product, process monitoring and control based on both dose and focus parameters. The method we present targets lot-to-lot, inter-field and intra-field dose and focus effect monitoring and control. The advantage of simultaneous dose and focus control over the currently used CD correction by adjusting exposure dose only is visible in improvement of the CD distributions both at pre-etch and at post-etch phases. The 'On Product' monitoring and compensation is based on the optical measurement of a special compact line end shortening target which provides the unique ability to separate dose from focus on production wafers.

SiO_XN_YARCs are critical for maintaining CD control in current and future generations of designs. However, even minor fluctuations in t, n, and k across the wafer, or from wafer to wafer, can have a significant impact on ARC performance. For process control of ARC deposition, metrology tools must be able to reproducibly measure thickness and optical properties to 6 σ, translating into 1.5 Å for a nominally 500 Å SiO_XN_YARC and 0.0015 for index. A combination of laser ellipsometry and DUV reflectometry has demonstrated the ability to meet these requirements, with two tool-matching results of 0.8 Å for thickness and 0.001 for index. The accuracy of the thickness measurements was further tested at SiO_XN_YARC films were etched to clear. TEM confirmation of thickness measurements demonstrated the metrology was accurate with films as thin as 75 Å. The metrology method was subsequently used to monitor both the thickness and reflectivity at 49-points across a wafer at various etch times until the film was thinner than 25 Å.

The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

Measurement of Si trench depth and width critical dimensions (CDs) is an important aspect of shallow trench isolation (STI) process development. The ideal method of measurement is completely non-destructive and has high throughput. However, depth measurement using a Profiler involves contact or potential contact with the wafer surface, is generally not deemed a high throughput solution, and does not provide line width CD information. CD-SEM measurement, on the other hand, provides line width CDs and is faster than using a Profiler, but does not measure trench depth. It can also lead to localized damage and CD variation due to charging effects. Optical Digital Profilometry (ODP), also known as scatterometry, allows for a completely non-destructive, high throughput approach to collecting both CD and depth information. In this paper, we describe the application of ODP for STI process monitoring and compare this approach to older, more firmly entrenched techniques.

The cleanliness of optical components is a critical process parameter in microlithography. Molecular contamination is often the culprit for contaminated optical elements. The increasing use of purge gases and/or gas phase chemical filtration in photolithography tools are methods to help reduce or eliminate airborne molecular contamination (AMC), and is evidence that this form of contamination is problematic. And unfortunately, AMC becomes even more challenging in the transition from 248nm to 193nm and 157nm radiation wavelengths. Because of this, quantitative monitoring techniques and strategies play a crucial role in identifying and resolving molecular contamination that affects optical components. This paper, and the examples within, describe work performed using surface acoustic wave (SAW) technology to monitor and quantify in real-time and with high sensitivity AMC as it adsorbs, desorbs, or reacts with critical optical components. A high frequency oscillating quartz crystal is coated with SiO₂ to mimic critical optical component surfaces. As gas phase molecular contamination interacts with the sensor surface, the frequency of oscillation is altered. Contamination information is then extracted from the change in output frequency, including mass, rate, and trending data and correlated to process, equipment, or facility logs in order to determine the contamination source.

One of the sub-functions in the Micronic Sigma 7300 mask writer is the 2:nd layer alignment system for writing of phase shift masks. The strategy chosen for performing PSM alignment is to use the DUV writing laser together with the spatial light modulator (SLM) to create a light stamp image, which is reflected on the first layer alignment marks. The reflected image is captured and measured with a DUV-sensitive CCD camera. Using the writing laser has many benefits since there is no position offsets coming from misalignment of multiple laser sources. The anti-reflection (AR) function in chemically amplified resists (CAR), bottom anti-reflex coatings (BARC) and top anti-reflex coatings (TARC) reduces reflectance for 248 nm incoming light. This could reduce the signal strength and accuracy of the alignment system as the 248 nm laser is used for the alignment. The paper focuses mainly on two issues, image contrast at different resist thicknesses and image contrast when AR coatings are used. The algorithm measuring the fist layer alignment mark positions is also described. The studies of this and results of the final PSM alignment system show that Micronic has found an efficient way of dealing with these issues.

Advances in micromachining (MEMS) applications such as optical components, inertial and pressure sensors, fluidic pumps and radio frequency (RF) devices are driving lithographic requirements for tighter registration, improved pattern resolution and improved process control on both sides of the substrate. Consequently, there is a similar increase in demand for advanced metrology tools capable of measuring the Dual Side Alignment (DSA) performance of the lithography systems. There are a number of requirements for an advanced DSA metrology tool. First, the system should be capable of measuring points over the entire area of the wafer rather than a narrow area near the lithography alignment targets. Secondly, the system should be capable of measuring a variety of different substrate types and thicknesses. Finally, it should be able to measure substrates containing opaque deposited films such as metals. In this paper, the operation and performance of a new DSA metrology tool is discussed. The UltraMet 100 offers DSA registration measurement at greater than 90% of a wafer's surface area, providing a true picture of a lithography tool’s alignment performance and registration yield across the wafer. The system architecture is discussed including the use of top and bottom cameras and the pattern recognition system. Experimental data is shown for tool repeatability and reproducibility over time.

The accurate measurement of CD (critical dimension) and its application to inline process control are key challenges for high yield and OEE (overall equipment efficiency) in semiconductor production. CD-SEM metrology, although providing the resolution necessary for CD evaluation, suffers from the well-known effect of resist shrinkage, making accuracy and stability of the measurements an issue. For sub-100 nm in-line process control, where accuracy and stability as well as speed are required, CD-SEM metrology faces serious limitations. In contrast, scatterometry, using broadband optical spectra taken from grating structures, does not suffer from such limitations. This technology is non-destructive and, in addition to CD, provides profile information and film thickness in a single measurement. Using Timbre's Optical Digital Profililometry (ODP) technology, we characterized the Process Window, using a iODP101 integrated optical CD metrology into a TEL Clean Track at IMEC. We demonstrate the Optical CD's high sensitivity to process change and its insensitivity to measurement noise. We demonstrate the validity of ODP modeling by showing its accurate response to known process changes built into the evaluation and its excellent correlation to CD-SEM. We will further discuss the intrinsic Optical CD metrology factors that affect the tool precision, accuracy and its correlation to CD-SEM.

Precision can no longer be disassociated from accuracy. In fact, the two parameters must go hand in hand in the current 100 nm and below metrology environment. Therefore stating that "precision is more important than accuracy" does not capture the criticality of measurements of logic and memory chips with critical dimensions (CD) of 100 nm and below. The ITRS roadmap continues to set attainable milestones, calling for CD measurements with 3 σ to fall within a 0.9 nm error budget for the 100 nm mode, translating to ±0.9%. This implies tool calibration precision of 0.1% for 3σ. The methods in the industry today avoid both precision and accuracy and therefore cannot achieve the ITRS requirements. The resultant low precision and no accuracy in the SEM measurements lead to 'matching' and 'offset tables' that waste time, lose efficiency and potentially produce lower yield. Nanometrology's integrated system, NanoCal, a software/hardware product offers the first opportunity to combine both precision and accuracy in SEM magnification calibration. Using NanoCal in this work, we report that out of fab SEMs can be calibrated to 0.1% precision and 1 nm accuracy.

Scatterometry has been most commonly applied to CD metrology of line/space grating structures. However, for the process development and control of 3D structures for contact hole lithography applications, the current metrology methods of CD-SEM, electrical CD (ECD) and/or cross-sectional SEM (X-SEM) produce the desired information either (a) as an incomplete solution, (b) too late in process flow, or (c) in a destructive manner. In this paper, we will present use cases for the application of scatterometry to 3D structures, i.e., post-lithography hole/space patterns, where measurements of CD, profile, and film thickness can be made immediately following the lithography process, in a method nondestructive to the wafer. These use cases demonstrate the capability of 3D metrology integrated onto a TEL Clean Track platform, where a Therma-Wave reflectometer was used to generate spectra that were then processed via Timbre ODP, for a film stack of patterned photoresist (PR), anti-reflective coating (ARC), and oxide on top of a silicon (Si) substrate. Focus-Exposure Matrix (FEM) wafers have also been produced in order to characterize the contact hole profile and CD variation as a result of changing focus and exposure conditions. The results of the experiment show that ODP can be used successfully to monitor CD, film thickness, and profile variation, providing a valuable solution to contact hole lithography. Tool precision and matching results are also shown, which indicate the stability of the measurement process, and correlation to CD-SEM is also provided as a reference metrology. These results suggest that integrated 3D scatterometry is a viable production metrology solution, enabling the progression toward Advanced Process Control (APC).

Traditionally, mask defect analysis has been done through a visual inspection review. As the semiconductor industry moves into smaller process generations and the complexity of mask exponentially increases, “Mask” issues have emerged as one of the main production problems due to their rising cost and long turn-around time. Mask-making specifications related to defects found on advanced masks also becomes more difficult to define due to the complex features involved [e.g. OPC (Optical Proximity Correction), SRAF (Sub Resolution Assist Features), etc.]. The Automatic Defect Severity Scoring (ADSS) module of i-Virtual Stepper System from Synopsys offers a fast and highly accurate software solution for defect printability analysis of advanced masks in a real production environment. In this paper, we present our case study of production pilot run in which the ADSS is used to automatically quantify the impact of a given defect on the surrounding features, basically filtering out killer defects and nuisance defects in terms of production viewpoints to reduce operators’ intervention. In addition, an automation workflow is also tested, in which the production issues, such as the communication feasibility of mask quality control between mask house and wafer fab, are also considered.

Flatness of the incoming silicon wafer is one major contributor to the ultimate focusing limitation of modern exposure tools. Exposure tools are designed to chuck wafers without creating non-flatness and then use focus control to follow as closely as possible the chucked wafer front surface topography. The smaller size of the exposure slit in a step-and-scan exposure tool, as compared to the previous generation full-field stepper tool, helps minimize the impact of chucked wafer non-flat topography. However, to maintain high throughput and improve critical dimension uniformity (CDU) at sub-wavelength line-widths requires continuous improvement in the incoming silicon wafer flatness. In this paper we report extensive experimental results that review existing wafer flatness metrics and propose the addition of a new metric. The new metric emulates the scanning motion of exposure by integrating the defocus that each point on the wafer experiences during exposure. We show that this method is in better spatial agreement with measured defocus in step-and-scan exposure tools. Simple metrics of moving average (MA) defocus prediction analysis will be defined and shown to correlate very well to post exposure defocus data. These experiments were enabled by the creation of special 300-nm wafers by MEMC. These special wafers include sites with a wide variation in flatness. Prior to exposure the wafers were measured with a high-resolution optical flatness metrology tool (WaferSight by ADE) to obtain industry standard thickness variation (flatness) data. Incoming wafer flatness data is used to predict wafer suitability for lithography at the desired device geometry node (e.g., 90 nm). The flatness data was processed and characterized using both standard metrics (SFQR) and the new MA analysis. The relationship between the industry standard metric (SFQR) and similar metrics applied to MA analysis will be presented. Full two-dimensional maps are used to present spatial correlations and permit simple physical insights into the flatness data sets. Measurements of chucked wafer flatness were made on the same wafers using ASML TWINSCAN in-line metrology. These measurements correlate very well to thickness-based flatness. Un-chucked wafer flatness metrics (SFQR and MA) are shown to correlate well to post exposure defocus data when an appropriate site size is used. This result is discussed in relationship to the industry-accepted practice of specifying un-chucked wafer flatness. Lithography performance tests were made to prove the relevance of the different flatness metrics. The same special wafers are used for lithography performance tests. These tests achieve excellent correlation between post-exposure full-wafer focus control results and predictions based on both SFQ (industry standard) and MA re-mapping of the flatness data. The relationship between measured critical dimension (CD) and defocus is also explored. Point-by-point analysis of CD residual versus measured defocus data nicely follows a Bossung curve. We also show that residual CD values predicted from defocus correlate well with measured values. These experiments confirm the application of industry standard wafer flatness measurements to step-and-scan lithography when appropriately using current metrics. They also present the potential for improved metrics based on the MA defocus prediction analysis to help drive continuous improvement of wafer flatness for advanced step-and-scan lithography.

The pitch of a Hitachi Standard Micro Scale was measured using NanoCal and a LEO 1560 SEM. The pitch pedigree and certification were intentionally withheld from Nanometrology team members to enable independent measurement and certification of an unknown Hitachi Micro Scale standard during this work. NanoCal allows one to achieve pitch measurements with sub-nanometer accuracy and precision as well as to perform SEM magnification calibration with the precision and accuracy required for sub 90 nm SEM metrology.

We report about three-dimensional measurement by CD-SEM. Last year, we reported that the new T-MOL (Tilting and Moving Objective Lens) electron optical system enabled the capture of tilt images without deterioration of the resolution and confirmed that the T-MOL system provides 4 nm resolution at tilting angle 5 degrees. In this year we developed and evaluated the new objective lens and the new octapole deflector for increase of tilting angle and improvement in resolution, and we confirmed that the new electron optical system provides 3.6 nm resolution at tilting angle 8 degrees. Moreover, we report the optimization of the stereo matching technique based on the tilting picture using the actual semiconductor device for measurement 3D analysis.

Tapered resist profiles have been found to cause a deterimental effect on the overlay measurement capability, affecting lithography processes which utilize thick implant resist. Particularly, for resist thicknesses greater than 1.5 μm, the systematical contribution to the overlay error becomes predominant. In CMOS manufacturing, these resist types are being used mainly for high energy well implants. As design rules progressively shrink, the overlay requirements are getting tighter, such that the limits of the process capability are reached. Since the resist thickness cannot be reduced due to the requirements of the implant process, it becomes inevitable to reduce the systematical overlay error for the litho process involving thick resists. The following analysis concentrates on the tapers of overlay marks printed on thick i-line positive resists. Conventionally, overlay between two litho layers is measured from box in box marks with respect to a reference layer where the statistical shift between the boxes is expected to provide the biggest source of residuals. We observed however that an even bigger error could be introduced by an unevenness of the i-line resist tapers, adding asymmetrical chip magnification. The inclination of these tapers depends on the proximity and surface of the surrounding features and stack variations. We show that by adjusting soft and hard bake temperatures and times, tapers can be significantly reduced and thereby the overlay performance was greatly improved.

Optical inspection systems and/or electron beam inspection systems are quite useful tools for the yield management in the semiconductor process. However, they have some issues of difficulties for the application to the yield management after 100nm-technology node generation. Optical inspection systems have a resolution limit by diffraction phenomena. On the other hand, electron beam inspection systems based on scanning electron microscopy (EBI-SEM) have the limit of inspection speed. Both limits are serious matter for the application to yield management after 100nm-technology node generation. We have developed the electron beam inspection system based on projection electron microscopy (EBI-PEM), having both performances of inspection speed of optical types and spatial resolution of EBI-SEM. The system has been improved on the signal electron collection efficiency and transmittance of the electron optical system. We also have developed high rate and sensitive signal detection system. Then we considered that the inspection speed of several times faster than the conventional EBI-SEM is feasible at the spatial resolution less than 100nm.

A small notch or foot existing at the bottom of a polysilicon gate is a common issue for etching processes. The small notch or foot could have a major impact on the length of the polysilicon gate, and the performance of the device would then be impacted significantly, especially for cutting-edge devices. This paper demonstrates the capability of a spectroscopic ellipsometry based profile technology, SpectraCD, as a new metrology tool to monitor polysilicon gate process at 130 nm and 90 nm nodes. Firstly, the capability of SpectraCD as a metrology technology was studied, including dynamic precision and CD correlation. Dynamic precision in the range of 0.1~0.4 nm was demonstrated repeatedly in this study. CD correlation with CDSEM also showed a very linear result. R-squared values of ~0.99 are presented. Secondly, by comparison with images from cross-sectional SEM (XSEM) and TEM (XTEM), it has been proved in this study that SpectraCD can consistently flag different profile excursions of polysilicon gate, e.g., small notching, footing, or undercut. The size of the footing or notch reported by SpectraCD shows a linear correlation with the size extracted from XTEM images, which demonstrates quantitatively SpectraCD capability for detecting profile excursions. Finally, linear correlation between the bottom CD from SpectraCD and the gate lengths determined from electrical test (Lcap) will be presented.

The effectiveness of multiple parameter profile characterization (MPPC) as a three-dimensional measurement technique for etched gates is examined by comparison of shape indices with device performance. The MPPC method derives shape indices from top-down, critical-dimension scanning electron microscopy (CD-SEM) images to characterize the sidewall angle and footing roundness of the gate, which are considered to be the structural features that have a great effect on device performance. The capabilities of the proposed method are evaluated through experiments using processed gate wafers etched under different conditions, comparing the shape indices with the cross-sectional profiles obtained by atomic force microscopy. The relationship between the MPPC indices and threshold voltage is also investigated, confirming that variations in sidewall angle and footing roundness have several times the impact on threshold voltage as line width variation. This study confirms the importance of three-dimensional measurement of gate profiles for process monitoring through the use of a method such as MPPC.

We evaluate the optical response of binary quarter micron slits and gratings in thin opaque chromium layers for measuring critical dimensions on photomasks. At present the CD is typically inspected by time expensive SEM measurements. A main disadvantage of the SEM measurements is that it determines only the geometric parameters. Starting from the optical properties that come closer to the application of the masks we have evaluated a new approach to inspect the CD of test structures like quarter micron slits and gratings. The CD of the test structures has been varied between 100nm and 400nm. Slit widths of these structures have been characterized. Based on the combination of spectral and polarization resolved transmission and reflection measurements in a spectral range between 500 nm and 1700 nm with RCWA calculations we propose a new method for measuring the CD of test structures below the resolution limit of the classical microscopy with visible and infrared light.

The continuing shrinkage of device size will result in stringent demands on high precision CD control. For example, at 0.13um technology node a typical poly gate size variation should be controlled within +/- 8nm or even smaller. This tight CD budget includes all possible variations which can be from different modules of resist coating track, optical and mechanical parts of exposure tool, non-uniformity of wafer substrate, CD metrology, mask making and so on. Particularly, the residual swing effect after applying an inorganic anti-reflection layer (SiON) still can claim a significant CD budget if not properly optimized. Therefore, how to minimize the residual swing effect still plays important role in CD control. Simulation of reflectivity is considered analytically rigorous and is therefore frequently employed to aid in process development. However, since in manufacturing environments people usually pay more attention to the repeatability of optical metrology tools rather than their accuracies, it is not surprising if some significant discrepancies exist between theoretical and experimental results. Instead of discussing the detail error sources and the tool calibrations, a quick and convenient experimental methodology is introduced to account for such differences and to optimize the film stack composition effectively. In this paper, with the CD variations on metal and poly substrates as examples, an effective combination between the calculations and the experiments is presented in order to minimize the CD swing. We also demonstrate that with the "single wafer swing curve" technique, the residual swing effect can be easily detected and minimized. This methodology provides a possibility to determine the best anti-reflection layer not only from theoretical but also from experimental point of view in manufacturing environments. Since the residual swing effect is a common issue, the results of this paper can be widely used in either manufacturing fabs or experimental labs.

Shallow-Trench-Isolation (STI), as one of the primary techniques for device isolation in complementary metal-oxide semiconductor (CMOS), requires accurate and precise CD and line-shape control during wafer process. Thus, the measurement of the critical dimensions after lithography and after formation of the STI structure is extremely important for process control. Currently used SEM technologies are either destructive or incapable of identifying the profile features. The necessary averaging of CD-SEM measurements to compensate for its large error diminishes its usage in automatic process control. In this paper we use the Optical Critical Dimension (OCD) technique to study focus exposure matrix (FEM) wafers of photoresist patterns and STI structures and compare the results with CD-SEM measurements. OCD measurement is performed with normal-incidence polarized reflectometry. Rigorous Coupled-Wave Analysis (RCWA) is combined with real-time regression to provide CD and profile parameters with excellent sensitivity to sub-50 nm grating lines. Thus, non-destructive and fast real-time measurements are easily accomplished during wafer processing. Optimization of STI model parameters is discussed. The critical dimensions of 121 dies extracted by OCD exhibit excellent correlation with those obtained by CD-SEM, with R-squared as high as 0.995 on STI wafers.

The performance characteristics of a microelectronic device depend on the physical structure of the device. The device structure fabrication process involves lithography imaging and etching steps using photomasks. A mask with defects may lead to a device structure that deviates from intended geometry. The device structure deviation may result in inferior device performance. To ensure desired device performance from a fabricated device, a mask inspection is performed to dispose defective masks that may result in device structures with inferior device performance. The disposition decision is currently based on defect size and other properties seen at the mask level. By using lithography simulation based technology, the defect printability is also considered in defect disposition. However, the defect size and other properties at the mask level and even defect printability at wafer level may or may not lead to device structures with inferior performance. Such an early disposition decision could be very costly because repair process is time consuming, not all defects are repairable, and repair may introduce new defects. To improve the defect disposition, we present a new flow and method that is based on process simulation and device performance modeling using photomask inspection image. Our case study shows two defects both classified as killer defects by defect printability have very different impact on device performance.

Reticle costs are increasing as users tighten specifications to accommodate the shrinking process windows in advanced semiconductor lithography. Tighter specs often drive the use of e-beam based mask processes, which produce better mask pattern acuity than laser-based tools but suffer lower throughput (and thus higher costs). In some cases, such as contacts, the pattern acuity of an e-beam tool does not seem to be required -- but the tight effective CD uniformity typically produced by an e-beam mask writer is still necessary to prevent wafer level defect problems. This presents problems for the maskshop (e.g., low yield and long cycle time) as well as for the fab (more expensive new product introduction, uncertainty in mask delivery). This paper describes the results of qualifying a low cost, high quality mask making process for 90nm wafer production. The process uses a DUV laser-based mask writer to achieve low cost. Wafer photolithography process results using two masks fabricated with different mask making processes are presented, along with comparative electrical performance.

With ever increasing linewidth challenges per technology changes, the mask manufacturing process becomes more and more difficult. The challenges can be separated into two categories: image size and defects. Mask inspection detects hard defects most likely caused somewhere in the mask manufacturing process. Defect partitioning highlights the hard defects sources. They range from pre-exposure mask blank handling to the cleanliness of the process tools. A test vehicle was designed to allow for mask manufacturing defect partitioning via a die-to-die inspection tool. The process changes implemented range from pre-write mask handling to tool modifications. The methodology used to determine the process induced defects and the yield gains by making the necessary process changes will be presented.

The National Institute of Standards and Technology (NIST) has implemented a high bandwidth laser interferometer measurement system in a specialized metrology microscope. The purpose of the system is the certification of SEM magnification calibration samples by moving the sample under a finely focused stationary electron beam in the metrology electron microscope. Using a laser interferometer with displacement measurements traceable to basic wavelength standards, the motion is measured while recording the secondary or backscattered electron output signal. The recent upgrade to the laser measurement system enables a measurement bandwidth of 300 kHz to be achieved in the sampling of the X-Y position of a test sample, along with measuring the intensity of the secondary electron beam output signal. This high bandwidth stage position measurement capability becomes a tool to measure the effects of environmental vibrations on SEM measurements. This paper outlines this ongoing research and presents the current results along with details of the measurement possibilities based on this new technique.

Downscaling of semiconductor fabrication technology nodes brought forth a need to reassess the accuracy of 3D metrology. Accuracy is defined relative to a reference tool measurement. The authors have studied the accuracy of 3D SEM measurement results for various feature geometries and materials, matching the results to Monte Carlo simulations. Analysis of the SEM images based on an analytical model was performed. Accuracy of 3D algorithm for nominal process window monitoring is shown.

SEM Metrology becomes the standard metrology for the mask industry, as the precision and accuracy requirements tighten continuously. At the same time, analysis of general shape features becomes an important task in wafer metrology. In this paper we consider the basic requirements and suggested implementations for performing 2D metrology on reticles and wafers, [i.e. measurements of OPC (Optical Proximity Correction) structures, End of Lines, Dual Damascene and Corner Rounding]. The authors consider the following challenges related to the development of a generic algorithm for general shape 2D analysis: (1) A generic segmentation of the feature. It should be robust to noise, as well as brightness and contrast changes. (2) The complexity of two dimensional general shape features metrology. Standard CD SEM metrology is based on metrics describing simple geometric shapes such as ellipses and lines). (3) Obtaining such metrics that can be used as handles for process control (i.e. what to measure on the 2D feature). In the first part of the paper we describe a novel algorithm for segmentation and geometric analysis of general shape features based on a Smoothing Spline and the methods of differential geometry. Next, we consider the numerical methods implemented for shape analysis of noisy contours. In the second part of the paper the performance of our methods on synthetic contours of circular arc with different noise levels is demonstrated. We conclude with sample results of several suggested metrics measured on real SEM images of reticles and wafers.

Overlay measurement of metal interconnect layers that exhibit contrast variation has historically been problematic. The appearance of random grain structure surrounding the overlay target obscures the edge contrast, leading to significant noise in measurement and residual error of fit. Large residuals reduce confidence in modeled scanner correctable terms, increasing the likelihood of false scanner corrections which can lead to poor process control. We have developed a new measurement methodology that minimizes the effect of grain-induced noise for overlay metrology. Measurements which utilize the new parameters have shown a 30% reduction in mean-square (MS) residual error and a 39% reduction in variance. In addition, predicted wafer maximum overlay error has decreased by 14%, with a 16% improvement in wafer-to-wafer variance. This type of performance improvement is expected to have a significant impact on rework reduction. The primary source of visible grain structure in the aluminum interconnect layer has been attributed to the metal hardmask deposition process. By moving to a lower temperature hardmask deposition, the grain has been significantly reduced. This has resulted in a 15% further reduction of MS residual error.

CD SEM’s used for CD Metrology in semiconductor fabs rely upon secondary electron emission to indirectly image features on process wafers. The use of secondary electrons by current CD SEM technology limits the resolution of this metrology and hinders its ability to meet future requirements. An idea that has garnered some interest from both the research and commercial sectors is to use backscattered, or primary, electrons with very low energy losses to image patterned features directly. Such a device would operate with acceleration (and landing) potentials in the range of 50 keV-200 keV. One concern is whether the high energy incident electrons will damage active devices. It has been hypothesized that the substrate’s reduced stopping power for high energy electrons will result in the majority of the electron energy being deposited far below the device structures. We have explored the issue of device damage from high energy and high dose incident electrons and find that this technique results in unacceptable transistor degradation at all of the doses and landing energies explored. We present our findings in this paper.

Evaluations of CD-metrology tools usually focus on resolution, repeatability and accuracy. These are traditional metrics which relate to the capability to measure a local line width. These metrics do not cover the capability to map the CD fingerprint (uniformity map) of the wafer and scanner field, which are essential for sub-100nm lithography process control. In this study, CD-uniformity wafers of state-of-the-art step-and-scan systems were measured with different metrology tools. Analysis of the results revealed a random contribution that could not be attributed to the exposure tool or to the repeatability of the metrology tool. A test and analysis method was developed to separate out this random contribution from the test results. The level of this random CD variation, called the Total Test Repeatability (TTR), is proposed here as a new metric to compare CD-metrology tools in their capability to generate CD uniformity maps. The method was applied to study CD-SEM, Electrical Line width Measurements and CD-scatterometry. In general, the TTR appears to be much larger than the metrology tool repeatability. As such it is an important figure of merit for CD metrology tools used to reveal fingerprints of reticles, exposure tools or processing tools. The TTR is dependent on the metrology tool, measurement algorithm, but also on materials and processing flow and conditions. Some root causes have been identified, such as the wafer resistivity properties for ELM or line width roughness that appears as CD variation in CD-SEM tools. Modifications can be made in the metrology strategy to suppress the TTR and reveal more reliable CD-uniformity fingerprints.

This study characterizes the process influence on the alignment signal of deep trench (DT) process, and correlates product overlay with alignment results based on volume production data. The affecting processes include various steps of polysilicon thickness, nitride and oxide films, recess etch depth control, and resist thickness impact. Correlation also proves that the alignment signal plays an important role at the resulted long-term overlay stability. In order to improve the signal strength, further study focuses on the alignment optimization through mark design for deep trench process. The alignment marks evaluated include Scribe-lane Primary Marks (SPM) with difference process segmentations, short SPM marks and Versatile SPM marks. A good correlation is established between varying trench width or line width of mark segmentation and alignment signal strength. Comparison is also done for the signal strength between SPM mark and SSPM marks, between standard SPM mark and pure higher order marks.

The Aerial Image Measurement System (AIMS) for 193 nm lithography emulation has been brought into operation successfully worldwide. By adjustment of illumination type, numerical aperture and partial coherence to match the conditions in 193 nm steppers or scanners, AIMS can emulate for any type of reticles like binary, OPC and phase shift. AIMS allows a rapid prediction of wafer printability of critical features, like dense patterns or contacts, defects or repairs on the masks without the need to do real wafer prints using the cost intensive lithography equipment. Therefore, AIMS is a mask quality verification standard for high-end masks established in mask shops worldwide. With smaller nodes, where design rules are below 100 nm and low k1 factors are used in the lithography process, the increasing printability of even smaller defects on reticles is becoming a serious problem. The evaluation of defect printability using AIMS becomes a significant aid and cost-saving technique to be applied directly in the wafer fab. The overall measurement capability of the 193 nm AIMS system will be demonstrated by measurements at 193 nm wavelength on attenuated phase shift masks. Excellent illumination uniformity is crucial for quantitative analysis of AIMS measurements such as CD variation or defect printability. To reduce disturbing speckle formation of the highly coherent ArF excimer laser a new beam homogenizing technique which contains motionless parts only will be presented as well as illumination homogeneity results compared to the current solution using a spinning scattering disk. The latest results on illumination performance exceed the current results especially with respect to illumination uniformity over the field. The improved performance will enable improved measurement capability down to the 65 nm node. An outlook will be given for extension of 193 nm aerial imaging down to the 45 nm node emulating immersion scanners.

The requirements for optical surfaces have drastically increased for the deep-ultraviolet (DUV) and vacuum-ultraviolet (VUV) spectral regions. Low optical loss and laser durable fluoride optics are required for microlithographic applications. A nondestructive quasi-Brewster angle technique (qBAT) has been developed for evaluating the quality of optical surfaces including both top surface and subsurface information. The negative quasi-Brewster angle shift at wavelengths longer than 200 nm has been used to model the distribution of subsurface damage. By using effective medium approximation (EMA), the positive quasi-Brewster angle shift at wavelengths shorter than 200 nm has been explained by subsurface contamination. The top surface roughness (TSR) depicted by the qBAT is consistent with atomic force microscopy (AFM) measurements. The depth and the micro-porous structure of the subsurface damage measured by the qBAT, has been confirmed by magnetorheological finishing (MRF). The technique has been used to evaluate optically polished CaF₂ (111) and MgF₂ (001) surfaces.

A more precise and accurate method of quantifying line end effects on binary photomasks becomes necessary as reticle features continue to decrease in size. A new methodology for measuring and evaluating line ends was developed. By performing multiple step-wise measurements across a single line end feature using a fixed-width region of interest, a simulated representation of the line end profile could be generated. A high n-order polynomial fit was then applied to the resultant data set and a minimum line end value was extrapolated. This methodology reduced the measurement error directly caused by the region-of-interest (ROI) placement and sizing while, at the same time, it improved the accuracy and precision of the measurement. The generated line end profiles may be further used for modeling, simulation, or characterization.

We present an innovating method to measure simultaneously the specular and non specular diffraction pattern of sub-micronic periodic structures. The sample is illuminated at fixed wavelength in the visible range (green laser) versus a large angular aperture both in incidence (0 to 80°) and azimuth (0 to 180°). A special optical setup including Fourier optics and a CCD camera allows to measure the entire diffraction pattern. The measurement spot size can be reduced to less than 50μm and its position can be visualized directly with the same optical setup. Polarimetric measurements can be made in less than two seconds. This new system is presented in details and the accuracy of the measurement is tested on homogeneous reference SiO₂/Si samples. Then the system is applied to submicron gratings. We show that fixed incidence angle measurements are useful to visualize the specular and non specular order. So, the periodicity of the can be extracted directly. In addition the specular and non specular intensity can be used to extract more accurately the topology of the samples. We show that specular reflection versus azimuth angle can provide similar results than conventional techniques. First experimental results on bi-periodic structures are also shown.

The semiconductor industry requires ever smaller semiconductor structures with faster response times and more function per unit area of each chip. In addition, the industry is changing from 200 mm to 300 mm diameter wafers with fewer defects and rapid detection at all processing stages. To meet these needs, defect data must be processed in near-real-time to expedite correction of processing problems at the earliest possible stage. Under a Small Business Innovation Research (SBIR) program, sponsored by the Air Force Manufacturing Technology Division at Wright Laboratory, Dayton, Ohio, Sentec Corporation has developed a revolutionary technology for contaminant particle detection on unpatterned semiconductor wafers. A key to the Sentec technology is detection, not of the intensity of backscattered energy from particles or defects, but of the amplitude of the electro-magneitc field of this backscattered energy. This new technology will allow the detection of particles that are significantly smaller than those which can be reliably located using current scatterometers. The technical concepts for a stand-alone particle detection tool have been created. It uses a continuous scanning mechanism to perform high-speed examinations of target wafers. This tool, also, has the capability of quantifying the microroughness or background haze of a subject wafer and presenting that information separate from the contamination particle data. During the course of this project, three patent applications were filed.

We discuss the aspects of three-dimensional AFM metrology relevant to 90 nm node processes, with extensions to 65 nm node and beyond. Important advances have been made, including deployment of silicon tips with diameter less than 70 nm as well as development of a novel algorithm for tip shape deconvolution. As primary case studies, we present detailed analyses of process and materials issues encountered during poly silicon etch and during 193 nm photolithography. Etched poly silicon shows shape details at the bottom of the line that are known to impact device performance both directly (by defining the physical gate length) and indirectly (by screening ion implantation). Our data from one particular process show that etch shape (CD and sidewall angle) varies strongly as the line pitch decreases from 500 nm to 260 nm, with sidewall angle changing by approximately 0.8 degrees per 100 nm pitch change. We also present data for a different etch process in which both CD and sidewall angle vary systematically across the wafer from center to edge, with the range of sidewall angles being ~2 degrees and CD varying by 20 nm. Resist is seen to have height and sidewall angle variation with pattern density and with linewidth at a given focus-exposure process point. In addition, resist profiles before resist trim show footing, standing waves and 3-dimensional sidewall roughness that are readily visualized and quantified with AFM measurements.

This paper shows the basic numerical calculation methods for measuring linewidths between 45-80nm using normal and oblique incident lightwaves to control the resist and silicon linewidths for the next-generation semiconductor circuits. The shape measurement method by nondestruction and noncontact, using the light wave scattering method is called Scatterometry. While using the scatterometry with the actual manufacturing process, it is necessary to compare the characteristics in proportion to the trench shape with the measured values in the real-time. In this paper, we use the finite-difference time-domain (FDTD) method as the numerical analysis method. FDTD method takes a lot of time to analyze with the Maxwell equation in the time domain until the electromagnetic fields are stabilized. Then, the examinations on the methods for shortening the FDTD calculation times are carried out by using the periodicity and the sub-grids. By using the periodicity and the incident plane waves, we only calculate the electromagnetic fields in the half pitched region of the grooves. Next, FDTD divides the analytic region into main- and sub-grids. We only allocate the silicon substrates and air parts to the main-cells. The sub-grids are created by dividing in the main-grids in the resist parts, because the resist parts have to be exmained with the minute groove changes. The oblique incidence analysis is important for ellipsometry and many other applications. It is ascertained for silicon that the amplitude reflectance calculated by using FDTD agreed well with Fresnel's law for TE and TM modes to the largest angle. Then, the oblique incidence amplitude reflectance for the resist grooves on silicon is calculated. Finally, we confirm the FDTD analysis is effective to obtain the reflected light characteristics close to the real photolithographic models.

This paper shows basic numerical data for measuring the double periodic linewidths in the complicated LSI circuits using lightwaves. The double periodic areas, containing contact holes, memory arrays, and the mazy and arbitrary line structures are hard to analyze by the RCWA (rigorous coupled wave analysis). Therefore we analyze them using the finite-difference time-domain (FDTD) method. The 3D FDTD analysis is explained in this paper. The refleced electromagnetic waves in the near fields are obtained by the vertical plane wave incidences. The far field solutions are calculated using the numerical integration of the near field currents and the magnetic currents. Then, the scatterometry characteristics can be calculated as a far field by superimposing the scattering electromagnetic fields in a periodic reference surface (a square or rectangular region). Finally, we confirm the FDTD analysis is effective to obtain the reflected light characteristics close to the complicated real photolithographic models.

Adsorption and desorption rates of a 6-component hydrocarbon mixture and SO₂ have been studied on the surfaces of Ultra High Purity (UHP) components under the presence of parts-per-billion (ppb) contaminant levels. The dry-down rates are monitored to sub parts-per-trillion (ppt) levels. In the hydrocarbon test, stainless steel components are confirmed to be more effective than Teflon during dry-down. Dry-down rates for hydrocarbons on stainless steel (SS) surfaces depend on the molecular weight of the contaminant; heavier molecules take longer to dry-down. The dry-down study for SO₂ revealed that it will desorb from Teflon surfaces quicker than it will desorb from stainless steel. The result of UHP valves tested for outgassing indicates that Extreme Clean Dry Air (XCDA) was able to remove hydrocarbons to lower levels and cleanup faster than with a N₂ purge.