PROCEEDINGS VOLUME 5379
MICROLITHOGRAPHY 2004 | 22-27 FEBRUARY 2004
Design and Process Integration for Microelectronic Manufacturing II
IN THIS VOLUME

0 Sessions, 31 Papers, 0 Presentations
Overture  (2)
Modeling  (5)
OPC  (6)
PDS  (2)
MICROLITHOGRAPHY 2004
22-27 February 2004
Santa Clara, California, United States
Overture
Proc. SPIE 5379, DFM: magic bullet or marketing hype?, 0000 (3 May 2004); doi: 10.1117/12.546792
Proc. SPIE 5379, The rising cost and complexity of RETs, 0000 (3 May 2004); doi: 10.1117/12.546794
Gridded Layouts
Proc. SPIE 5379, High-performance circuit design for the RET-enabled 65-nm technology node, 0000 (3 May 2004); doi: 10.1117/12.538242
Proc. SPIE 5379, Minimizing mask complexity for advanced optical lithography, 0000 (3 May 2004); doi: 10.1117/12.536369
Proc. SPIE 5379, Manufacturability of the X Architecture at the 90-nm technology node, 0000 (3 May 2004); doi: 10.1117/12.536027
Proc. SPIE 5379, Taking the X Architecture to the 65-nm technology node, 0000 (3 May 2004); doi: 10.1117/12.536130
Proc. SPIE 5379, Standard cell design with regularly placed contacts and gates, 0000 (3 May 2004); doi: 10.1117/12.534538
Proc. SPIE 5379, Forbidden-area avoidance with spacing technique for layout optimization, 0000 (3 May 2004); doi: 10.1117/12.533640
Modeling
Proc. SPIE 5379, Feature level test patterns for characterizing residual process effects, 0000 (3 May 2004); doi: 10.1117/12.540685
Proc. SPIE 5379, A methodology to analyze circuit impact of process-related MOSFET geometry, 0000 (3 May 2004); doi: 10.1117/12.532860
Proc. SPIE 5379, DFM through correct process construction, 0000 (3 May 2004); doi: 10.1117/12.535496
Proc. SPIE 5379, Impact of lithography variability on statistical timing behavior, 0000 (3 May 2004); doi: 10.1117/12.537259
Proc. SPIE 5379, Design rule optimization for 65-nm-node (CMOS5) BEOL using process and layout decomposition methodology, 0000 (3 May 2004); doi: 10.1117/12.544234
Design and Layout
Proc. SPIE 5379, Manufacturing-aware design methodologies for mixed-signal communication circuits, 0000 (3 May 2004); doi: 10.1117/12.539591
Proc. SPIE 5379, Yield-enhanced layout generation by new design for manufacturability (DfM) flow, 0000 (3 May 2004); doi: 10.1117/12.536254
Proc. SPIE 5379, Taming pattern and focus variation in VLSI design, 0000 (3 May 2004); doi: 10.1117/12.538271
Proc. SPIE 5379, OASIS-based data preparation flows: progress report on containing data size explosion, 0000 (3 May 2004); doi: 10.1117/12.535683
OPC
Proc. SPIE 5379, Combining OPC and design for printability into 65-nm logic designs, 0000 (3 May 2004); doi: 10.1117/12.537655
Proc. SPIE 5379, Interaction of RET and MDP: optimization for reducing the mask writing time, 0000 (3 May 2004); doi: 10.1117/12.535653
Proc. SPIE 5379, Merits of cellwise model-based OPC, 0000 (3 May 2004); doi: 10.1117/12.535852
Proc. SPIE 5379, Extending aggressive low-k1 design rule requirements for 90-nm and 65-nm nodes via simultaneous optimization of NA, illumination, and OPC, 0000 (3 May 2004); doi: 10.1117/12.536982
Proc. SPIE 5379, Image fidelity verification: contourIFV, 0000 (3 May 2004); doi: 10.1117/12.537490
Proc. SPIE 5379, Mathematically describing the target contour in silicon such that model-based OPC can best realize design intent, 0000 (3 May 2004); doi: 10.1117/12.538047
Device and Process
Proc. SPIE 5379, A 65-nm node SRAM solution using alt-PSM with ArF lithography, 0000 (3 May 2004); doi: 10.1117/12.540311
Proc. SPIE 5379, Optimization of interconnection layout for multitransistor cell shrinkability, 0000 (3 May 2004); doi: 10.1117/12.535975
Proc. SPIE 5379, Designing high-performance cost-efficient embedded SRAM in deep-submicron era, 0000 (3 May 2004); doi: 10.1117/12.536016
Proc. SPIE 5379, Layout modification for library cell Alt-PSM composability, 0000 (3 May 2004); doi: 10.1117/12.538900
Proc. SPIE 5379, Patterning sub-50-nm Fin-FET using KrF lithography tool, 0000 (3 May 2004); doi: 10.1117/12.536040
Poster Session
Proc. SPIE 5379, CMP dummy pattern insertion with reduction in power supply voltage drops, 0000 (3 May 2004); doi: 10.1117/12.535991
PDS
Proc. SPIE 5379, Statistical analysis of poly line printability affected by sPSM manufacturing errors, 0000 (3 May 2004); doi: 10.1117/12.556623
Proc. SPIE 5379, Hybrid AAPSM compliance methodology to ensure design for manufacturing, 0000 (3 May 2004); doi: 10.1117/12.561828
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