The Advanced Mask Technology Center (AMTC) in Dresden is an equally-owned joint venture of Advanced Micro Devices Inc. (AMD), DuPont Photomasks, Inc. (DPI), and Infineon Technologies AG (Infineon) founded in 2002 to create a world-leading mask R&D center for both DRAM and logic applications. The AMTC's primary focus is research and development of sub-70 nm technologies. While 193 nm lithography will be used for 65 nm design rules and is probable for 45 nm design rules, solutions for sub-45 nm design rules are still being studied. Possible solutions include 193 nm immersion, 157 nm immersion, EUV, and EPL or its variants. The AMTC is actively involved in multiple collaborative projects to develop masks for advanced lithographies. This paper presents a sampling of AMTC's development activities on both conventional and EUV masks. Intensive studies on adequate materials and their properties for the respective technology have been performed with key partners in the field. Masks have been produced and analyzed. New repair processes have been developed for the small structures of future nodes, the printing capabilities have been predicted by AIMS measurements and analyzed with printing experiments at the respective wavelengths. In this talk we will present the latest results of simulations, experiments, handling and tool qualifications performed at the AMTC or with its partners. We will especially focus on our activities for the EUV technology and will present results on material and process development as well as on simulations for soft and hard pellicle induced distortions. For the EUV technology we will present preliminary results from our etching experiment on binary masks. First results on the performance of our new nano-machining RAVE tool will be shown.

Quartz dry etching is critical to realize the resolution enhancement technology (RET) mask, such as chromeless phase lithography (CPL) mask, alternating phase shift mask, and RIM type phase shift mask. Quartz etching is one of challenging processes in photomask manufacturing due to the absence of etch stopper. The requirements of quartz etching are sidewall angle, phase uniformity, depth linearity, and micro/macro loading effect in wide range of feature sizes. In this paper, we will discuss the improvement of quartz dry etching using Cr hardmask without any hardware modifications. We can control the tendency of phase uniformity across mask surface in convex or concave curvature with nearly vertical sidewall angle. Two-step quartz etching recipe, which consists of two kinds of sub-etching recipe, is introduced to meet the phase uniformity and quartz profile at the same time. We have optimized quartz dry etching with vertical sidewall angle, low depth uniformity, and low micro/macro loading effect.

The specification of mask global CD uniformity (GCDU) is ever tightening. There is no exception at the 65-nm node. Some of the key contributors affecting GCD non-uniformity is pattern-density effects such as fogging effect from the e-beam writer and macro loading effect from the etcher. In addition, the contributions from position-dependent effects are significant, and these contributions included resist developing, baking, as well as aberrations of the wafer-imaging lens. It is challenging to quantify these effects and even more so to correct them to improve the GCDU. Correction of the fogging and etch loading effects had been reported by various authors. In addition to correction for these effects, we are reporting the position-dependent effects in this paper. Currently, the fogging effect induces 5 nm of CD error and an additional 5~15 nm of CD errors is induced by the etch-loading effect within a 60-mm radius area. We improved the GCDU by pattern-dependent corrections. Using position-dependent dose correction in mask writing, we managed to effectively compensate for intra-field non-uniformity on wafer, which is induced by lens aberrations and illumination non-uniformity.

In this study, Cr defects resulted from high voltage E-beam writing in high Cr load Logic Mask were investigated. The Cr defect, which is a damage of anti-reflection layer on Cr, is mainly found in isolated Cr patterns of high Cr load Logic Mask. This defect appears under high voltage E-beam writing with high dose and dry etch process. High accelerating voltage and dose of E-beam writing decrease the thickness of remaining E-beam resist after developing. These phenomena are more significant in high Cr load Logic Mask consisted of isolated Cr patterns. Because the resist thickness of isolated Cr pattern is not enough for enduring dry etch process-induced damage, Cr surface is damaged during etching. Consequently, the Cr surface damage of high Cr load Logic Mask is related with voltage and dose of E-beam and dry etch process time. To prevent these defects, low accelerating voltage and dose of E-beam and low thickness of Cr layer to increase dry etch process margin are necessary.

Optimized process parameters using the TOK OEBR-CAN024 resist for high chrome load patterning have been determined. A tight linearity tolerance for opaque and clear features, independent on the local pattern density, was the goal of our process integration work. For this purpose we evaluated a new correction method taking into account electron scattering and process influences. The method is based on matching of measured pattern geometry by iterative back-simulation using multiple Gauss and/or exponential functions. The obtained control function acts as input for the proximity correction software PROXECCO. Approaches with different pattern oversize and two Cr thicknesses were accomplished and the results have been reported. Isolated opaque and clear lines could be realized in a very tight linearity range. The increasing line width of small dense lines, induced by the etching process, could be corrected only partially.

We investigated the film property and the lithographic performance of five commercialized NCARs. This report shows the relationship between chemical structure and EB lithographic performance, such as resolution, sensitivity and environmental stability. In this study, we found the good matching the matrix polymer, the cross linker and the photo acid generator(PAG) against NCARs issues. Furthermore, we could demonstrate the trade-off relation for lithographic factor and stabilized factor by chemical characteristics. This report suggests the strategy that was design of chemical structure for the next generation NCARs.

Moore's law has been guiding the semiconductor industry for four decades. Lithography is the key enabler to keep the industry on the technology treadmill. Lithographers have been facing unprecedented challenges during last five years to keep the technology on the technology treadmill by developing various kinds of resolution enhancement techniques (RETs). In low K₁ regime, co-optimization of design, layout mask, OPC, lithography and etching is the primary strategy to deliver a production-worthy patterning solution. Optical shrink is not a trivial task anymore. Intel always pursues parallel patterning techniques based on the dual exposure wavelength patterning strategy. While EUVL is the preferred patterning solution for 32nm node, 193nm immersion lithography with super high NA illumination is one of the parallel patterning strategies. The effects of polarization at super high NA illumination on mask technology, such as lens reduction ratio, blank absorber thickness and image imbalance correction, and restriction on design layout are addressed in this paper. Contact patterning is extremely challenging at low K₁. Contact shape factor (circularity) which impacts the design rule will be discussed in this paper. Explosion of data file size and mask write time, stringent mask CD control and mask defect disposition are direct consequences of low-K₁/high-MEEF (Mask Error Enhancement Factor) lithography. Mask makers alone cannot resolve the challenges in a cost effective manner. A seamless integration solution is a must.

The increasing complexity of Resolution Enhancements Techniques (RET) in optical lithography requires careful qualification of new reticle designs when they arrive at the wafer fab before commiting them to printing product. In order to qualify the reticle designs at the wafer level, process window qualification (PWQ) is performed by inspecting wafers printed with the reticles to be qualified. The output from the wafer inspection tool provides information on the regions of marginality within the reticle field or features within the die which can have a smaller than expected process window. tsmc Fab 6, an advanced high volume production foundry fab, uses an effective and efficient standardized PWQ procedure to qualify new incoming reticle designs described herein.

As originally submitted

We investigated that the root cause of the crystal growth on the reticles at 193nm excimer laser lithography. We confirmed that crystal growth consisted of ammonia sulfate. We investigated the relationship between crystal growth and 3 factors; reticle cleaning condition, exposure environment, and storage environment. We reduced the residual sulfate ion on mask surface by optimizing cleaning condition. On the evaluation of the wafer fab, total exposure energy until crystal growth occurred were increased as residual sulfate ion is reduced by the cleaning condition optimization. In order to evaluate influence of exposure environment, we carried out an irradiation test under mixture of oxygen and nitrogen up to 10kJ/cm2. We did not observe crystal growth up to 10kJ/cm2. We suppose that crystal growth might be prevented by controlling chemical environment. Regarding storage environment, amount of sulfate ion on the mask surface was increased when it was stored in certain kind of box. Out-gas from storage box is one of sulfuric ion source.

Growing application of 193nm lithography for low-k1 process has increased the appearance of progressive defects on reticles often known as haze, precipitates or crystal growth. Although the industry has identified multiple potential sources of these progressive defects, a high contributor is a combination of pollutant reactions from reticle manufacturing process and wafer fab environment. This paper will address the analysis of progressive defects and the associated studies focusing on the sources from possible mechanism to prevention methods. In this evaluation, a split study was performed looking at mask cleaning recipes, pellicle types and also the resulting contaminant on the reticles. The reticles were then cycled through 193nm exposure and then inspected on KLA-Tenor's latest best known inspection strategy to capture and characterize the progressive defects. Finally, the mask specification for contamination level, inspection method and re-clean frequency to meet the wafer fab requirements was established. Under these controls, the impact of progressive defects on wafer yield can be minimized.

In this study we investigated the defect due to pellicle frame materials for repeating exposure in months. Defects were found in the sub-pellicle and the defect density was high in the 4 corners compared to the center of the mask. The defects grew on MoSiON or the interface Quartz and MoSiON film, and the defect size was below 0.5 um. By analyzing with Raman Spectroscopy, defects consist of Ammonium Sulfates, Melamine Formaldade Resin and KClO₃. The evaluation method for cleaning process and pellicles was Ion Chromatography. According to Ion Chromatography analysis, the main composition of defect was substances of pellicle frame materials. Also we confirmed the pellicle frame effect with the exposure test.

To overcome the resolution limits of the current generation of steppers, mask makers are forced to include an ever-growing number of OPC features on 65 nm node masks. Although lithography techniques have improved significantly in the last five years, they have not kept pace with the needs of 65 nm technology. To produce viable OPC features at the 65 nm node, the etch process must be capable of accurately defining on the mask features as small as 100 nm. The etch must also show reasonable linearity to prevent distortion of the primary features. To this end, a four factor, irregular fraction factorial design was performed using a 4^th generation mask etch system. The factors in this design include RIE power, RIE coupling efficiency, ICP power, and pressure. These factors were selected for their influence on CD bias, CD uniformity, and CD linearity. The results of this design will be presented, along with an optimized solution. This solution is demonstrated on an asymmetric test pattern representative of logic or ASIC devices, as well as an evenly loaded pattern more representative of memory devices.

Studies on photomask quartz etching in a gas system consisting of SF₆, O₂, and He were carried out using an inductively coupled plasma (ICP) photomask etcher. A profilometer was used for etch rate uniformity characterization. Quartz etch was performed in the same chamber as was used for MoSi etching. The defectivity influence was also investigated so that the feasibility of MoSi and quartz etches in the same chamber was examined and discussed. Process optimization was studied by changing the Cr layer thickness, the O₂, SF₆, and He flow rates and gas composition, the ICP power and bias power, and the pressure. It was found that ICP power, bias power, pressure, O₂ flow rate, and He flow rate played an important role in determining etch performance. Plasma stability and etch performance were also investigated. An empirical kinetic equation was proposed based on experimental data and a quartz etch mechanism was also explained. Systematic etch non-uniformity resulting from radial and the side-to-side errors were also investigated in this study. High CD resolution (down to 100 nm), good etch rate linearity, extremely low etch rate dependency on photomask patterns with different loading, and repeatable etch rate produced an optimal etch process suitable for 90 nm and below technology node.

The move towards smaller feature size continuously requires more accurate lithography models. Part of models improvement comes from a better understanding of involved physics and chemistry. State of the art models assume development rate to be dependent on level of de-protection of resist film while development kinetics is not taken into account. Model refinements consist in getting a good model of development rate versus de-protection level. Recent studies have put in evidence the importance and the influence of development kinetics. Based on this, a new development process concept has been developed: the Proximity Gap Suction Development (PGSD). This paper presents a parallel approach to PGSD using megasonic agitation in order to improve development process understanding. Analysis has been performed by focusing on microloading effect characterization, also taking into account Critical Dimension (CD) linearity, CD iso-dense bias. Interpretation and analysis were achieved through use of DOE techniques. Results are then discussed with respect to previous PGSD studies but also to current development models. It is believed that improvement of development process could be also achieved in wafer making through the use of high flow rate development techniques such as PGSD or megasonic development.

CD control of FEP-171 is difficult due to abnormal CD variation in single puddle development. Fogging analysis patterns show that space CD in large open region is smaller than that in small open region. That is caused by develop loading effect, which is largely affected by developer dispensing condition in single puddle method. Double puddle development improves the abnormal CD trend and has a good CD uniformity (3sigma 5.4nm). Contrary to FEP-171, abnormal CD trend is not observed in UV-82(CAR). The low dissolution rate of FEP-171 is the cause of the abnormal CD trend. The yield of CD uniformity and MTT increases with applying double puddle method to FEP-171 process.

ZEP is a field-proven stable E-Beam resist for photo-mask manufacturing. The spin-spray develop method has been widely used for ZEP resist processing. Recently, we have successfully adopted the spin-stream develop process for ZEP resist by using modified TEL MARK-8 wafer process track. This paper presents a comparison result of CD uniformity between the conventional spin-spray method and new spin-stream method on 6-inch production halftone phase shift masks. In this process, we apply low temperature(18 deg. C) develop solution in room temperature ambient. The spin-stream process with low temperature solution is found to be a suitable recipe for high-end phase shift mask manufacturing with under 10 nm CD uniformity (3sigma) in 120mm X 120mm area. Moreover, the modified MARK-8 track can provide both of a FEP and a ZEP process module in one unit, and this advantage reduces the cost of ownership for a high-end mask manufacturing facility.

We did many numerical simulation of the modified model of drying process for the flat polymer (resist) film fabrication taking effects of latent heat and heat conductivity into account and studied effects of introducing latent heat and heat conductivity to the model. From those we clarified dependence of distribution of resist molecules on a substrate on latent heat of solvent. Moreover, we clarified why above characteristic dependence of distribution of resist molecules on latent heat appeared.

Mask critical dimension (CD) errors are analyzed in case fogging effect is corrected by dose modulation method with comparison of measurement and simulation. In the test mask, an extreme condition from pattern density 0% to 100% is applied for making fogging effect. On the ground of the utmost pattern densities which is one of the factors of fogging effect, various mask CD errors are observed with optical measurement in spite of fogging correction. Each error factor is distinguished from whole mask error using electron beam simulator which is adopting Monte Carlo (MC) calculation for electron scattering modeling, proximity effect correction (PEC) and even fogging effect correction. From error analysis, 3 kinds of mask error are observed. The first CD error is from an inaccurate modeling of fogging effect, the second is from fogging correction program. The third is error from development loading effect. The two formers are comparatively less important than the latter because they can be soluble problems by careful selection of fogging model or improvement of computing systems. However, error from develop loading effect is hard to solve so that not only chemical but also fluid mechanical approach is needed.

Progress towards 65nm next-generation lithography requires unprecedented global CD uniformity, with the actual ITRS 2002 roadmap proposing 4.2nm 3σ (dense lines) for 65nm binary masks. Since resolution requirements are satisfied only by using chemically amplified resists (CARs), exposure and post-exposure bake (PEB) are key processes to successful mask making, both introducing global CD errors. Develop and etch processes potentially contribute further global CD errors. The global CD uniformity can be improved significantly by adaptive PEB, especially for CARs showing moderate to strong PEB sensitivity, like NEB22. With the 25-zone hotplate of the APB5500 bake system, facilitated through a novel calibration mask with 25 equidistant temperature sensors within the resist plane, an appropriate temperature profile can be applied during PEB. This temperature profile is automatically calculated by an adaptive optimization algorithm, based on 2-dimensional spline fitting of a CD measurement. A CD-uniformity improvement (dense lines) from 3.80nm 3σ to 3.06nm 3σ (~20%) is achieved on evaluation photomasks with an 11x11 CD measurement grid.

The final reticle CD uniformity provides us with quantitative information but impracticable one to classify it into each step of the process. We then contrived a new method for quantifying process non-uniformity and classifying it into each of baking and development with properly utilizing resist behaviors in the process. We firstly tried to quantify baking non-uniformity by utilizing a resist behavior in coating film contraction to baking temperature. A resist film can be used just like a thermo-measuring device if the film contraction occurs significantly enough and linearly to baking temperature. Secondly, we tried to quantify development non-uniformity by utilizing a resist behavior in film dissolution by development. A resist film can be used as development speed-meter if the film reduction by the development occurs slowly enough and linearly. This paper describes a novel and convenient technique and its value to quantify process non-uniformity and classify it into resist baking and development.

In this paper, two negative-tone chemically amplified resists (CAR) are evaluated. The methodology and results are compared and discussed. The resists include EN-024M from TOK, and NEB 31 from Sumitomo. Both resists show high contrast, good dry etch selectivity, and high environmental stability. EN-024M showed good coating uniformity while NEB31 showed a coating uniformity problem. This was a round “dimple” approximately one centimeter in diameter of different thickness and density at the center of the plate. We addressed the “dimple” coating problem as described in the paper. Optimum PAB and PEB temperatures and nominal to maximum doses for isolated features were determined by running a matrix of PAB and PEB temperatures along with a dose series. We evaluated the process and compared the lithographic performance in terms of dose sensitivity, dose and bake latitude, resolution, resist profile, OPC (Optical Proximity Correction) pattern fidelity, CD uniformity, environmental stability, Line Edge Roughness (LER) and etching bias and resistance.

The combination of conductive topcoat ESPACER Z300 and positive tone CAR FEP171 was investigated in detail for the second level patterning of Alternating Aperture Phase Shift Masks (AAPSM) using e-beam lithography. Chrome load variations between 2 and 50% with the corresponding deviation of the second level pattern, homogeneously and unevenly distributed on the mask, had no significant impact on placement and overlay accuracy. No clear defect increasing could be measured when applying ESPACER top coat. The quartz etch selectivity of FEP171 was identically with the widely accepted laser resist IP3600 and a good etch depth linearity was achieved down to 200nm feature size. Finally, the performance of the developed process has been demonstrated on a 65nm node device design.

In the recent past Deep Ultra Violet (DUV) Laser generated photomasks have gained widespread acceptance for critical and semi-critical applications in semi-conductor lithography. The advent of stable, highly capable, single-layer Chemically Amplified Resist (CAR) processes has made fabrication of this type of mask very robust in today's mask manufacturing environment. This platform affords mask makers benefits of the highly parallel architecture available in today's DUV Laser pattern generators - providing excellent cost and cycle time advantages when compared with alternative leading-edge processes using 50 KeV VSB e-beam systems. To date literature on this topic has focused mostly on characterization and optimization of DUV mask making processes. Meanwhile treatment of the resultant aerial image for critical litho applications has been largely ignored. In this paper details of the aerial image produced using DUV Laser generated photomasks will be detailed. Both 248nm and 193nm source printing with multiple types of illumination will be discussed. Details of a print test comparison performed on photomasks from two popular mask lithography platforms in use today; DUV, and 50 KeV VSB, will be documented. Finally, the most recent process improvements achieved in DUV Laser mask fabrication will be detailed. Special attention will be given to the impact of these enhancements on image quality.

In Embedded Attenuated PSMs(Phase Shift Masks), chrome residues on MoSiON, especially at the edge of a pattern, should be decreasing the phase-shift effect and it must be also causing CD(critical dimension) variations in a wafer-process. Chrome residues on MoSiON are well known being generated at second level lithography or according to performance of cleaning process before it. In this paper, we investgated the influence of treatment on Cr surface during MoSiON etch process using CF₄ plasma and proposed the optimum treatment procedure to reduce the Cr residues originated form re-deposition of carbon-contained polymers in CF₄ plasma.

Organic compound contamination in a clean room is presently attracting attention as a serious problem in F₂ laser lithography. Certain organic compounds may possibly have absorption spectra in the vacuum ultra violet region (VUV), as has been indicated by various theoretical considerations. But the effects of organic compounds present on a substrate surface are as yet unclarified. This study was conducted to determine whether organic compounds on the surface of a substrate serve significantly to reduce the transmittance of the substrate. The substrates of F-doped SiO₂ glass and MgF₂ were made to adsorb organic compounds by two different methods. Transmittance was measured at 130 to 200nm and clearly found to decrease as a result of organic compound contamination. In the case of dry-cleaned substrates, transmittance was recovered to its original level. It thus follows from these findings that substrate transmittance is significantly reduced by organic compound contamination on the substrate surface in the VUV region.

In recent years, Quick-TAT (Turn-Around Time) in preparing masks is very important factor together with the complexity and cost in mask development and manufacturing in higher-end devices. Especially in the development phase of customer-driven devices such as SOC, MCU and so on, QTAT role of mask supply might get a larger weight in LSI business. However, overhead in workflow, system and burden of mask users (designer, etc) in mask making are significant, not to mention the increase of OPC processing time and DA cost. For responding to the efficient and precipitous manufacturing requirement even for complicated leading-edge devices, we should focus on the optimization of workflow system minimization of mask-work resources in users (designer, etc.). Therefore, new Renesas Integrated Mask Operation System (RIMOS) has been developed as making masks “Everywhen you want” supporting five key functions as follows: (1) Simple interface to input mask-making parameters on Web-based integrated system (2) Hierarchical specification system of high maintainability and capability for SEMI-P10 format (3) Easy operation to instruct build-in specification for manufacturing such as complicated CD inspection (4) Bi-directional synchronization between mask-shop and wafer-fabs MES supporting the flexible multi-pass supply of masks (5) On-line quality reporting for mask-SPC monitoring supporting. This paper shows architecture of the new system 'RIMOS' and the estimate of TAT reduction in workflow.

We have developed a new photomask inspection method which has capability for inspecting 65nm technology node reticles using 257nm wavelength light source. This new method meets the requirement for the current mask inspection system using KrF inspection light source to be employed even in the fabrication of photomasks for 65nm technology node by the appearance of immersion technology using ArF wavelength. This paper discusses the detection capability of the 257nm wavelength inspection system for the defects on the 6% ArF attenuated phase shifting masks for 65nm node, using DSM based test pattern mask.

As semiconductor integration goes down to nano-meter scale, finer patterning technology is inevitable. Therefore it is more and more important not only new lithographic development but also mask quality enhancement. Particularly, due to the delay of NGL technology, optical lithography is growing candidate for 65nm and beyond node device. In that case, mask CD uniformity and defect control issues are more important than ever. In mask inspection technology, there were a lot of new progresses to enhance the defect inspection sensitivity and stability via short-wavelength and advanced defect inspection algorithms. In this paper, we will present a concept and on going status of newly developed short-wavelength DUV inspection tool that is co-worked by Selete, Toshiba, and NEC. Moreover, we will discuss defect specifications that is required 65nm node and beyond technology node by simulations. This will include relations between defect inspectability and printability in the case of ArF, ArF immersion, and F2 lithography in various layouts and patterns. Through this study, we can conclude stable short-wavelength inspection tool and proper inspection algorithms are essential for future generation mask to cope with low k1 lithography.

As the design rule of the semiconductor devices approaches to 90nm node technology, the defect controllability of the photomask becomes critical success factor. The halftone defects generated in photomask cannot be easily judged because the results of Aerial Image Measurement System (AIMS) are flexible with the defect size and transmission. Also, the printability of halftone defect on wafer is not clear because of low sensitivity of inspection system for pinholes. In this paper, halftone defects with programmed size were fabricated by Focused Ion Beam (FIB) repair tool. We evaluated the transmission correlation of the halftone defects between printability with 248nm simulation tool and inspection machine with 365nm light source. We could make the judgment criteria of halftone defects captured by inspection machine without AIMS result from this correlation result. Inspection machines such as KLA-Tencor and Lasertec are used to verify the detectability of halftone defects. Wafer printability was simulated using AIMS fab 248. Even though the transmission of halftone defects is same, the energy intensity of large size defects is higher than that of small size.

A model has been developed using process yields and costs in order to judge the benefit of performing multiple inspections during the manufacture of reticles that employ multiple writing steps in their manufacture. The model presented is forward looking in terms of judging whether an additional inspection step will incur added cost to the manufacturing process. For this forward looking model, only subsequent process step costs and prior process step yield to the proposed inspection point is required.

A traditional method of mask quality control in a fab has been wafer image qualification i.e., wafer inspection on printed monitor wafer or wafer inspection on production wafer. But recently many fabs that are using DUV lithography for low k1 process are experiencing the progressive defect growth challenge (such as crystal growth, haze, fungus, precipitate etc.) on their photomasks. The quality of some reticles will worsen over time due to this progressive defect problem on the mask. Hence it is important to detect such problems before they start impacting the device yield. An evaluation was constructed in a Japanese advanced logic fab to compare the performance between traditional image qualification methods and direct reticle inspection using TeraStar STARlight. The goal was to determine if the TeraStar STARlight inspection could provide the sensitivity required to give early warning of progressive defects before image qualification can detect these defects. Evaluation results show that TeraStar STARlight is the most effective method in a fab to provide early warning to a progressive defect growth on reticle that is likely to print later during mask life.

We have studied stencil mask repair technology with focused ion beam and developed an advanced mask repair tool for electron projection lithography. There were some challenges in the stencil mask repair, which were mainly due to its 3-dimensional structure with aspect ratio more than 10. In order to solve them, we developed some key technologies with focused ion beam (FIB). The transmitted FIB detection technique is a reliable imaging method for a 3-dimensional stencil mask. This technique makes it easy to observe deep patterns of the stencil mask and to detect the process endpoint. High-aspect processing can be achieved using gas-assisted etching (GAE) for a stencil mask. GAE enables us to repair mask patterns with aspect ratio more than 50 and very steep sidewall angle within 90±1°precisely. Edge placement accuracy of the developed tool is about 14nm by manual operation. This tool is capable to achieve less than 10nm by advanced software. It was found that FIB technology had capability to satisfy required specifications for EPL mask repair.

The applicability of ultrafast laser 3D machining of transparent objects for photomask clear defects repair is investigated. The technology is based on patterning 3D shading elements inside quartz body of the photomask at the vicinity of clear defects in chrome layer, which effectively blocks the light for the duration of the photolithography process. Shading elements consist of an array of breakdown points in quartz, produced as a result of laser-induced breakdown and arranged in accordance with the size and location of the defects. Thresholds of bulk breakdown and chrome removal at laser irradiation from the back side of the photomask and their dependence on the pulse energy and height of focal point under chrome layer were obtained. Optical density of the shading element depends on the laser pulse energy, distance between breakdown points, the number of layers and the size of the shading element itself. To increase optical density multi layer shading elements were created. Ultrafast laser technology and a tool for photomask clear defects repair are described.

As 90 nm LSI devices are about to enter pre-production, the cost and turn-around time of photomasks for such devices will be key factors for success in device production. Such devices will be manufactured with state-of-the-art 193nm photolithography systems. Photomasks for these devices are being produced with the most advanced equipment, material and processing technologies and yet, quality assurance still remains an issue for volume production. These issues include defect classification and disposition due to the insufficient resolution of the defect inspection system at conventional review and classification processes and to aggressive RETs, uncertainty of the impact the defects have on the printed feature as well as inconsistencies of classical defect specifications as applied in the sub-wavelength era are becoming a serious problem. Simulation-based photomask qualification using the Virtual Stepper System is widely accepted today as a reliable mask quality assessment tool of mask defects for both the 180 nm and 130 nm technology nodes. This study examines the extendibility of the Virtual Stepper System to 90nm technology node. The proposed method of simulation-based mask qualification uses aerial image defect simulation in combination with a next generation DUV inspection system with shorter wavelength (266nm) and small pixel size combined with DUV high-resolution microscope for some defect cases. This paper will present experimental results that prove the applicability for enabling 90nm technology nodes. Both contact and line/space patterns with varies programmed defects on ArF Attenuated PSM will be used. This paper will also address how to make the strategy production-worthy.

Nanomachining has become a mainstream process for repairing photomasks. The advantages of nanomachining versus other repair techniques are improved edge placement, reliable depth control, and minimized substrate damage. This technique can be applied to any defect that requires a subtractive repair process. The process can be equally well applied to defects of any material including unknown materials. This paper evaluates the correlation of different inspection methods in characterizing nanomachined photomask repairs. The repairs were made using an nm650 mask repair tool manufactured by RAVE LLC. The repairs were inspected using a 248nm Aerial Image Measurement System (AIMS) and the Atomic Force Microscope (AFM) image produced by the nanomachining tool itself. These repairs were performed on 248nm MoSi photomasks. Results were compared to measurements by SEM and optical edge placement measurement techniques.

The effort to produce perfect dimension repairs of quartz bump defects on Alternating-Aperture Phase Shift Masks (AAPSM) has been brought to a new level with process developments to meet 90 nm technology node specifications. Decreasing photomask line and space dimensions pushes performance requirements for a mask repair system in terms of fine control in difficult to access structures on the mask surface. New repair strategies using a recently improved focused ion beam mask repair system for different defect types are discussed, along with their relative effectiveness. These strategies are then applied to the repair of full height extension and bridging defects in a line and space array. The role of quartz topography and its optical effects, Cr edge bias, and the combination of both strategies in a quartz bump repair are discussed. Additionally, effective process controls in repair are also discussed, along with analysis of metrology data received from a stylus nano-profilometer (SNP) system, and their relationship to potential imaging on the wafer by examination of AIMS data at a high numerical aperture. Several possible mask repair process flows are also reviewed in light of this work.

Mask data preparation (MDP) is a complicated process because many kinds of EB data files and jobdeck data files are used in mask manufacturers and EB data files continue to become bigger. Therefore we have developed unified mask data formats for Variable-Shaped-Beam (VSB) EB writers with efficient data compaction. The unified mask data formats are composed of a pattern data format for EB writers named "NEO" and a layout format named "MALY". We released NEO and MALY on April 2003. To evaluate NEO and MALY, we have made a prototype system of MDP such as a converter from design data to NEO/MALY and converters from NEO/MALY to each EB data. We have evaluated about functions and performance of the MDP flow using real design data in device manufacturers. As a result, some improvements in NEO and MALY were achieved and we have revised the specification of NEO and MALY as the final version. We have confirmed that NEO and MALY can be used for a set of unified mask data formats among VSB EB writers and can reduce complexity of mask data handling in mask manufacturers. They will be put to practical use in MDP flow.

An agile mask data preparation (MDP) approach is proposed to cut re-fracture cycle time as incurred by mask writer dispatching policy changes. Shorter re-fracture cycle time increases the flexibility of mask writer dispatching, as a result, mask writer's capacity can be utilized to its optimum. Preliminary results demonstrate promising benefits in MDP cycle time reduction and writer dispatching flexibility improvement. The agile MDP can save up to 40% of re-fracture cycle time. OASIS (Open Artwork System Interchange Standard) was proposed to address the GDSII file size explosion problem. However, OASIS has yet to gain wide acceptance in the mask industry. The authors envision OASIS adoption by the mask industry as a three-phase process and identify key issues of each phase from the mask manufacturer's perspective. As a long-term MDP flow reengineering project, an agile MDP and writer dispatching approach based on OASIS is proposed. The paper describes the results of an extensive evaluation on OASIS performance compared to that of GDSII, both original GDSII and post-OPC GDSII files. The file size of eighty percent of the original GDSII files is more than ten times larger compared to that of its OASIS counterpart.

The data volumes of individual files used in the manufacture of modern integrated circuits have become unmanageable using current data format specifications. A number of factors contribute to the problem: size, content and complexity of the designs are growing; the application of RET increases the vertex counts; complex data preparation flows post tape-out result in a large number of intermediate representations of the data and assembly steps are introduced for leveling critical parameters. Based on the choices for the mask making equipment the final result of the flow - the mask writer data - varies. While there is a continuous effort to improve the individual performance of the tools that handle the data, is has become apparent that enhancements to the entire flow are necessary to gain efficiency. Two ways are explored in the present study - the elimination of processing overhead and repeated execution of similar functions and the simplification of the data flow by reducing the number of formats involved. OASIS, the new stream format developed under the sponsorship of SEMI, has the necessary features to fullfill this role. The paper will describe the concept of OASIS as a common intermediate format in the mask data preparation flow and illustrate the benefits with experimental results. A concept for a common mask writer format based on OASIS will be proposed. It considers format dependencies for the mask writing performance for different type of mask writing equipment. Different implementation scenarios are discussed.

We reported the Guideline(Ver. 1) of Reticle Data Management(RDM) Activity in 2001. Among we have been focused SoC(System on Chip) Business, we have been improved the efficiency over Design technology, Mask manufacturing and Wafer manufacturing. Especially, these subjects have been the lithography Cost including Reticle Cost, shorter life cycle of product, more difficult technique, lower cost and shorter total TAT from design to chip shipping. Guideline Ver 1.0 announced the standardization of interface contents over Design to Mask manufacture, and to wafer manufacture. Guideline Ver 2.0 will announce this RDM activity has been developed the optimization of a new engineering chain management in addition to the pattern data and the linkage to EDA in 2003.

Complex layout features, especially two-dimensional features such as jogs and corners, are susceptible to photoresist pinching and bridging, even with the use of Optical Proximity Correction. Some of these problems arise due to improper interpretation of the design intent when determining the correction targets. These targeting problems result in excessively aggressive correction in the vicinity of two-dimensional features. Compounding the problem is the propagation of the effects of aggressive correction into 1 dimensional pattern regions, resulting in oscillatory deviations from the correction target along one-dimensional edges. Current correction processes use rules and geometric approximations based on the feature's size to generate a curved target for OPC tools to reference during correction. A new model-based methodology is proposed that will utilize significantly more pattern information as well as process information to determine how a feature should be interpreted. The model-based target construction reacts to pitch and other geometric variations within the model's influence. This targeting methodology is therefore able to predict a realistic shape for two-dimensional feature based on all pattern information within model proximity. The model-based manipulation reduces pitch and other proximity related effects for two-dimensional features, especially at more aggressive process nodes.

This paper presented an integrated simulation framework linking our in-house mask writer simulator and the optical lithography simulation engines to include the mask corner rounding effect in lithographic performance evaluations. In the writer simulator, a modified two-dimensional Gaussian function is used as the functional form of the convolution kernel (point spread function). Parameters of the kernel function for different writing machines are automatically extracted from scanning electron microscope (SEM) photographs of simple mask pattern geometries. The convolution results of the kernel and the mask layout form the intensity distribution for pattern definition. The isocontour of the resulting image at the desired level of bias can be regarded as a good approximation of the mask shape obtained from a real mask writer. The writer simulator then saves the contour data as the user-specified format of mask file for subsequent lithography simulations. With the aid of this simulation tool, the impacts of mask corner rounding effects on two-dimensional OPCed pattern for 90-nm and 65-nm node lithography processes are quantitatively evaluated. The results show the line end shortening (LES) is greatly influenced by mask corner rounding effects. The LESs in the 65-nm node process are over twice of those in the 90-nm node process. The resolution capability of a 2-stage 16X mask manufacturing process was also studied in this paper. Simulation results indicate the ArF lithography might be required to make this innovative mask-making technology suitable for 90-nm generation and beyond.

The theory of interference mapping lithography (IML) is presented for low k₁ (k₁<0.4) contact hole imaging. IML with a coherent source is shown to be analogous to methods used in creating a Fresnel lens. With IML for a partially coherent source, the interference map is calculated by using the first eigenfunction of the transmission cross coefficient (TCC). From this interference map, clear 0° AFs and for clear 180° AFs are placed in the optimal location. Thus, IML is a method to place AFs via a model. From the interference map, a method for creating a CPL mask is demonstrated. Using IML, techniques to optimize a binary mask or a CPL mask are presented for maximizing the exposure latitude (EL) or depth of focus (DOF). These techniques are verified with simulation. Using IML for maximum EL, a CPL mask with 100nm (k₁=0.39) contacts was created and exposed on an ASML /1100 ArF scanner using NA of 0.75 and Quasar illumination (σ_in=0.72, σ_out=0.92, span angle=20°). Measurements on the exposed wafers show that IML CPL results in printing 100nm contacts through pitch (200nm minimum pitch to isolated) with 0.45μm DOF at 10% EL.

The oldest lithography technique contact/proximity printing are widely used for research activity, most MEMS, Bio-Chip and Optical Electro devices can be fabricated by this method. In this paper, deep submicron 1x mask can be fabricated easily by using e-beam exposure, chemically amplified resist (CAR) and Cr dry etching, a chemical shrink method using dry/wet etching technology was proposed for nanofabrication by using Cr film as hard mask. Micro channel for biochip as well as micro lens for Optical Electro devices can easily be fabricated on glass and quartz substrates by this method.

Imaging contact and via layers continues to be one of the major challenges to be overcome for 65nm node lithography. Initial results of using ASML MaskTools' CPL Technology to print contact arrays through pitch have demonstrated the potential to further extend contact imaging to a k1 near 0.30. While there are advantages and disadvantages for any potential RET, the benefits of not having to solve the phase assignment problem (which can lead to unresolvable phase conflicts), of it being a single reticle - single exposure technique, and its application to multiple layers within a device (clear field and dark field) make CPL an attractive, cost effective solution to low k1 imaging. However, real semiconductor circuit designs consist of much more than regular arrays of contact holes and a method to define the CPL reticle design for a full chip circuit pattern is required in order for this technique to be feasible in volume manufacturing. Interference Mapping Lithography (IML) is a novel approach for defining optimum reticle patterns based on the imaging conditions that will be used when the wafer is exposed. Figure 1 shows an interference map for an isolated contact simulated using ASML /1150 settings of 0.75NA and 0.92/0.72/30deg Quasar illumination. This technique provides a model-based approach for placing all types features (scattering bars, anti-scattering bars, non-printing assist features, phase shifted and non-phase shifted) for the purpose of enhancing the resolution of the target pattern and it can be applied to any reticle type including binary (COG), attenuated phase shifting mask (attPSM), alternating aperture phase shifting mask (altPSM), and CPL. In this work, we investigate the application of IML to generate CPL reticle designs for random contact patterns that are typical for 65nm node logic devices. We examine the critical issues related to using CPL with Interference Mapping Lithography including controlling side lobe printing, contact patterns with odd symmetry, forbidden pitch regions, and reticle manufacturing constraints. Multiple methods for deriving the interference map used to define reticle patterns for various RET's will be discussed. CPL reticle designs that were created from implementing automated algorithms for contact pattern decomposition using MaskWeaver will also be presented.

We have developed a new mask technology to print small structures for three-dimensional integrated circuits. Aspects of the new technique provide for a novel photo mask for patterning small post features for an integrated circuit. The photo mask includes masked features having interior nonprinting windows. The interior nonprinting window is a phase shifter, while the area surrounding the masked features transmits light un-shifted. Thus any arrangement of features can be patterned with no phase conflict. In this paper, we will present a study of printing small post structures with pitch smaller than 0.26 μm by currently available KrF photolithography. Both alternating and chrome-less phase shifting masks are used to test the resolution limit. Resolution capability of various OAI techniques such as annular and quadrupole are analyzed by simulation and wafer printing images. This new photo mask with interior nonprinting phase-shifting window provides great improvement for resolving small post structures which having limited process window due to 2-D optical interference effects.

We evaluated the chromium-shielding attenuated phase shift mask (Cr-shield att-PSM) for the fabrication of fine hole patterns in 157-nm lithography. The transmittance of the phase shifter was set at 5% to achieve the best performance for 70- to 90-nm-diameter holes. Simulation and experimental results indicated that the optimum distance a between the pattern edge and the Cr-shield edge changed depending on the size and pitch of the holes. The optimum distance a for sub-70-nm-diameter holes was zero, which meant the binary mask gives the best depth of focus. In the case of 80-nm-diameter holes, the conventional att-PSM proved to be the best option for 1:1 hole patterns. For 1:2 hole patterns, the optimized distance a was 60 to 70 nm. For isolated hole patterns, the optimum distance a was 45 nm. After optimizing distance a, we confirmed the side-lobe control capability of the Cr-shield att-PSM through exposure experiments. The elimination of side-lobes greatly improved the resolution. Furthermore, we found that the mask linearity was improved through use of a Cr-shield att-PSM.

As the semiconductor-process technology advances towards the 90nm-node, more and more wafer-fabs start to use 193nm EAPSM (Embedded Attenuated Phase-Shift Mask) technology as the main lithography strategy for the most critical-layers. Because the 193nm EAPSM is a relative new technology in the semiconductor industry, it is important for us to understand the key-mask-specifications in a 193nm EAPSM and their impact to the wafer process windows. In this paper, we studied the effects of phase-angle and transmission to the wafer process window of a 193nm-EAPSM in a 300mm wafer-manufacturing environment. We first fabricated a special multi-phase EAPSM by a combination of extra Quartz-etch and Mosi-removal. We then used a high NA 193nm scanner (ASML-ALTA1100) and high contrast resist to perform the wafer-level printing study. To fully understand the impact of phase-angle and transmission to wafer process windows, we also used AIMS (Aerial-Image Measurement System) and Prolith simulation software to study the lithographic performances of various phase-angle and transmission combinations. By combining the wafer-level resist imaging printing results, AIMS studies and Prolith-2 lithography simulations, we proposed the practical phase-angle and transmission specifications for the 90nm-node wafer process.

Contact patterning for the 65nm device generation will be an exceedingly difficult task. The 2001 SIA roadmap lists the targeted contact size as 90nm with +/-10% CD control requirements of +/- 9nm¹. Defectivity levels must also be below one failure per billion contacts for acceptable device yield. Difficulties in contact patterning are driven by the low depth of focus of isolated contacts and/or the high mask error factor (MEF) for dense contact arrays (in combination with expected reticle CD errors). Traditional contact lithography methods are not able to mitigate both these difficulties simultaneously. Inlaid metal trench patterning for the 65nm generation has similar lithographic difficulties though not to the extreme degree as contacts. We have investigated the use of CPL mask technology for ArF contact hole imaging for sub-100nm contact imaging. The author's activities have been focused on the design, fabrication and integration of imaging technology. In this paper the author's emphasis will be on issues related to pattern layout, mask fabrication and image processing.

In this paper, the influence of dose modulation on CD trend by using electron beam exposure model has been investigated and simulated. To predict CD trend, we developed an analysis program, which shows the exposed energy profile and the corrected CD distribution in mask. First, it calculates the factor of fogging effect correction (D_f) from pattern density distribution with the assumption that fogging effect depends on only pattern density. And then it calculates the modified dose for correcting both proximity and fogging effect. From dose distribution, the corrected CD is calculated analytically by using e-beam lithography model: see Figure 1. It can give a glance how the dose modulation method has an influence on the CD uniformity. Moreover, the result of global error correction such as side, radial error at the mask writing stage has been analyzed in this study.

We have developed a high alignment-accuracy electron beam (EB) mask writing processes of phase shift layer using alignment-and-height marks. The new process consists of (1) First layer writing with “alignment-and-height” marks on peripheral area of the mask patterns; (2) Development of resist, Cr etching of the first layer pattern and coating of new resist; (3) Measurement of position, height and rotation of “alignment-and-height” marks with electron beams; (4) Create alignment map, scanning distortion correction map for the second layer writing; (5) Second layer pattern writing using these correction maps. We performed a set of evaluation test of the processes and confirmed that an overlay alignment accuracy of within 16nm (3 sigma) between first and second layer is attainable, and thus, practically effective for phase shift image writing of 65nm node masks.

The shortening of electron beam settling time is important for the shortening of writing time of variable-shaped beam (VSB) writers. The settling time is the time until the electron beam is deflected to a desired position, and is settled. In the case of electrostatic deflector, the electron beam is deflected in proportion to the voltage to which the amount of deflections is supplied. The Digital-Analog converter and Amplifier (DAC/Amp) circuit supplies voltage required for deflector and, in order to shorten a settling time; it is necessary to accelerate operation of a DAC/Amp circuit. Especially, the amplifier operation speed should be accelerated. The performances required of amplifier are high-speed operation and high-voltage operation. The key technology for high speed and high voltage operation of amplifier is the development of high speed, high voltage operation transistor. Although these two performances are the relation of a trade-off, the transistor that has attained our required performances dose not exists. For this reason, we started from joint development of the transistor, which had attained the required performances. Furthermore, we developed the trial peace amplifier using the developed transistor and evaluated. In addition to these results, we will also report the result of the throughput evaluation using the pattern for supposing the 65nm node device pattern.

Semiconductor manufacturing and associated industries contain many applications that require precise positioning. Indeed, as feature sizes decrease, applications that could once utilise standard scale encoders for position feedback must migrate to high-accuracy laser interferometers. Traditionally, these interferometer systems have been perceived as being expensive, complex and intrusive. This paper covers a range of recent homodyne interferometer developments, including a novel fringe detection scheme that utilises an integrated photodetector, and also a fibre optic laser beam delivery system that enables light to be routed straight to the measurement axis without additional external steering optics. The resultant system provides the user with low noise, low latency, position feedback signals that can be interpolated to provide sub nano-meter resolution. These and other developments directly address the negatives associated with traditional interferometer architectures and firmly establish homodyne interferometry as comparable in performance to the more complex heterodyne schemes.

Measurement by AIMS is the final step of mask defect control, and its accuracy is the critical issue to make guaranty and improve the mask quality. AIMS157 has developed by Carl Zeiss SMS GmbH and is expected to make a contribution to accelerate the 157nm lithography technology development. AIMS157 has been challenging to solve 157nm specific optical issues with accuracy for 65nm node photomask specifications. This paper discusses the defect measurement by AIMS157. Evaluation using programmed defect mask, repeatability is analyzed changing the optical parameters. Static and dynamic measurements were evaluated and the result shows the improved accuracy. It shows the possibility to be applied on 65nm node and smaller feature size.

The technology node of semiconductor device production is progressing to 65nm generation. For the 65nm photomasks, the target specifications of defect size and repair accuracy are 52nm and 7nm, respectively. Especially, real defects on photomasks are not only simple two-dimensional patterns but also three-dimensional shapes such as phase shift defects and contamination, thus we need to recognize defect shapes accurately. Additionally, AAPSM's Cr patterns overhang, and we have to measure defects on three-dimensional shapes. To evaluate them, we use an AFM metrology system, Dimension X3D (Veeco), having both precise CD measurement repeatability (2nm) and high resolution for defects. In this report, we show the performance of the AFM metrology system. First, we evaluated CD metrology performance, CD repeatbility about four type photomasks: NEGA-BIM, POSI-BIM, KrF-HT and ArF-HT, and all masks met specifications. Next, we evaluated defect pattern shapes and AAPSM and CPL mask patterns. Consequently, we have confirmed that the AFM metrology system has high performance for 65nm photomasks.

The mask pattern edge profile's impact on critical dimension (CD) metrology and printing performance was investigated. Three 193nm attenuating PSMs with intentionally changed pattern edge profiles were made. The three masks had patterns with different CD data width, so that we could chose isolated lines and holes from each mask that gave almost the same CD when measured by a mask CD-SEM. We chose patterns that were measured approximately 400nm and 800nm for isolated lines, and approximately 500nm for isolated holes, and simulated their wafer CD by an AIMS tool and found not only that the AIMS results were different from the mask CD-SEM, but also that the difference was not constant for the three masks. Though in this work, the pattern edge profiles were intentionally changed and were far beyond the actual deviation range in current photomask manufacturing, this meant that the mask CD-SEM might face a difficulty in accurate wafer CD prediction if we should take the pattern edge profile into account. In this work we employed an atomic force microscope (AFM) based mask CD metrology tool, and by comparing the output profile with cross sectional SEM observation, we confirmed that the tool can observe the pattern edge profile nondestructively. If, at a certain slice, this tool can output the same CD as the AIMS for the three masks, we thought that this tool might be a promising candidate in wafer CD prediction. We found that the optimal slice level for the CD-AFM depended on the pattern category. For 400nm isolated lines, a 40% slice was optimal, while an 80% slice was optimal for 800nm isolated lines. For 500nm isolated holes, the range of 30 to 40% show good match between mask metrology and AIMS. Though the cause of this difference among pattern categories should be investigated further, from the fact that a certain slice can match the mask CD and AIMS, we concluded that the CD-SEM was a promising tool for wafer CD prediction.

As lithography wavelengths reduce, the depth of focus decreases rapidly as well, resulting in the need for flatter photomasks with specifications under 0.25 microns. As the industry begins to extend 193 nm technology to smaller line widths, and with the significantly tighter flatness requirements for 157 nm and EUV masks, it will become necessary to inspect finished masks for flatness. By measuring the mask flatness after the pellicle has been mounted, the deformations caused by stress relief due to exposure of the reticle and mounting the pellicle can be taken into account reducing the overall uncertainty of the lithography process. This paper describes measurement techniques applied to a tool that utilizes near normal incidence interferometry to perform concurrent flatness and thickness measurements on finished reticles, as well as other techniques to bring the reticle flatness measurements more in line with the exposure tools. The flatness of the reticle is a critical aspect of the lithography system performance. Without sufficient control over flatness, the features on the image plane become distorted, resulting in image placement errors. As the line widths become finer, and especially in the case where wavelengths are being extended beyond their original nodes, control of the reticle flatness becomes more critical. In many cases, the last time the reticle flatness is measured, is after the photoresist is applied, or even as far back as the blank state. The influence of later changes such as film deposition, exposure, and pellicle mounting may only be accounted for through tightening the flatness spec on the blank itself. By measuring the flatness later in the process, it is possible to have greater control over the individual process steps, and to meet the flatness requirements for the lithographic process without excessively tight tolerances upstream. In order to interferometrically measure the reticle flatness with the pellicle mounted, it is necessary to either measure the surface through the pellicle, or through the back surface of the photomask. In either situation there will be interference patterns generated between the reference surface, the pellicle, the reticle surface, and the back surface of the photomask, as well as interference between each of these surfaces and each other. In the case of hard pellicles for 157 nm lithography, an extra surface is introduced. The total number of potential interferograms for a reticle with a soft pellicle would be 6, and for a hard pellicle 10. Retrieving the information about the surface of interest then becomes very complicated. The Corning Tropel UtraFlat is a near normal incidence interferometer with some unique measurement advantages over traditional normal incidence interferometers. By illuminating the surface at approximately 45° angle of incidence, it is possible to eliminate extraneous fringe patterns optically by limiting the spatial coherence of the laser source. Limiting the spatial coherence optically eliminates fringe patterns from surfaces far apart due to the relative shear distances of these interfered beams, while maintaining signal from the closer surfaces. In this manner it is possible to restrict the measurement data to the back surface flatness, or the backside flatness plus the thickness variation of the mask in a controlled manner. Utilizing this same technique from the pellicle side, it is possible to measure pellicle flatness and thickness variation in its final, mounted state, a key factor in overall system performance for 157 nm lithography. Figure 1 shows an example of an interferogram from a photomask blank measured from the backside with flatness and thickness variation fringes. Figure 2 shows the isolated backside flatness as well as the front side flatness measured by combining the thickness variation and backside flatness from a reticle with a pellicle mounted. Figure 3 shows the change in form over a 130 x 130 mm quality area caused by mounting the pellicle to the reticle. An alternative technique for tracking late process changes is to store the blank front and back surface measurements before coating, exposure, and pellicle mounting, and by measuring the back surface flatness through each of these steps, it is a simple matter to track the changes in the form from each step directly in the back surface, and apply this shape change to the front surface measurement. This technique has advantages later in the process since a finished reticle may have significant variation in reflectivity due to exposure, resulting in high frequency contrast variation on the thickness variation fringes, which may complicate the previously discussed methods. By increasing the control over late process flatness changes, it should be possible to improve reticle performance more directly than simply tightening the requirements on the blanks. Most importantly, it is the finished reticle flatness that the lithography process requires, and not simply the blank flatness. By measuring the finished reticle the performance is known, not simply implied, ensuring that the real lithographic needs are met, which are becoming more and more stringent as line widths and wavelengths reduce.

The interaction of probe and sample is a well known factor affecting the measurement accuracy of atomic force microscopy (AFM). The emergence of ultra-sharp carbon nanotube tips provides a good approach to minimizing the distortion of the measured profile caused by interaction with the finite probe tip. However, there is nearly always a significant tilt angle resulting when the nanotube is attached to an ordinary probe. As a result, we can obtain an accurate sidewall image of only one side of the linewidth sample rather than two sides. This somewhat reduces the advantage of using nanotube probes. To solve this problem, a dual image stitching method based on image registration is proposed in this article. After the first image which provides an accurate profile of one side of the measured line is obtained, we rotate the sample 180° to obtain the second image, which provides an accurate profile of the other side of the line. We keep the sidewall data for the better side of each image and neglect the data for the other side of each image. Then, we combine these better two sides to yield a new image for which the linewidth can be calculated. The sample is inevitably located at slightly different spatial positions in the two measurements. Image registration based on an improved iterative closest point (ICP) method was applied to remove the position difference between these two images. We are working to demonstrate that the calculated sidewall angle and linewidth value after registration and stitching is more accurate than obtained from only one image.

Dynamic speckles appear when a diffuse object moving in a plane is illuminated by a Gaussian light beam. The statistical properties of dynamic speckles produced in the Fresnel diffraction field by a diffuse object moving along x-axis with constant velocity are investigated in this paper. The space-time correlation function of the dynamic speckle intensity fluctuation is discussed in detail by using a weak random phase screen as a model of the diffuse object. The parameters describing the properties of the space-time cross-correlation of dynamic speckles, such as average grain size, translation distance and correlation distance, are given under some special conditions. It is shown that the statistical properties of dynamic speckles depend on the optical condition, surface roughness, and moving velocity of the object. The relation of translation and boiling motions of the dynamic speckles and the optical condition and surface roughness is discussed. The possibility is presented for measuring the roughness of the object using the correlation function of dynamic speckles.

An EUVL mask consists of a multilayer, a capping layer, a buffer layer, and an absorber layer formed on a glass substrate with a low coefficient of thermal expansion. The buffer layer protects the multilayer during the repair of absorber defects. In this study, Ru, Cr, and CrN were investigated as buffer layer candidates, and their etching selectivity with respect to a TaGeN absorber, DUV defect inspection contrast, and film stress were compared. Ru was found to be the most promising material of the three.

In Extreme Ultraviolet Lithography, the electromagnetic modeling of the mask allows to determine the influence of the mask structure on the electromagnetic field and on the aerial image. It is very useful to study the effect of the shape absorber on the CD shift. This effect, called shadowing effect, is analyzed in this paper. A simple geometrical approach to address this phenomenon is presented first. It is shown that although it can qualitatively be drawn some first orders conclusions, this over simplified view is unable to explain the complex behavior of the reflected light field. A rigorous method is still the more adapted method to assess the influence of the geometrical parameters of the features on the mask to control the CD shift on the printed resist. This study is especially focused on the absorber edges slope. It is demonstrated the choice of edge angles can minimize CD shift or keep a constant CD width.

Mask blank inspection is a critical issue in EUV lithography. Visible-light inspection has the advantages of a high throughput and a low tool cost, while actinic inspection potentially has a high inspection capability. The Hamamatsu Photonics Super Fine Particle Detection System, which employs dark-field scattering optics, has a high detection sensitivity and throughput. It is able to detect PSL spheres with diameters below 50 nm on a Si substrate. So, we tried using it to detect fine PSL spheres on Mo/Si multilayer mask blanks. 60-nm PSL spheres were detected, but noise arising from the surface roughness of the Mo/Si multilayer prevented the accurate detection of PSL spheres with diameters of less than 50 nm. Thus, it is important to reduce the surface roughness of the multilayer in order to improve the inspection capability of visible-light inspection systems.

MIRAI Project has developed a novel actinic (at-wavelength) inspection tool for detecting critical multilayer defects on EUV mask blanks using a dark-field imaging and a laser-produced plasma (LPP) light source. The first milestone of proof-of-concept was successfully achieved by demonstration of programmed defect detection accurate to 70nm in width and 2nm in height without any detection of false defects. Characterization of this experimental actinic inspection tool is ongoing to define the detailed specification of a proto-type tool. One of the important factors that define the sensitivity of the inspection tool is the signal to noise ratio available from the inspection image. In this paper, characterization results of background fluctuation and through focus imaging are presented. The characterization of background fluctuation suggested that the pixel-to-pixel fluctuation by spatial fluctuation of roughness is smaller than originally assumed possibly because of the smoothing by the aberration of the imaging optics. The negative impact of the degradation of defect signal by the aberration at the best focus is relaxed due to the smoothed fluctuation of the background intensity.

200-mm stencil masks for electron beam projection lithography (EPL) have been developed. Since they are not so rigid as photomasks because of their structure, 200-mm wafers with about 8,000 membrane windows, new metrological techniques dedicated to stencil masks have be introduced. Image placement (IP) accuracy of an EPL mask is evaluated with a suspension-type electrostatic chuck introduced to a Leica LMS IPRO. The dynamic repeatability of global IP measurements was 27 nm (3σ). It was confirmed that global IP errors were reduced to 60 nm (3σ, max) by linear-term and gravity corrections.

Image placement (IP) error of a 1x stencil mask is a concern for proximity electron beam lithography (PEL) when considering its application in the 65 and 45-nm nodes. According to our preliminary overlay budget for the 65-nm node, the global IP over the mask and the local IP within each membrane should be kept less than 10 and 7 nm, respectively to fulfill the total overlay accuracy of 23 nm. In this paper, we demonstrate the mask structure and the data processing method that enables the mask to be fully compatible with the local IP requirement in those technology nodes.

Masks for low energy electron proximity projection lithography (LEEPL) are fabricated starting with 200 mm silicon-on-insulator (SOI) wafers. The effect of the thickness of the buried oxide (BOX) layer of an SOI wafer on its flatness has been investigated. The wafer flatness is found to decrease as the BOX layer becomes thin. When the SOI layer (Si membrane) is not doped by B or P, the membrane has a compressive stress even for a 0.2 μm thick BOX layer. A monitor mask with image placement (IP) marks on a single-large (24 mm square) membrane area has been fabricated, starting with an SOI wafer with an 1.1 μm thick stress-controlled SOI layer and a 0.2 μm thick BOX layer. The internal stress of the membrane was 19 +/- 6 MPa (3σ) (tensile), and the membrane flatness was 0.8 μm. An ES chuck for an LSM-IPRO, which holds a mask in the method compatible with that in LEEPL exposure tools, has been installed. Chucking reduced the mask flatness from 22 μm to 10 μm while the membrane flatness was kept less than 1.0 µm. The dynamic repeatability of IP measurement was 7.6 nm (x) and 4.8 nm (y) in 3σ. The IP error of the monitor mask that had only IP marks was 17 nm (x) and 17 nm (y) in 3σ, satisfying the specification of 30 nm or less.

PATACON-LEEPL is a software product for converting semiconductor mask CAD data to the EB data of masks for LEEPL transcribing devices. This software has several functions, such as pattern placement function corresponding to the structure of the LEEPL mask, which is different from the mask for optical steppers, complementary division function for stencil masks, correction of distortion due to mask internal stress, and alignment mark insertion. This software operates in the environment in which several to some hundreds of Linux PC's are connected by a high-speed network.

PATACON-EPL is a software product for converting semiconductor mask CAD data to the EB data of masks for EB steppers. This software has several functions, such as pattern placement corresponding to the structure of masks for EB steppers, complementary division for stencil masks, stitching for deforming the shape of a portion for connecting divided portions, proximity effect correction, machine control data generation, mask inspection data generation, and alignment mark insertion. This software operates in the environment in which several to some hundreds of Linux PC's are connected by a high-speed network.

The contact layer has been said to be the first application of NGL technologies such as EPL or LEEPL, in which stencil masks are used. Since the computation time depends on the number of edges of patterns, contact layer data which contains many rectangles takes very long time to process. Actually it has been reported that the complementary split of the contact layer patterns take longer time than any other layer like metal layer or poly line layer due to the numerous small rectangle patterns in the contact layer. This paper presents a new innovative algorithm, called gravity point method, to dispatch contact patterns very quickly onto complementary masks. The results show that the new gravity point method algorithm is effective for the huge size of contact layer data.

In the present paper, a mask structure called adhering mask for excimer laser ablation is introduced. This mask is fabricated directly on the etched material, so it needn't a supporting chip and it thus has high transmission. Its absorber is made of gold and is fabricated by UV LIGA technology. Therefore the mask has more accurate structure and more smooth edges. This mask can fulfill the direct etching of the polymers by using a simpler optical system and can be a method of the mass production to some extent. The other mask is developed for X-ray lithography. It is made by UV LIGA process too. It consists of the substrate, the absorber and the supporter. The substrate is made of PI and the absorber is prepared by gold. The structure, fabrication process and experiment results of this mask are given.

Photomasks are currently inspected based on the standard of defect size. A shortcoming of this standard is that the type of defects which do not impact on a wafer, could be detected as impermissible defects. All of them are subject to repair works and some of them require further inspection by AIMS. This is one of the factors that are pushing down the yield and the turnaround time (TAT) of mask manufacturing. An effective way to improve this situation will be to do the repair works selectively on the defects that are predicted to inflict a functional damage on a wafer. In this report, we will propose a defect evaluation system named ADRES (Advanced Photomask Defect Repair Evaluation System), featuring a function to extract edges from a mask SEM image to be passed on to a litho-simulation. A distinctive point of our system is the use of a mask SEM image with a high resolution.

A new DUV die-to-database high-resolution reticle defect inspection platform has been developed. This platform is designed to meet the 90nm through 65nm node 248/193nm lithography reticle qualification requirements of the IC industry. These design nodes typically include: COG layers, EPSM layers, and AltPSM layers, plus aggressive OPC which includes jogs, serifs, and SRAF (sub-resolution assist features). The architecture and technology of the new inspection platform is described. Die-to-database inspection results are shown on standard programmed defect test reticles, as well as, advanced 90nm through 65nm node reticles from industry sources. Results show high sensitivity and low false detections being achieved.

The extension of dry-ArF optical lithography to the 65nm node imposes many challenges to photomask makers. More than likely a flavor of Alternating Aperture Phase Shift Masks (AAPSM) will be used on the most advanced lithography layers. Although the development of AAPSM masks has validated the resolution improvement, production issues are still present. Strategies for defect inspection, disposition, and repair of quartz defects at this technology node are still in development. A comprehensive strategy for the disposition and repair of quartz defects on AAPSM photomasks will be presented. The work utilizes a 65nm node, 193nm lithography based, AAPSM programmed defect mask comprised of multiple defect types at multiple quartz depths. A strong emphasis for the work is given to 60-degree phase defects. Both a Zeiss AIMSfab 193 aerial image microscope and a FEI SNP9000 scanning probe metrology tool is used to disposition the defects. The printability of defects at various illumination settings will also be reported. Repair solutions for the defects that do “print” is also presented.

In this paper, we present the test results obtained from the first commercial electron beam mask repair tool. Repaired defect sites on chrome-on-glass masks are characterized with 193nm AIMS to quantify the edge placement precision as well as optical transmission loss. The electron beam mask repair tool is essentially based on a scanning electron microscope (SEM), therefore, it can be used for in-situ CD and defect metrology. E-beam for EUV mask defect repair is also discussed. These early results are very encouraging and demonstrate the basic advantages of electron beam mask repair as well as highlight the key challenge of charge control.

The 65nm photomasks have to meet tight specifications and improve the production yield due to high production cost. The 65nm optical lithography has two candidates, 157nm and 193nm, and we are developing two types of experimental photomask repair systems, FIB and EB, for the 65nm generation. We designed and developed FIB and EB beta systems. The platforms of beta systems consist of anti-vibration design to reduce outer disturbance for repair accuracy. Furthermore, we developed a new CPU control system, especially the new beam-scanning control system that makes it possible to control the beam position below nanometer order. These developments will suppress transmission loss and improve repair accuracy of the systems. We also adopt the 6-inch mask SMIF pod system and the CAD data linkage system that matches the EB mask data image with the SED image to search defects in photomasks with sophisticated patterns such as OPC patterns. We evaluate the EB repair process, and confirm that it generates carbon film, which has possibility to generate the same quality as that of FIB. Furthermore, we confirmed that EB and FIB repair systems were able to deposit carbon film and etch chrome, quartz, and MoSi. In this paper, we report the photomask defect repair experimental systems and the feasibility study on photomask defect repair for the 65nm generation.

Advanced masks such as CPL and DDL are the two leading low k1 lithography enablers for the upcoming 90nm and 65nm nodes. The mask generation methodologies for both have been clearly defined with convincing wafer printing results. We found that full-chip optical proximity correction (OPC) is by all means one of most critical components for CPL and DDL. The OPC process ensures the correct 2D pattern shapes and to achieve the desired CD to be printed on wafer with sufficient process margin. However, in addition to the already complex mask data generation, the OPC process further increases mask data complexity and more prone to data handling errors. It is therefore highly desirable to perform full-chip Manufacturing Reliability Check (MRC) prior to mask making. From our viewpoints, MRC needs to cover two goals: first is to single out the “weak printing spots” or to map out the treated CPL/DDL features with unacceptable DOF and exposure latitude so that the corrective actions can be taken, and second is to ensure printing of the entire chip to meet the process requirement. The success of MRC process depends on a well-trained modeling algorithm, which should be well capable of predicting the optical and resist behavior correctly across the entire chip. To perform a production worthy MRC for CPL (with two mask writing steps) and DDL (with two exposure masks), one must have a full knowledge of the mask generation principles for both. In this paper, we demonstrate a working scheme that has been designed to capture a variety of geometric variations on the treated mask layout that could lead to unacceptable printing performance. In this scheme, the MRC for CPL and DDL are handled in two separate modules and the final MRC data is characterized and classified into specified category. The predicted error points were reported and displayed through statistical analysis. Process tolerance during mask making was also taking into consideration. For the optimum MRC performance, we try to balance the wafer pattern fidelity, data complexity, and the mask cost. The fix suggestions for the failure discovered can be automatically proposed for some of specified layouts. This MRC method could also be applied to all types of PSM or multi-exposure mask.

We will review the evolution of photolithography since its implementation in production of semiconductor IC devices. We will show how, at every forecast end of its existence, we have found new ways to prolong its life well beyond what was thought possible, and are now considering driving it to the limits of Physics. We will show how the development of new materials has, in almost all cases, been the enabling factor to implementation of new, lower wavelength photolithgraphies. We will discuss the factors driving the economics of lithography and how this has previously, and continues to have, a pivotal influence on which lithography technique is implemented into production. The likely limits of photolithography below 50nm resolution will be shown together with the factors likely to finally force us out of photolithography.

Model based optical proximity correction (OPC) to enhance image fidelity and process robustness has become one of the most critical components that enable optical lithography tackling 45nm node and beyond. To meet the challenges imposed by the previously unthinkable low k₁ for manufacturing with most stringent dimension control requirements, a capable model OPC to meet such an aggressive lithography challenges has been urgently called upon. In addition to providing better accuracy for the currently implemented process technologies, the new model OPC must work well with Chromeless Phase Lithography (CPL) in which the topography on the mask is rather significant, and Double Dipole Lithography (DDL) in which two masks and two exposures are needed. It must also be able to intelligently take into account the effect from the more aggressive illuminations, such as customer designed illuminator and experimental measured illuminator profile from the scanners. This capability is very important since the real illuminator pupil can impact OPC accuracy. The physical and mathematical foundation of the model must be well thought of to meet the requirement for the above-mentioned applications. We have developed a novel Eigen Decomposition Model (EDM) for model OPC treatment applicable for all types of advanced binary and phase-shifting masks. Together with a full 2D model calibration and verification methodology, the results from this new model OPC have proven to achieve a superb CD accuracy with versatile capabilities for extreme low k₁ imaging application. This report will explain how the model works with example applications and actual wafer results.

Tolerance-based process proximity correction (PPC) verification methodology is proposed for “hot spot management” in LSI fabrication process flow. This methodology verifies the PPC accuracy with the features of actual processed wafers/masks and target features in CAD data including CD tolerance around hot spots. The CD tolerance in CAD data is decided according to device characteristics, process integration, CD budget, and so on, and is used for the judgment criteria of the PPC accuracy. After the verifications, the actions in the manufacturing are decided. This methodology is demonstrated for the 65nm-node CMOS local metal at three representative hot spots extracted by lithography simulation, and the results yielded useful information for the manufacturing.

Double Dipole Lithography (DDL) has been demonstrated to be capable of imaging complex 2D patterns for full-chip application. Due to inherently high aerial image contrast, we have found that there is strong potential for this technology to meet manufacturing line width roughness (LWR) and critical dimension uniformity (CDU) requirements for the 65nm node using ArF binary chrome masks or 6% attenuated phase shift mask (AttPSM). For patterning at k₁ less than 0.35, DDL is a Resolution Enhancement Technology (RET) that offers an acceptable process window without resorting to costly hard phase shift masks. To use DDL for printing actual IC device patterns, the original design data must be converted into “vertical (V)” and “horizontal (H)” masks for the respective X and Y dipole exposures. An improved model-based DDL mask data processing steps has been demonstrated that it is possible to convert complex logic and memory data to X-Y dipole exposure compatible layout. Due to the double exposure, stray light must be well controlled to ensure uniform printing across the entire chip. One solution to minimize stray light is to apply large patches of chrome in open field areas to reduce the background transmission during exposure. Unfortunately, this is not feasible for most poly gate masks using a positive resist process. In this work, we report an improved model based DDL layout conversion methodology for full-chip application. A new generation of DDL technology reticle set was developed to verify the performance. Background light shielding is a critical part of the DDL. We report an innovative shielding scheme to minimize the negative impact of stray light for the critical features during double exposures.

A new phase shifting film system based on tantalum and silicon dioxide is presented. The tantalum film works as a transmission control layer and furthermore as an etch stop layer due to its good etch selectivity. The silicon dioxide phase control layer is tuned to 180° phase shift. Excellent laser stability and chemical durability were already shown. The two layer system can be easily tuned to various transmission values for three different lithography wavelengths. Transmission and phase shift uniformity fulfill already the final production specifications according to ITRS. An optimized deposition process yields excellent film surface roughness values equal to an uncoated substrate. Defect density could be significantly reduced recently. First SEM pictures of structured films show promising results.

We have developed a new pattern correction method to improve the uniformity of gate width and thus transistor characteristics. It is well known that the width of the gate pattern as exposed with an alternating phase shift mask (alt-PSM) varies along the gate width direction, owing to the optical-intensity maxima within the phase shifter regions on both sides of the gate. Since the positions of the maxima depend on the shifter height, the pattern pitch and the illumination conditions (σ and NA), the degree of distortion of the gate length also depends on these factors. We have found that the optimal segment size for optical proximity correction (OPC) of gate distortion also depends on the above factors and should be determined by simulation prior to OPC. From our simulations, shorter segments do not necessarily lead to higher correction accuracy, and the optimal size is strongly related to the degree of distortion. Based on these observations, we propose a novel correction method, in which the look-up table of optimal segment size as a function of shifter height and pattern pitch is referred to in the model-based OPC flow. The advantage of the method has been shown by comparing the correction results to those from the ordinary model-based method, with the latter focusing on the line-end regions where the distortion effects are most remarkable.

The alternating phase-shift mask (alt. PSM) is one of the most effective approaches to improve a resolution of the 65nm logic gate structure in ArF lithography. Previously we have studied the optimization of alt. PSM in 180nm gate-pitch. In this study, we evaluated various alt. PSM in the case of 160nm gate-pitch. Using a rigorous electro-magnetic field simulation of light scattering in 3D mask topographies, we evaluated CD difference between π-phase and 0-phase space size (the π-0 CD difference), resist CD through pitch and normalized image log-slope (NILS). The parameters for our simulation were mask structure (shallow trench depth (ST), undercut size (UC), space bias, Chrome (Cr) CD, pitch, phase shift depth) and ArF exposure condition (NA, sigma, defocus). From the results of simulation, it turned out that single trench structures with UC and/or space bias showed the good intensity balance through defocus. We compared the simulation results with the AIMS fab193 (Carl Zeiss) results and found there was no large difference. The combination of UC and space bias could be chosen as suitable structure for 160nm gate-pitch.

Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET's). The race to smaller and smaller geometry's has forced device manufacturers to k1's approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.

Chromeless-Phase Lithography (CPL) combined with IML (Interference Mapping Lithography) technology is experimentally demonstrated as a viable resolution enhancement technique (RET) to pattern low-k1 (0.39) contact holes (CHs) from dense through sparse pitches. Both the process latitude and the MEEF values are measured. The most promising single exposure techniques combine off-axis-illumination (OAI) with the use of non-printing assist features, as in the case of CPL with IML. Contrary to other RETs, CPL does not use sub-resolution assist features but non-printing assist slots with a well-chosen phase (180° or 0°) and transmission (0% or 100%) assignment. The optimization and the positioning of assist features result of IML, based on a mapping of the field intensity at the wafer level: the assist features interfere to enhance the image at the contact hole location. The experimental layout optimization is discussed, showing how the process is maximized together with the dose-margin before any side-lobe printing. Using ArF immersion lithography at 0.75 NA with Quasar 20° σ_out=0.92 / σ_in=0.72, the CPL printing performance of 100 nm contact holes, from 200 nm pitch through isolated, is measured. The Depth-Of-Focus at 8% Exposure Latitude (DOF @ 8% EL) remains above 0.4 μm through pitch, with 0.43 μm DOF @ 8% EL at the difficult 300 nm pitch. The MEEF becomes a multi-dimensional metric on CPL masks. The wafer CD uniformity depends not only on the size variation of the CH on the reticle, but also on the size variations at the two reticle write steps, i.e. the assist slots opening and the Cr removal. The MEEF metrics related to the CH and slot sizes appear as the most critical ones. For each of those parameters, measured MEEF is always below 3.

With each new technology generation, photomask manufacturing faces increasing complexity due to shrinking designs and accelerating use of reticle enhancement techniques. Denser and more complex patterns on the mask result in lower yields and long write and turn-around times, important factors for the rapidly increasing mask related costs in IC manufacturing. Laser pattern generators operating at DUV wavelengths were recently introduced to provide cost effective alternatives to electron-beam systems for printing of high-end photomasks. DUV wavelengths provide the required resolution and pattern fidelity. Optical tools that use raster writing principles and massively parallel printing ensure short and predictable write times for photomasks almost independent of pattern complexity. One such high-volume production system, the Sigma7300, uses spatial light modulator (SLM) technology and a 248 nm excimer laser for printing. Partially coherent imaging and multi-pass printing as in a lithography scanner further increases resolution and pattern accuracy. With four-pass printing the system provides resolution and pattern accuracy meeting mask requirements for critical layers at the 90-nm node and sub-critical layers at the 65-nm node and beyond. The paper discusses how mask layout can be optimized to take full advantage of the speed potential provided by the SLM-based writer. It shows how flexible use of the writing principle can provide cost effective writing solutions for many layers in high-end mask sets. Resolution and pattern accuracy results from the Sigma7300 will be presented together with write times for different types of designs.

The ALTA 4300 system has been used to successfully write many advanced designs previously only possible with 50kV VSB systems. In order to further enlarge the application space of this high productivity system, an aerial image enhancement technique has been developed to deliver mask patterns that more closely match the pattern data for corners and jogs. This image enhancement is done in real time in the ALTA system's rasterizer by modifying the gray level mapping of pixels near the corner vertexes. SEM measurements of corner rounding with standard rasterization and the enhanced rasterization show a 35% improvement of corner rounding radius from ~205 to ~132 nm. A direct comparison of SEM micrographs show little qualitative difference between vector scan mask features and those written with aerial image enhancement. This convincingly demonstrates that the ALTA 4300 system with the new image enhancement can write many layers requiring vector scan corner acuity.

A new electron beam mask writer, HL-7000M, has been developed for mass production of 90 nm node photomask and, research and development of 65 nm node mask. A series of adjustments to improve CD accuracy provides us a novel systematic solution for VSB system optimization. By applying a novel constant-gain method for linearity adjustment, linearity range, for designed size ranging from 0.3 um to 1.0 um, has been improved to < 3 nm for line and space pattern, the maximum XY discrepancy is 2 nm. Both experimental and theoretical studies for shot-divided patterns, which are often generated in OPC pattern conversion, have been applied. By modification of the shift term in beam size correction, exposure results for such shot-divided patterns, for divided pattern size varied from 500 nm to 1 nm, are improved to be less than 5 nm in range.

The rapid shrink of device dimensions requires reduced feature size on reticles and hence, improved CD uniformity and CD measurement precision in order to achieve tight process control. To meet this on-going trend the industry is in a quest for higher resolution metrology tools, which in-turn drives the use of SEM metrology into standard mask and manufacturing process. This paper concentrates on one specific area of Mask Metrology, being measurement of 2D (Two Dimensional) features such as contacts with sub resolution features -0 using a new SEM metrology tool, the Applied Materials' RETicleSEM. We consider the basic requirements for performing 2D measurements on a reticle as well as the algorithmic development to generalize a solution for these requirements. We consider three main requirements from such algorithm: a) It should be generic and deal with general shape features; b) It should provide new geometric metrics - such as contact area and corner roundness; c) It should measure new geometric patterns such as OPC (Optical Proximity Corrections) features and small CDs. We discuss the following issues/challenges related to the development of a generic algorithm for general shape 2D analysis: a) Limitations of the standard approach for Contacts qualification based on the Area loss measurement (Area based). b) A generic segmentation of the feature. It should be robust to noise, as well as brightness and contrast changes. c) The complexity of two dimensional general shape features metrology, especially OPC measurements. Limitations of the standard CD SEM metrology based on metrics describing simple geometric shapes such as ellipses and lines. The obtaining of new metrics can be useful as handles for advanced process control (i.e. what to measure on the 2D feature with complex shape such as contact with OPC structures).

Optical Critical Dimension (OCD) measurements using Normal-Incidence Spectroscopic Polarized Reflectance and Ellipsometry allows for the separation of transverse electric and transverse magnetic modes of light reflected from an anisotropic sample as found in a periodic grating structure. This can provide the means for determining line widths and analyzing complex profiles for a variety of structures found in mask fabrication. The normal-incidence methodology maintains much of the simplicity in mechanical design found in a standard reflectometer and the additional polarizing element has no effect on the footprint making the system amenable for integration, inline monitoring and advanced process control. The Rigorous Coupled Wave Analysis (RCWA) method provides an exact method for calculating the diffraction of electromagnetic waves by periodic grating structures. We have continued development of OCD technology to critical measurement steps in the photomask fabrication process: After Development Inspection (ADI), After Etch Inspection (AEI) for binary and phase shift masks. Additionally, we have demonstrated the ability of monitoring the mask CD quality with the presence of a protective pellicle. The determination of important critical dimensions in photomasks via optical techniques is appealing for several reasons: the method is non-destructive to photoresist and the sample is not subject to charging effects; the technique is capable of measuring the critical dimensions of grating structures down to approximately 40 nm; finally, minimal facilities are required for installation (no high vacuum, cooling or shielding of electromagnetic fields). Results will be presented showing the capabilities of OCD metrology for ADI, AEI and masks monitoring applications that emphasizes how the technology can be incorporated at many steps in the mask manufacturing process.

Development of OPC strategies, both model-based and rules-based, can be greatly accelerated by identifying and minimizing metrology bias during OPC iterations. The CD-SEM edge-detection algorithms best suited for precision on 90 nm and 65 nm node ground-rule structures often do not provide linear response across a wide range of line sizes, line-end gaps and other structures of interest during OPC refinement. To ensure that reliable metrology data is being fed into the OPC calculation engine, reference measurements that are independent of (a) feature size, (b) feature shape and (c) material composition must be made to optimize CD-SEM edge-detection for this application. We show the importance of on-line atomic force microscopy (AFM) measurements to improve CD-SEM measurements and speed turnaround of OPC model generation. Measurements are made on through-pitch and through-size lines and spaces, both after litho and after etch and compared with CD-SEM measurements.

The Aerial Image Measurement System (AIMS)* for 193 nm lithography emulation has been brought into operation successfully worldwide. A second generation system comprising 193 nm AIMS capability, mini-environment and SMIF, the AIMS fab 193 plus is currently introduced into the market. By adjustment of numerical aperture (NA), illumination type and partial illumination coherence to match the conditions in 193 nm steppers or scanners, it can emulate the exposure tool for any type of reticles like binary, OPC and PSM down to the 65 nm node. The system allows a rapid prediction of wafer printability of defects or defect repairs, and critical features, like dense patterns or contacts on the masks without the need to perform expensive image qualification consisting of test wafer exposures followed by SEM measurements. Therefore, AIMS is a mask quality verification standard for high-end photo masks and established in mask shops worldwide. The progress on the AIMS technology described in this paper will highlight that besides mask shops there will be a very beneficial use of the AIMS in the wafer fab and we propose an Automated Reticle Defect Disposition (ARDD) process. With smaller nodes, where design rules are 65 nm or less, it is expected that smaller defects on reticles will occur in increasing numbers in the wafer fab. These smaller mask defects will matter more and more and become a serious yield limiting factor. With increasing mask prices and increasing number of defects and severability on reticles it will become cost beneficial to perform defect disposition on the reticles in wafer production. Currently ongoing studies demonstrate AIMS benefits for wafer fab applications. An outlook will be given for extension of 193 nm aerial imaging down to the 45 nm node based on emulation of immersion scanners.

Linearity improvement for critical dimension (CD) measurement of a photomask by the simulation assist (SA) method with a deep-UV microscope is proposed. In the conventional method, if the measurement pattern is resolved insufficiently with a deep-UV microscope, the CD cannot maintain linearity to the actual pattern size. In the SA method, the insufficient resolution is canceled by the actual image and the simulated image, and therefore the CD can maintain linearity even if the pattern is resolved insufficiently. The experiment result indicates that the SA method improves CD linearity of the conventional method; furthermore, it improves repeatability of hole patterns.

Many technological challenges exist for the timely introduction of successive generations of integrated circuits with decreasing feature size. Lithography at dimensions commensurate with those described in the International Roadmap for Semiconductors at technology nodes with half pitch ≤45nm will require complex masks for 193nm immersion or EUV masks. ISMT has a five-year alliance with the State University of New York at Albany to develop EUV mask blanks and EUV resist. A process line to develop low defect extreme ultraviolet (EUV) mask blank multilayers is operational. ISMT is also working with commercial suppliers, who are fabricating EUV mask substrates and multilayer-coated mask blanks. Tools and processes for fabricating, inspecting, reviewing defects and repairing defects for EUV mask blanks are being developed as well. In addition, standards for EUV mask blank requirements and strategies for maintaining defect free EUV masks are being investigated.

We proposed an actinic (at-wavelength) EUV mask blank inspection method providing a printable phase-defect detection capability within the whole area of the mask blanks in an allowable inspection time. The inspection tool based on our method consists of optics for illuminating a mask blank with an EUV light, a mask blank stage, Schwarzschild optics for dark-field imaging, and a CCD camera. Phase-defect detection experiments were performed using a 10 Hz LPP source and with 0.2 NA imaging optics with the center obscuration NA of 0.1. Two-dimensional dark field image signal of 0.5 mmX0.5 mm area was captured by the CCD camera with 1M pixels and the phase-defects with the size down to 70 nm were successfully detected. In addition, a programmed phase defect and natural defect with 2 nm height were clearly detected. Inspection time including image capture and data processing for 0.5 mmX0.5 mm area was approximately 2 second. This is equivalent to an inspection time of 800 seconds/cm². Inspection speed will increase by more than 10 times when combined with high power light source and high speed data acquisition. Although further optimization is needed, possibility of actinic inspection of EUV mask blanks within a practical inspection time has been demonstrated.

The Coefficient of Thermal Expansion (CTE) uniformity and the surface finish performance of the low expansion glass-ceramic material produced by Ohara called CLEARCERAM-Z HS were investigated relative to the SEMI P37 specifications for Extreme Ultraviolet Lithography (EUVL) Photomask Substrates. The study on the CTE uniformity utilizing precision CTE measurement system based on Fizeau Interferometry with a single ppb/degree C level repeatability revealed that the standard deviation of the latest product CTE (+19 to +25degree C) data was 0±10ppb/degree C, which meets the Class B CTE specification in the SEMI P37 with statistical confidence and was improved from the previous report (0±15ppb/degree C, Class C). For the surface finish performance, the flatness data less than 100 nm (meeting Class A in the SEMI P37) and the roughness of 0.15nm Rms (Conforming to the SEMI P37) were demonstrated. Additionally the roughness uniformity was investigated and shown to be 1% in the coefficient of variation. By reviewing the data and performances from actual measurements, the suitability of CLEARCERAM-Z HS for EUVL Photomask Substrate material is discussed and updated. Also, preliminary R&D data of a new CLEARCERAM-Z material now under developing to response to the further requirements from EUVL community are introduced.

Using ruthenium (Ru) material as an extreme ultraviolet lithography (EUVL) mask blank multi-layer (ML) capping presents many advantages over silicon (Si) capping layer. Its high resistance to oxidation has been tested in EUVL optics. Ru capped ML mask blank also demonstrated very high etch selectivity during both mask absorber etch when the blank has no buffer layer and during buffer etch when the blank contains buffer layer. Due to higher EUV light absorption, Ru capping layer usually has to be much thinner than that of Si capping layer. As a result, long-term mask lifetime with thin Ru capping layer and its stability during multiple mask cleans becomes a concern. To address these concerns, we developed a process that improves Ru capped ML reflectivity for a given capping thickness. We further demonstrated the shelf lifetime stability of Ru capped ML mask blank and stability during multiple mask cleans. In this paper, we will discuss the detailed performance of Ru capped ML blanks, which includes mask blank reflectivity performance for different capping thickness, Ru capped ML mask blank shelf lifetime stability and cleaning stability performance. Mask patterning results using Ru capped ML blanks will also be presented.

EUVL mask process of absorber layer dry etching and defect repair were evaluated. TaGeN and Cr were selected for absorber layer and buffer layer, respectively. These absorber layer and buffer layer were coated on 6025 Qz substrate. Two dry etching processes were evaluated for absorber layer etching. One is CF4 gas process and the other is Cl2 gas process. CD uniformity, selectivity, cross section profile and resist damage were evaluated for each process. FIB-GAE and AFM machining were applied for absorber layer repair test. XeF2 gas was used for FIB-GAE. Good selectivity between absorber layer and buffer layer was obtained using XeF2 gas. However, XeF2 gas causes side etching of TaGeN layer. AFM machining repair technique was demonstrated for TaGeN layer repair.

Electron projection lithography (EPL) is a viable candidate for moderate-volume production of systems-on-a-chip (SoC) for the 65 nm node and beyond. Making EPL a realistically applicable technology depends strongly on how well its infrastructure is developed. Many developments related to EPL, including those by Selete, are currently under way. The world's first full-field EPL exposure tool, the Nikon EB stepper, NSR-EB1A, was shipped to Selete. In the installation stage, the tool produced 70 nm line and space, 50 nm isolated line, and 80 nm contact hole resolution. EPL resist performance is approaching 50 nm resolution and 5 μC/cm² sensitivity and commercial availability. Sample EPL stencil masks are also available from three mask suppliers in Japan. Beta mask defect inspection and repair are also available, as is data processing software for EPL mask making. Such software has reduced processing time and data volume using PC clusters and hierarchical processing. The results of the first of EPL trial device fabrication showed good resolution for hole patterns at about 70 nm and the usefulness of EPL in hole delineation. EPL is thus being steadily improved and elements are commercially available, underscoring EPL's feasibility as a practical technology. Issues that remain to be solved include better EB stepper performance, faster resist, more accurate masks, the demonstration of practical inspection and repair tools, and verification software. These issues are, it should be noted, engineering issues rather than basic EPL issues. EPL remains the most promising candidate for the 65 nm node and beyond, especially for hole delineation. Selete is continuing EPL development, working with suppliers of exposure tools, resist, masks, and inspection and repair tools, and software targeting lithography for 65 nm, 45 nm, and 32 nm nodes.

A new inspection system for stencil mask using transmission electron beam (E-beam) has been developed to detect defects on masks for Electron Projection Lithography (EPL) and Low Energy E-beam Proximity projection Lithography (LEEPL) for 65nm design rule and beyond. For high-performance image acquisition, the combination of multi-line Time Delay integration (TDI)- CCD camera and electron optic system (EOS) have been achieved very wide field-of-view and accurate imaging in this system. In Image Processing Unit, “Multi Algorithm Processing” is used for defect detection. One of “Multi Algorithm Processing” focuses on defects at corners of patterns. This is a new and very flexible algorithm to detect corner defects. It realizes very high detection performance compared with conventional Die-To-Database inspection. The minimum detectable defect size is smaller than 1 pixel. The pixel size is 50 nm for EPL mask and 30 nm for LEEPL mask. The performance of the system also has been confirmed using resist pattern wafer inspection results after EPL and LEEPL printing.

In electron projection lithography (EPL), a proximity-effect was the most significant problem to critical dimension (CD) control. It was remarkable, especially when beam blur was as large as the minimum pattern size. We have developed proximity-effect correction software for EPL to solve this problem. First, this software made a correction table automatically. In this table, the optimum biases were given for various backward-scattering energy levels and beam blurs regarding all kinds of model patterns. Next, every pattern edge was classified in any of the model patterns. Then, the bias for each edge was determined taking certain proportion between the correction table bias and the previous bias. After that, pattern shape was modified. Those processes were iterated until every change in bias was less than 0.5 nm. Finally, stitching pattern features were added. This software was tested using actual 70-nm rule chip data. Errors in energy level for various kinds of patterns were better than 3 percent and line end shortening was successfully corrected. Data size expansion after the correction was about 10 percent. Processing time was about 10 hours on six PCs cluster system. In conclusion, this software provides enough CD uniformity and pattern fidelity for EPL practically. In addition, this software is applicable to not only EPL but also to EB-direct writing.

A production-compatible method for the correction of image-placement (IP) error over a 1x stencil mask as used for proximity electron lithography (PEL) has been demonstrated. The mask IP error as measured using a newly developed metrology tool was fed forward to the PEL stepper, LEEPL-3000 and corrected for via the fine deflection of the electron beam. The overlay errors with respect to the substrate patterned by the ArF scanner have decreased from 63.6/59.3 nm to 26.1/36.4 nm in the x/y directions, but they are still larger than the errors of 15.2/14.8 nm for the conventional feedback method. Therefore, some improvements in the metrology method, the mask chucking method, the mask flatness and so on are required.

We report the first evaluation results for the printability and detectability of mask defects on a 1x stencil mask as used for proximity electron lithography (PEL). The defect printability has been defined for the patterns after the multi-step etching process through the tri-layer resist system inherently required for the use of low-energy electrons and the substrate. According to the three-dimensional lithography simulation, this definition is preferable to the conventional one based on the resist patterns prior to the etching process in the point that smoothing effects on defects are automatically taken into account. The critical size of printable defects as defined is 22 nm for 140 nm contact holes, while the stringent value of 16 nm is predicted in the conventional definition. Also, the detectability of the printable defects has been assessed by using the transmission electron-beam (EB) inspection tool. The assessment has been performed for both programmed defects and real defects occurred in contact-hole arrays. For the programmed defects, the perfect repeatability has been demonstrated for all the defects with printable sizes. In addition, real defects with the size of 15 nm have been successfully detected in the contact-hole arrays. Therefore, this study has demonstrated the manufacturability of PEL masks from the viewpoint of defect inspection.

The etching loading effect is always a big issue for mask maker to get excellent critical dimension (CD) uniformity. For etching process, with different loading area density the etching rate is different and then micro-loading issue exists. In accordance with the shrinking of patterns on ultra-large scale integration (ULSI), higher CD accuracy on photomask is required. For the 130nm technology node, the SPEC of CD uniformity range is about 17 ~ 22nm. At common poly layer, the distribution of pattern density is from 50% ~ 90%. The CD variation with different pattern density is 15 ~ 20nm. Besides adjusting the etching recipe to minimize the loading effect, we provide another solution. With loading effect correction (LEC) function on HL-950M, it offers a software method to calculate the pattern density and produce a dosage map to compensate the CD variation which is resulted from etching loading.