PROCEEDINGS VOLUME 5683
ELECTRONIC IMAGING 2005 | 16-20 JANUARY 2005
Embedded Processors for Multimedia and Communications II
ELECTRONIC IMAGING 2005
16-20 January 2005
San Jose, California, United States
Low-Power Architectures and Analysis
Proc. SPIE 5683, Instruction-level power dissipation in the Intel XScale embedded microprocessor, 0000 (8 March 2005); doi: 10.1117/12.585564
Proc. SPIE 5683, Energy-efficient H.264 video decoding on VLIW embedded processors, 0000 (8 March 2005); doi: 10.1117/12.589673
Proc. SPIE 5683, Application-specific low-power hybrid FPGA architecture design, 0000 (8 March 2005); doi: 10.1117/12.593286
Processor Architectures
Proc. SPIE 5683, Breaking the I/O bottleneck for high-compute performance processing with Xtensa LX configurable and extensible processor architecture, 0000 (8 March 2005); doi: 10.1117/12.586013
Proc. SPIE 5683, 32b RISC/DSP media processor: MediaDSP3201, 0000 (8 March 2005); doi: 10.1117/12.586072
Proc. SPIE 5683, Dynamic reconfiguration of streaming graphs on a heterogeneous multiprocessor architecture, 0000 (8 March 2005); doi: 10.1117/12.586112
Proc. SPIE 5683, A novel predicated data flow analysis based memory design for data- and control-intensive multimedia applications, 0000 (8 March 2005); doi: 10.1117/12.593236
Processors for MPEG-4 and H.264
Proc. SPIE 5683, Embedded architecture for fast implementation of H.264 subpixel interpolation, 0000 (8 March 2005); doi: 10.1117/12.586053
Proc. SPIE 5683, MediaBench II video: expediting the next generation of video systems research, 0000 (8 March 2005); doi: 10.1117/12.587955
Proc. SPIE 5683, A hardware architecture for a context-adaptive binary arithmetic coder, 0000 (8 March 2005); doi: 10.1117/12.596811
Proc. SPIE 5683, Efficient mapping of the H.264 encoding algorithm onto multiprocessor DSPs, 0000 (8 March 2005); doi: 10.1117/12.593980
Compiler and Software Tools for Embedded Processors
Proc. SPIE 5683, An improved approach of register allocation via graph coloring, 0000 (8 March 2005); doi: 10.1117/12.586295
Proc. SPIE 5683, H.264/AVC deblocking filter correlation analysis in embedded systems, 0000 (8 March 2005); doi: 10.1117/12.589738
Proc. SPIE 5683, SHRED: a CPU scheduler for heterogeneous applications, 0000 (8 March 2005); doi: 10.1117/12.592143
Proc. SPIE 5683, Pipelining and bypassing in a RISC/DSP processor, 0000 (8 March 2005); doi: 10.1117/12.583185
Multimedia Systems
Proc. SPIE 5683, Wi-fi walkman: a wireless handheld that shares and recommends music on peer-to-peer networks, 0000 (8 March 2005); doi: 10.1117/12.588509
Proc. SPIE 5683, A case study in clock synchronization for distributed camera systems, 0000 (8 March 2005); doi: 10.1117/12.589840
Proc. SPIE 5683, Wireless video transmission techniques on MPEG-4 streaming systems, 0000 (8 March 2005); doi: 10.1117/12.591404
Proc. SPIE 5683, PLASMA: a component-based framework for building self-adaptive multimedia applications, 0000 (8 March 2005); doi: 10.1117/12.592148
Multimedia Algorithms
Proc. SPIE 5683, A reduced complexity frequency domain acquisition of DS-SS signals for embedded applications, 0000 (8 March 2005); doi: 10.1117/12.584980
Proc. SPIE 5683, New algorithm for computation of DCT through pyramidal addition, 0000 (8 March 2005); doi: 10.1117/12.588161
Proc. SPIE 5683, Compression of CCD raw images for digital still cameras, 0000 (8 March 2005); doi: 10.1117/12.596869
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