PROCEEDINGS VOLUME 5756
MICROLITHOGRAPHY 2005 | 27 FEBRUARY - 4 MARCH 2005
Design and Process Integration for Microelectronic Manufacturing III
IN THIS VOLUME

0 Sessions, 43 Papers, 0 Presentations
DfM Overview  (3)
OPC and RET  (6)
MICROLITHOGRAPHY 2005
27 February - 4 March 2005
San Jose, California, United States
DfM Overview
Proc. SPIE 5756, Integrating DfM components into a cohesive design-to-silicon solution, 0000 (5 May 2005); doi: 10.1117/12.604723
Proc. SPIE 5756, Using yield-focused design methodologies to speed time-to-market, 0000 (5 May 2005); doi: 10.1117/12.601945
Proc. SPIE 5756, Design process optimization, virtual prototyping of manufacturing, and foundry-portable DFM, 0000 (5 May 2005); doi: 10.1117/12.603077
Design, Automation, and Characterization
Proc. SPIE 5756, Integrated circuit DFM framework for deep sub-wavelength processes, 0000 (5 May 2005); doi: 10.1117/12.599044
Proc. SPIE 5756, Process-window sensitive full-chip inspection for design-to-silicon optimization in the sub-wavelength era, 0000 (5 May 2005); doi: 10.1117/12.599865
Proc. SPIE 5756, Inspection of integrated circuit databases through reticle and wafer simulation: an integrated approach to design for manufacturing (DFM), 0000 (5 May 2005); doi: 10.1117/12.604698
Proc. SPIE 5756, Introduction of a die-to-database verification tool for the entire printed geometry of a die: geometry verification system NGR2100 for DFM, 0000 (5 May 2005); doi: 10.1117/12.599467
Design Optimization and RET
Proc. SPIE 5756, Investigation of model-based physical design restrictions, 0000 (5 May 2005); doi: 10.1117/12.601105
Proc. SPIE 5756, MAID: manufacturing aware IC design, 0000 (5 May 2005); doi: 10.1117/12.605371
Proc. SPIE 5756, Design of integrated-circuit interconnects with accurate modeling of chemical-mechanical planarization, 0000 (5 May 2005); doi: 10.1117/12.605222
Proc. SPIE 5756, Optical extensions integration for a 0.314-µm<sup>2</sup> 45-nm node 6-transistor SRAM cell, 0000 (5 May 2005); doi: 10.1117/12.600862
Proc. SPIE 5756, Manufacturing-aware design methodology for assist feature correctness, 0000 (5 May 2005); doi: 10.1117/12.604872
Proc. SPIE 5756, Integrating RET and mask manufacturability in memory designs for local interconnect for sub-100nm trenches, 0000 (5 May 2005); doi: 10.1117/12.602539
Analysis and Modeling
Proc. SPIE 5756, Geometrical analysis of product layout as a powerful tool for DFM, 0000 (5 May 2005); doi: 10.1117/12.595062
Proc. SPIE 5756, Toward through-process layout quality metrics, 0000 (5 May 2005); doi: 10.1117/12.601842
Proc. SPIE 5756, Correlation analysis of CD-variation and circuit performance under multiple sources of variability, 0000 (5 May 2005); doi: 10.1117/12.604606
Proc. SPIE 5756, Modeling within-field gate length spatial variation for process-design co-optimization, 0000 (5 May 2005); doi: 10.1117/12.600028
Proc. SPIE 5756, Advanced timing analysis based on post-OPC patterning process simulations, 0000 (5 May 2005); doi: 10.1117/12.604567
Proc. SPIE 5756, Model-based verification for first time right manufacturing, 0000 (5 May 2005); doi: 10.1117/12.600552
Design for Yield
Proc. SPIE 5756, Building an infrastructure for parametric yield analysis: concept and implementation of a DFM platform, 0000 (5 May 2005); doi: 10.1117/12.600261
Proc. SPIE 5756, Lithography simulation system for total CD control from design to manufacturing, 0000 (5 May 2005); doi: 10.1117/12.601132
Proc. SPIE 5756, Design and process limited yield at the 65-nm node and beyond, 0000 (5 May 2005); doi: 10.1117/12.605369
Proc. SPIE 5756, Assessing the impact of real world manufacturing lithography variations on post-OPC CD control, 0000 (5 May 2005); doi: 10.1117/12.598063
Proc. SPIE 5756, Detecting focus-sensitive configurations during OPC, 0000 (5 May 2005); doi: 10.1117/12.601062
OPC and RET
Proc. SPIE 5756, DFM in practice: results of a three way partnership between a leading fabless design house, foundry, and EDA company to implement alternating-phase shift mask (Alt-PSM) on a 90-nm FPGA chip, 0000 (5 May 2005); doi: 10.1117/12.598838
Proc. SPIE 5756, Design rule considerations for 65-nm node contact using off axis illumination, 0000 (5 May 2005); doi: 10.1117/12.600005
Proc. SPIE 5756, Lithography yield check for IC design, 0000 (5 May 2005); doi: 10.1117/12.600636
Proc. SPIE 5756, Improving model-based OPC performance for the 65-nm node through calibration set optimization, 0000 (5 May 2005); doi: 10.1117/12.601166
Proc. SPIE 5756, New OPC methods to increase process margin for sub-70nm devices, 0000 (5 May 2005); doi: 10.1117/12.600231
Proc. SPIE 5756, Mask cost analysis via write time estimation, 0000 (5 May 2005); doi: 10.1117/12.598884
Poster Session
Proc. SPIE 5756, Device and lithography contextual mask rule generation, 0000 (5 May 2005); doi: 10.1117/12.600730
Proc. SPIE 5756, Process centering OPC using design intent to improve yield, 0000 (5 May 2005); doi: 10.1117/12.600180
Proc. SPIE 5756, Evaluating design for manufacturing with process capability analysis, 0000 (5 May 2005); doi: 10.1117/12.599648
Proc. SPIE 5756, The prospects for hierarchical data processing with growing complexity of the post-tapeout flow, 0000 (5 May 2005); doi: 10.1117/12.600659
Proc. SPIE 5756, Exploiting hierarchical structure to enhance cell-based RET with localized OPC reconfiguration, 0000 (5 May 2005); doi: 10.1117/12.599830
Proc. SPIE 5756, Investigating a lithography strategy for diagonal routing architecture at sub-100nm technology nodes, 0000 (5 May 2005); doi: 10.1117/12.601421
Proc. SPIE 5756, 65nm OPC and design optimization by using simple electrical transistor simulation, 0000 (5 May 2005); doi: 10.1117/12.600887
Proc. SPIE 5756, Mask cost reduction and yield optimization using design intent, 0000 (5 May 2005); doi: 10.1117/12.600086
Proc. SPIE 5756, Full chip gate CD error prediction for model-based OPC, 0000 (5 May 2005); doi: 10.1117/12.599253
Proc. SPIE 5756, WAMA: a method of optimizing reticle/die placement to increase litho cell productivity, 0000 (5 May 2005); doi: 10.1117/12.584775
Proc. SPIE 5756, Line end design intent estimation using curves, 0000 (5 May 2005); doi: 10.1117/12.604526
Proc. SPIE 5756, A novel design-process optimization technique based on self-consistent electrical performance evaluation, 0000 (5 May 2005); doi: 10.1117/12.600283
Proc. SPIE 5756, Considerations for the use of defocus models for OPC, 0000 (5 May 2005); doi: 10.1117/12.598059
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