PROCEEDINGS VOLUME 6156
SPIE 31ST INTERNATIONAL SYMPOSIUM ON ADVANCED LITHOGRAPHY | 19-24 FEBRUARY 2006
Design and Process Integration for Microelectronic Manufacturing IV
IN THIS VOLUME

0 Sessions, 52 Papers, 0 Presentations
RET and OPC  (17)
Proceedings Volume 6156 is from: Logo
SPIE 31ST INTERNATIONAL SYMPOSIUM ON ADVANCED LITHOGRAPHY
19-24 February 2006
San Jose, California, United States
Design-Manufacturing Interface
Proc. SPIE 6156, Layout rule trends and effect upon CPU design, 615602 (10 March 2006); doi: 10.1117/12.664598
Proc. SPIE 6156, Through-process modeling in a DfM environment, 615603 (14 March 2006); doi: 10.1117/12.658049
Proc. SPIE 6156, A genuine design manufacturability check for designers, 615604 (24 March 2006); doi: 10.1117/12.657011
Proc. SPIE 6156, Annotated layout optimization, 615605 (13 March 2006); doi: 10.1117/12.656428
Proc. SPIE 6156, Silicon IP reuse standards for design for manufacturability, 615606 (14 March 2006); doi: 10.1117/12.659829
Proc. SPIE 6156, Call for an industry standard for pattern transfer models for usage in OPC and design for manufacturability, 615607 (14 March 2006); doi: 10.1117/12.652682
Layout Design for Manufacturability
Proc. SPIE 6156, A heuristic method for statistical digital circuit sizing, 615608 (13 March 2006); doi: 10.1117/12.657499
Proc. SPIE 6156, Maximization of layout printability/manufacturability by extreme layout regularity, 615609 (24 March 2006); doi: 10.1117/12.659984
Proc. SPIE 6156, Layout verification and optimization based on flexible design rules, 61560A (24 March 2006); doi: 10.1117/12.658982
Proc. SPIE 6156, Self-compensating design for reduction of timing and leakage sensitivity to systematic pattern dependent variation, 61560B (14 March 2006); doi: 10.1117/12.659577
Proc. SPIE 6156, DFM: a practical layout optimization procedure for the improved process window for an existing 90-nm product, 61560C (14 March 2006); doi: 10.1117/12.656085
Proc. SPIE 6156, CD analysis of advanced photolithography and its impact on critical design structures, 61560D (13 March 2006); doi: 10.1117/12.657131
Proc. SPIE 6156, Platform for collaborative DFM, 61560E (13 March 2006); doi: 10.1117/12.657042
Proc. SPIE 6156, Lithography oriented DfM for 65 nm and beyond, 61560F (24 March 2006); doi: 10.1117/12.656858
Proc. SPIE 6156, Design-friendly DFM rule, 61560G (13 March 2006); doi: 10.1117/12.656271
Proc. SPIE 6156, Development of hot spot fixer (HSF), 61560H (24 March 2006); doi: 10.1117/12.657806
Proc. SPIE 6156, Across field CD control improvement for critical level imaging: new applications for layout correction and optimization, 61560I (14 March 2006); doi: 10.1117/12.657268
Proc. SPIE 6156, The use of process models to enhance device performance through semiconductor design, 61560J (14 March 2006); doi: 10.1117/12.656964
Analysis Techniques
Proc. SPIE 6156, Reducing DfM to practice: the lithography manufacturability assessor, 61560K (13 March 2006); doi: 10.1117/12.657139
Proc. SPIE 6156, Toward DFM: process worthy design and OPC through verification method using MEEF, TF-MEEF, and MTT, 61560L (14 March 2006); doi: 10.1117/12.655482
Proc. SPIE 6156, Meeting critical gate linewidth control needs at the 65 nm node, 61560M (14 March 2006); doi: 10.1117/12.659427
Proc. SPIE 6156, Hot spot management in ultra-low k<sub>1</sub> lithography, 61560N (13 March 2006); doi: 10.1117/12.656418
Proc. SPIE 6156, Experimental verification of improved printability for litho-driven designs, 61560O (14 March 2006); doi: 10.1117/12.656359
Proc. SPIE 6156, From poly line to transistor: building BSIM models for non-rectangular transistors, 61560P (13 March 2006); doi: 10.1117/12.657051
Proc. SPIE 6156, Impact of process variation on 65nm across-chip linewidth variation, 61560Q (14 March 2006); doi: 10.1117/12.660541
Proc. SPIE 6156, Reticle enhancement verification for the 65nm and 45nm nodes, 61560R (14 March 2006); doi: 10.1117/12.658823
Proc. SPIE 6156, Modeling edge placement error distribution in standard cell library, 61560S (14 March 2006); doi: 10.1117/12.658580
Proc. SPIE 6156, Lithography simulation-based full-chip design analyses, 61560T (14 March 2006); doi: 10.1117/12.658129
Proc. SPIE 6156, Modeling of non-uniform device geometries for post-lithography circuit analysis, 61560U (14 March 2006); doi: 10.1117/12.658087
Proc. SPIE 6156, Full-chip lithography manufacturability check for yield improvement, 61560W (14 March 2006); doi: 10.1117/12.656401
Proc. SPIE 6156, Lithography window check before mask tape-out in sub-0.18um technology, 61560X (14 March 2006); doi: 10.1117/12.655851
DFM Roadmap and Future Technologies
Proc. SPIE 6156, DFM requirements and solution roadmaps: the multilayer approach, 61560Y (13 March 2006); doi: 10.1117/12.659302
Proc. SPIE 6156, The nanotech impact on IC processing: near and long term, 615610 (13 March 2006); doi: 10.1117/12.659558
Proc. SPIE 6156, Diblock copolymer directed self-assembly for CMOS device fabrication, 615611 (14 March 2006); doi: 10.1117/12.661028
Proc. SPIE 6156, A high aspect ratio Si-fin FinFET fabricated with 193nm scanner photolithography and thermal oxide hard mask etching techniques, 615612 (14 March 2006); doi: 10.1117/12.659648
RET and OPC
Proc. SPIE 6156, Sequential PPC and process-window-aware mask layout synthesis, 615613 (13 March 2006); doi: 10.1117/12.656667
Proc. SPIE 6156, Accurate OPC model generation through use of a streamlined data flow incorporating automated test-structure layout and CD-SEM recipe generation, 615614 (14 March 2006); doi: 10.1117/12.660600
Proc. SPIE 6156, Implementation of adaptive site optimization in model-based OPC for minimizing ripples, 615615 (17 March 2006); doi: 10.1117/12.660180
Proc. SPIE 6156, Improving asymmetric printing and low margin using custom illumination for contact hole lithography, 615616 (17 March 2006); doi: 10.1117/12.660120
Proc. SPIE 6156, Challenges and solutions for trench lithography beyond 65nm node, 615617 (14 March 2006); doi: 10.1117/12.659242
Proc. SPIE 6156, Fast lithography simulation under focus variations for OPC and layout optimizations, 615618 (14 March 2006); doi: 10.1117/12.658110
Proc. SPIE 6156, The influence of calibration pattern coverage for lumped parameter resist models on OPC convergence, 615619 (16 March 2006); doi: 10.1117/12.657536
Proc. SPIE 6156, Highly accurate hybrid-OPC method for sub-60nm memory device, 61561A (14 March 2006); doi: 10.1117/12.656853
Proc. SPIE 6156, Using design intent to qualify and control lithography manufacturing, 61561B (14 March 2006); doi: 10.1117/12.656856
Proc. SPIE 6156, Simple method to verify OPC data based on exposure condition, 61561C (14 March 2006); doi: 10.1117/12.656888
Proc. SPIE 6156, Considerations of model-based OPC verification for sub-70nm memory device, 61561D (14 March 2006); doi: 10.1117/12.656852
Proc. SPIE 6156, RET for the wiring layer of a 3D memory, 61561E (14 March 2006); doi: 10.1117/12.656725
Proc. SPIE 6156, The use of optical proximity correction to compensate for reflectivity differences in N type and P type poly-silicon, 61561F (14 March 2006); doi: 10.1117/12.656732
Proc. SPIE 6156, Optimal segmentation of polygon edges, 61561G (14 March 2006); doi: 10.1117/12.656695
Proc. SPIE 6156, Improving model-based OPC performance for sub-60nm devices using real source optical model, 61561H (24 March 2006); doi: 10.1117/12.655954
Proc. SPIE 6156, OPC to improve lithographic process window, 61561I (14 March 2006); doi: 10.1117/12.655237
Proc. SPIE 6156, Patterning with spacer for expanding the resolution limit of current lithography tool, 61561J (13 March 2006); doi: 10.1117/12.650991
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