PROCEEDINGS VOLUME 6521
SPIE ADVANCED LITHOGRAPHY | 25 FEBRUARY - 2 MARCH 2007
Design for Manufacturability through Design-Process Integration
Proceedings Volume 6521 is from: Logo
SPIE ADVANCED LITHOGRAPHY
25 February - 2 March 2007
San Jose, California, United States
Front Matter
Proc. SPIE 6521, Front Matter: Volume 6521, 652101 (30 March 2007); doi: 10.1117/12.736571
Computational Lithography (Joint Session with 6520)
Proc. SPIE 6521, Model-based assist feature generation, 652102 (20 March 2007); doi: 10.1117/12.711504
Proc. SPIE 6521, Three-dimensional mask effect approximate modeling for sub-50-nm node device OPC, 652103 (21 March 2007); doi: 10.1117/12.711946
Keynote Presentation
Proc. SPIE 6521, Collaborative platform, tool-kit, and physical models for DfM, 652104 (28 March 2007); doi: 10.1117/12.721199
Layout Verification
Proc. SPIE 6521, Lithography simulation in DfM: achievable accuracy versus requirements, 652106 (21 March 2007); doi: 10.1117/12.712437
Proc. SPIE 6521, Structural failure prediction using simplified lithography simulation models, 652107 (21 March 2007); doi: 10.1117/12.712054
Proc. SPIE 6521, Unified process-aware system for circuit layout verification, 652108 (21 March 2007); doi: 10.1117/12.711619
Proc. SPIE 6521, Double patterning design split implementation and validation for the 32nm node, 652109 (21 March 2007); doi: 10.1117/12.712139
Proc. SPIE 6521, DRC Plus: augmenting standard DRC with pattern matching on 2D geometries, 65210A (28 March 2007); doi: 10.1117/12.716600
Layout Optimization
Proc. SPIE 6521, Process window aware layout optimization using hot spot fixing system, 65210B (21 March 2007); doi: 10.1117/12.710299
Proc. SPIE 6521, Automated full-chip hotspot detection and removal flow for interconnect layers of cell-based designs, 65210C (21 March 2007); doi: 10.1117/12.712491
Proc. SPIE 6521, Model-assisted routing for improved lithography robustness, 65210D (21 March 2007); doi: 10.1117/12.717055
Proc. SPIE 6521, Model-based approach for design verification and co-optimization of catastrophic and parametric-related defects due to systematic manufacturing variations, 65210E (21 March 2007); doi: 10.1117/12.712471
Process-Aware Timing and Power Analysis
Proc. SPIE 6521, Context-specific leakage and delay analysis of a 65nm standard cell library for lithography-induced variability, 65210F (21 March 2007); doi: 10.1117/12.712281
Proc. SPIE 6521, Patterning effect and correlated electrical model of post-OPC MOSFET devices, 65210G (21 March 2007); doi: 10.1117/12.717254
Proc. SPIE 6521, Coupling-aware mixed dummy metal insertion for lithography, 65210H (21 March 2007); doi: 10.1117/12.711644
Proc. SPIE 6521, Prediction of interconnect delay variations using pattern matching, 65210I (21 March 2007); doi: 10.1117/12.712257
Proc. SPIE 6521, OPC to reduce variability of transistor properties, 65210J (21 March 2007); doi: 10.1117/12.711812
DFM Efficiency
Proc. SPIE 6521, Improving the power-performance of multicore processors through optimization of lithography and thermal processing, 65210K (21 March 2007); doi: 10.1117/12.711750
Proc. SPIE 6521, Cost-performance tradeoff between design and manufacturing: DfM or MfD?, 65210L (21 March 2007); doi: 10.1117/12.711709
Proc. SPIE 6521, Hardware verification of litho-friendly design (LfD) methodologies, 65210M (21 March 2007); doi: 10.1117/12.713995
Proc. SPIE 6521, Lithography and yield sensitivity analysis of SRAM scaling for the 32nm node, 65210N (21 March 2007); doi: 10.1117/12.713385
Poster Session
Proc. SPIE 6521, Litho aware method for circuit timing/power analysis through process, 65210O (21 March 2007); doi: 10.1117/12.711723
Proc. SPIE 6521, Circuit size optimization with multiple sources of variation and position dependant correlation, 65210P (21 March 2007); doi: 10.1117/12.711794
Proc. SPIE 6521, Multidimensional physical design optimization for systematic and parametric yield loss reduction, 65210Q (21 March 2007); doi: 10.1117/12.711774
Proc. SPIE 6521, Highly accurate model-based verification using SEM image calibration method, 65210R (21 March 2007); doi: 10.1117/12.712037
Proc. SPIE 6521, The study for increasing efficiency of OPC verification by reducing false errors from bending pattern by using different size of CD error non-checking area with various corner lengths, 65210S (21 March 2007); doi: 10.1117/12.711959
Proc. SPIE 6521, DFM flow by using combination between design-based metrology system and model-based verification at sub-50nm memory device, 65210T (21 March 2007); doi: 10.1117/12.711953
Proc. SPIE 6521, Application of enhanced dynamic fragmentation to minimize false error from post OPC verification, 65210U (21 March 2007); doi: 10.1117/12.711950
Proc. SPIE 6521, Pattern decomposition for double patterning from photomask viewpoint, 65210V (21 March 2007); doi: 10.1117/12.711915
Proc. SPIE 6521, Impacts of optical proximity correction settings on electrical performances, 65210W (21 March 2007); doi: 10.1117/12.711850
Proc. SPIE 6521, Lithography enhanced manufacturability analysis by using multilevel simulated contours, 65210Y (21 March 2007); doi: 10.1117/12.711825
Proc. SPIE 6521, Scanner-characteristics-aware OPC modeling and correction, 65210Z (21 March 2007); doi: 10.1117/12.711624
Proc. SPIE 6521, Wire sizing and spacing for lithographic printability optimization, 652111 (21 March 2007); doi: 10.1117/12.708974
Proc. SPIE 6521, A rigorous method to determine printability of a target layout, 652112 (21 March 2007); doi: 10.1117/12.711530
Proc. SPIE 6521, Double patterning technology: process-window analysis in a many-dimensional space, 652113 (21 March 2007); doi: 10.1117/12.711515
Proc. SPIE 6521, Novel technique to separate systematic and random defects during 65nm and 45nm process development, 652114 (21 March 2007); doi: 10.1117/12.711512
Proc. SPIE 6521, Intelligent fill pattern and extraction methodology for sensitive RF/analog or SoC products, 652115 (21 March 2007); doi: 10.1117/12.711460
Proc. SPIE 6521, Scanner parameter sensitivity analysis for OPE, 652116 (21 March 2007); doi: 10.1117/12.711356
Proc. SPIE 6521, OPC and design verification for DFM using die-to-database inspection, 652117 (21 March 2007); doi: 10.1117/12.711348
Proc. SPIE 6521, Self-assembled dummy patterns for lithography process margin enhancement, 652118 (21 March 2007); doi: 10.1117/12.711253
Proc. SPIE 6521, Modeling spatial gate length variation in the 0.2µm to 1.15mm separation range, 652119 (21 March 2007); doi: 10.1117/12.710668
Proc. SPIE 6521, Novel method for quality assurance of two-dimensional pattern fidelity, 65211B (21 March 2007); doi: 10.1117/12.713604
Proc. SPIE 6521, A systematic approach for capturing interconnects hot spots, 65211C (21 March 2007); doi: 10.1117/12.713521
Proc. SPIE 6521, Ensuring production-worthy OPC recipes using large test structure arrays, 65211D (21 March 2007); doi: 10.1117/12.713411
Proc. SPIE 6521, Intelligent visualization of lithography violations, 65211E (21 March 2007); doi: 10.1117/12.714515
Proc. SPIE 6521, Production-worthy OPC verification methods for protecting against process variability, 65211F (21 March 2007); doi: 10.1117/12.714088
Proc. SPIE 6521, Automatic OPC mask shape repair, 65211G (21 March 2007); doi: 10.1117/12.714014
Proc. SPIE 6521, SOFT: smooth OPC fixing technique for ECO process, 65211H (21 March 2007); doi: 10.1117/12.712878
Proc. SPIE 6521, The accuracy of a calibrated PROLITH physical resist model across illumination conditions, 65211I (21 March 2007); doi: 10.1117/12.712862
Proc. SPIE 6521, Feedback flow to improve model-based OPC calibration test patterns, 65211J (28 March 2007); doi: 10.1117/12.712843
Proc. SPIE 6521, Double pattern EDA solutions for 32nm HP and beyond, 65211K (21 March 2007); doi: 10.1117/12.712773
Proc. SPIE 6521, Optimizing gate layer OPC correction and SRAF placement for maximum design manufacturability, 65211L (21 March 2007); doi: 10.1117/12.712748
Proc. SPIE 6521, Assist features for modeling three-dimensional mask effects in optical proximity correction, 65211M (21 March 2007); doi: 10.1117/12.712513
Proc. SPIE 6521, Circuit-based SEM contour OPC model calibration, 65211N (28 March 2007); doi: 10.1117/12.713044
Proc. SPIE 6521, Boundary-based cellwise OPC for standard-cell layouts, 65211O (21 March 2007); doi: 10.1117/12.712185