PROCEEDINGS VOLUME 6590
MICROTECHNOLOGIES FOR THE NEW MILLENNIUM | 2-4 MAY 2007
VLSI Circuits and Systems III
Proceedings Volume 6590 is from: Logo
MICROTECHNOLOGIES FOR THE NEW MILLENNIUM
2-4 May 2007
Maspalomas, Gran Canaria, Spain
Front Matter: Volume 6590
Proc. SPIE 6590, Front Matter: Volume 6590, 659001 (31 May 2007); doi: 10.1117/12.747410
Digital Design Methodologies and Tools
Proc. SPIE 6590, High-level power estimation for digital system, 659002 (10 May 2007); doi: 10.1117/12.721182
Proc. SPIE 6590, Crosscoupling power optimal wire spacing in quasilinear runtime, 659003 (10 May 2007); doi: 10.1117/12.724139
Proc. SPIE 6590, Partitioning and characterization of high speed adder structures in deep-submicron technologies, 659004 (10 May 2007); doi: 10.1117/12.721996
Proc. SPIE 6590, Power-driven FPGA to ASIC conversion, 659005 (10 May 2007); doi: 10.1117/12.722901
Proc. SPIE 6590, Automatic logic synthesis for parallel alternating latches clocking schemes, 659006 (10 May 2007); doi: 10.1117/12.723664
Proc. SPIE 6590, Effects of buffer insertion on the average/peak power ratio in CMOS VLSI digital circuits, 659007 (23 May 2007); doi: 10.1117/12.724162
Proc. SPIE 6590, HEAPAN: a high-level computer architecture analysis tool, 659008 (23 May 2007); doi: 10.1117/12.721972
Multimedia I
Proc. SPIE 6590, MPEG-4 ASP SoC receiver with novel image enhancement techniques for DAB networks, 659009 (10 May 2007); doi: 10.1117/12.723740
Proc. SPIE 6590, Toward the implementation of a baseline H.264/AVC decoder onto a reconfigurable architecture, 65900A (10 May 2007); doi: 10.1117/12.722042
Proc. SPIE 6590, Accelerating a MPEG-4 video decoder through custom software/hardware co-design, 65900B (10 May 2007); doi: 10.1117/12.722068
Proc. SPIE 6590, Optimizing coarse-grain reconfigurable hardware utilization through multiprocessing: an H.264/AVC decoder example, 65900C (10 May 2007); doi: 10.1117/12.722077
Analog Circuits I
Proc. SPIE 6590, Low-voltage low-power reference circuits for an autonomous robot: I-SWARM, 65900D (10 May 2007); doi: 10.1117/12.721287
Proc. SPIE 6590, Low-voltage CMOS variable preamplifier for fiber-based gigabit ethernet, 65900E (10 May 2007); doi: 10.1117/12.721381
Proc. SPIE 6590, Design of clock recovery circuits for optical clocking in DSM CMOS, 65900F (10 May 2007); doi: 10.1117/12.721646
Proc. SPIE 6590, A study of mismatch in adaptive programmable CMOS sensor compensation circuits, 65900G (23 May 2007); doi: 10.1117/12.721959
Proc. SPIE 6590, Ultra low power switched current finite impulse response filter banks realized in CMOS 0.18 um technology, 65900H (10 May 2007); doi: 10.1117/12.721162
Proc. SPIE 6590, IP-based design reuse for analog systems, 65900I (10 May 2007); doi: 10.1117/12.721882
Proc. SPIE 6590, A fully integrated folded mixer in CMOS 0.35 µm technology for 802.11a WIFI applications, 65900J (23 May 2007); doi: 10.1117/12.721971
Proc. SPIE 6590, Flexible and low power binary-tree current mode min/max nonlinear filters realized in CMOS technology, 65900L (10 May 2007); doi: 10.1117/12.721192
FPGAs
Proc. SPIE 6590, Architectural design for a low cost FPGA-based traffic signal detection system in vehicles, 65900M (10 May 2007); doi: 10.1117/12.721694
Proc. SPIE 6590, Hand veins feature extraction using DT-CNNS, 65900N (10 May 2007); doi: 10.1117/12.722920
Proc. SPIE 6590, Real-time lane detector hardware system, 65900O (10 May 2007); doi: 10.1117/12.723615
Proc. SPIE 6590, FPGA realization of a split radix FFT processor, 65900P (10 May 2007); doi: 10.1117/12.721975
CAD
Proc. SPIE 6590, Exploring system interconnection architectures with VIPACES: from direct connections to NoCs, 65900Q (10 May 2007); doi: 10.1117/12.722054
Proc. SPIE 6590, Automatic synthesis of zero-aliasing space compactors with application to testing of embedded IP cores, 65900R (10 May 2007); doi: 10.1117/12.722047
Analog and Mixed Signal Design Methodologies and Tools
Proc. SPIE 6590, Design automation techniques for high-resolution current folding and interpolating CMOS A/D converters, 65900S (10 May 2007); doi: 10.1117/12.721826
Proc. SPIE 6590, Toward systematic design of multi-standard converters, 65900T (23 May 2007); doi: 10.1117/12.721877
Proc. SPIE 6590, A methodology for switching noise estimation at gate level, 65900U (23 May 2007); doi: 10.1117/12.724164
Proc. SPIE 6590, Synchronous and asynchronous multiplexer circuits for medical imaging realized in CMOS 0.18um technology, 65900V (10 May 2007); doi: 10.1117/12.721239
Proc. SPIE 6590, Resizing methodology for CMOS analog circuits, 65900W (10 May 2007); doi: 10.1117/12.721871
Multimedia II
Proc. SPIE 6590, Low-cost VLSI architecture design for forward quantization of H.264/AVC, 65900Y (10 May 2007); doi: 10.1117/12.721493
Proc. SPIE 6590, Multiformat decoder for a DSP-based IP set-top box, 65900Z (10 May 2007); doi: 10.1117/12.722287
Proc. SPIE 6590, High parallel-pipeline integer-pel and fractional-pel motion estimation VLSI architectures for H.264/AVC, 659010 (10 May 2007); doi: 10.1117/12.724042
Proc. SPIE 6590, H.264 video stream statistical analysis for post-compression improvements, 659011 (10 May 2007); doi: 10.1117/12.724165
Data Communication
Proc. SPIE 6590, Variable length packet scheduler algorithm with QoS support, 659012 (10 May 2007); doi: 10.1117/12.721947
Proc. SPIE 6590, Integrated hardware interfaces for modular sensor networks, 659014 (10 May 2007); doi: 10.1117/12.723773
Analog Circuits II
Proc. SPIE 6590, Design of a 0.13-um CMOS cascade expandable ΣΔ modulator for multi-standard RF telecom systems, 659015 (23 May 2007); doi: 10.1117/12.721341
Proc. SPIE 6590, A design tool for high-resolution high-frequency cascade continuous-time ΣΔ modulators, 659016 (23 May 2007); doi: 10.1117/12.721896
Proc. SPIE 6590, A highly linear fast-settling envelope detector, 659017 (10 May 2007); doi: 10.1117/12.724037
Circuit Design for RF Applications
Proc. SPIE 6590, Behavioral modeling and simulation of multi-standard RF receivers using MATLAB/SIMULINK, 659018 (23 May 2007); doi: 10.1117/12.721339
Proc. SPIE 6590, Low power considerations and design for CMOS VCOs applied for direct conversion receivers at 5GHz, 659019 (10 May 2007); doi: 10.1117/12.721661
Proc. SPIE 6590, Test measures evaluation for VCO and charge pump blocks in RF PLLs, 65901A (10 May 2007); doi: 10.1117/12.721819
Proc. SPIE 6590, A low-voltage fully balanced CMFF transconductor with improved linearity, 65901B (10 May 2007); doi: 10.1117/12.722000
Proc. SPIE 6590, A study of stacked and miniature 3-D inductor performance for radio frequency integrated circuit design, 65901C (10 May 2007); doi: 10.1117/12.721913
Proc. SPIE 6590, A fully integrated VCO with a wide tuning range for DVB-H, 65901D (10 May 2007); doi: 10.1117/12.721953
Proc. SPIE 6590, Influence of the diffusion geometry on PN integrated varactors, 65901E (10 May 2007); doi: 10.1117/12.721999
Proc. SPIE 6590, A 3-10 GHz ultra-wideband SiGe LNA with wideband LC matching network, 65901F (23 May 2007); doi: 10.1117/12.723575
High Level Modelling and VLSI Arithmetic
Proc. SPIE 6590, Powerline LonTalk protocol performance analysis in SystemC, 65901G (10 May 2007); doi: 10.1117/12.721799
Proc. SPIE 6590, Mixed signal SystemC modelling of a SoC architecture with Dynamic Voltage Scaling, 65901H (10 May 2007); doi: 10.1117/12.722072
Proc. SPIE 6590, Efficient hardware implementation of 3X for radix-8 encoding, 65901I (10 May 2007); doi: 10.1117/12.721489
Systems and Network on a Chip
Proc. SPIE 6590, Dynamic power management of a system on chip based on AMBA AHB bus, 65901K (10 May 2007); doi: 10.1117/12.721892
Proc. SPIE 6590, Implementation of a parametrizable router architecture for networks-on-chip (NoC) with quality of service (QoS) support, 65901L (10 May 2007); doi: 10.1117/12.721922
Proc. SPIE 6590, A SoC for studying multi-agent software/algorithms on a real swarm of mm3-sized microrobots, 65901M (10 May 2007); doi: 10.1117/12.722037
Proc. SPIE 6590, New FPSoC-based architecture for efficient FSBM motion estimation processing in video standards, 65901N (10 May 2007); doi: 10.1117/12.724094
Technology
Proc. SPIE 6590, The electrical origin of the 1/f electrical noise in solid-state devices and integrated circuits, 65901O (10 May 2007); doi: 10.1117/12.721175
Proc. SPIE 6590, A stochastic model of digital switching noise, 65901P (10 May 2007); doi: 10.1117/12.722082