PROCEEDINGS VOLUME 6925
SPIE ADVANCED LITHOGRAPHY | 24-29 FEBRUARY 2008
Design for Manufacturability through Design-Process Integration II
Proceedings Volume 6925 is from: Logo
SPIE ADVANCED LITHOGRAPHY
24-29 February 2008
San Jose, California, United States
Front Matter
Proc. SPIE 6925, Front Matter: 6925, 692501 (17 April 2008); doi: 10.1117/12.797490
Keynote Session
Proc. SPIE 6925, DfM, the teenage years, 692502 (19 March 2008); doi: 10.1117/12.782650
Proc. SPIE 6925, Intel design for manufacturing and evolution of design rules, 692503 (20 March 2008); doi: 10.1117/12.772052
Layout Verification, Hotspots, Variations
Proc. SPIE 6925, Automatic hotspot classification using pattern-based clustering, 692505 (4 March 2008); doi: 10.1117/12.772867
Proc. SPIE 6925, Effective learning and feedback to designers through design and wafer inspection integration, 692506 (4 March 2008); doi: 10.1117/12.772242
Proc. SPIE 6925, Rigorous CMP and electroplating simulations for DFM applications, 692507 (12 March 2008); doi: 10.1117/12.771702
Proc. SPIE 6925, Global and local factors of on-chip variation of gate length, 692508 (4 March 2008); doi: 10.1117/12.772568
Proc. SPIE 6925, Layout verification in the era of process uncertainty: target process variability bands vs actual process variability bands, 692509 (4 March 2008); doi: 10.1117/12.769287
Proc. SPIE 6925, Context analysis and validation of lithography induced systematic variations in 65nm designs, 69250A (19 March 2008); doi: 10.1117/12.778836
Design Rules for Manufacturability
Proc. SPIE 6925, Low-k1 logic design using gridded design rules, 69250B (12 March 2008); doi: 10.1117/12.772875
Proc. SPIE 6925, DfM lessons learned from altPSM design, 69250C (4 March 2008); doi: 10.1117/12.771974
Proc. SPIE 6925, Yield aware design of gate layer for 45 nm CMOS-ASIC using a high-NA dry KrF systems, 69250D (19 March 2008); doi: 10.1117/12.771998
Proc. SPIE 6925, Inverse lithography as a DFM tool: accelerating design rule development with model-based assist feature placement, fast optical proximity correction and lithographic hotspot detection, 69250E (17 March 2008); doi: 10.1117/12.774581
Layout Optimization
Proc. SPIE 6925, Layout optimization based on a generalized process variability model, 69250F (4 March 2008); doi: 10.1117/12.772882
Proc. SPIE 6925, Manufacturing for design: a novel interconnect optimization method, 69250G (4 March 2008); doi: 10.1117/12.772341
Proc. SPIE 6925, Shaping gate channels for improved devices, 69250I (1 April 2008); doi: 10.1117/12.772889
Proc. SPIE 6925, A routing clean-up methodology for improvement of defect and lithography related yield, 69250J (4 March 2008); doi: 10.1117/12.770292
DFM Strategies in Design
Proc. SPIE 6925, Analysis of systematic variation and impact on circuit performance, 69250K (19 March 2008); doi: 10.1117/12.772075
Proc. SPIE 6925, VARAN: variability analysis for memory cell robustness, 69250L (4 March 2008); doi: 10.1117/12.777269
Proc. SPIE 6925, Implementation of silicon-validated variability analysis and optimization for standard cell libraries, 69250M (19 March 2008); doi: 10.1117/12.772897
Proc. SPIE 6925, Microprocessor chip timing analysis using extraction of simulated silicon-calibrated contours, 69250O (4 March 2008); doi: 10.1117/12.773013
DFM and Yield
Proc. SPIE 6925, Hypersensitive parameter-identifying ring oscillators for lithography process monitoring, 69250P (18 March 2008); doi: 10.1117/12.773184
Proc. SPIE 6925, Systematic yield estimation method applying lithography simulation, 69250Q (17 March 2008); doi: 10.1117/12.772747
Proc. SPIE 6925, Litho variations and their impact on the electrical yield of a 32nm node 6T SRAM cell, 69250R (12 March 2008); doi: 10.1117/12.773333
Proc. SPIE 6925, Predicting yield using model based OPC verification: calibrated with electrical test data, 69250S (4 March 2008); doi: 10.1117/12.773591
Poster Session
Proc. SPIE 6925, Exposure tool specific post-OPC verification, 69250T (4 March 2008); doi: 10.1117/12.773340
Proc. SPIE 6925, A procedure to back-annotate process induced layout dimension changes into the post layout simulation netlist, 69250V (4 March 2008); doi: 10.1117/12.771427
Proc. SPIE 6925, Predicting conversion time of circuit design file by artificial neural networks, 69250W (4 March 2008); doi: 10.1117/12.771771
Proc. SPIE 6925, System to improve RET-OPC production by dynamic design coverage using sign-off litho simulator, 69250X (4 March 2008); doi: 10.1117/12.771821
Proc. SPIE 6925, An extraction of repeating patterns from OPCed layout data, 69250Y (12 March 2008); doi: 10.1117/12.771836
Proc. SPIE 6925, Accurate model base verification scheme to eliminate hotspots and manage warmspots, 69250Z (18 March 2008); doi: 10.1117/12.771856
Proc. SPIE 6925, ACLV- and process-window-aware extraction of transistor parameters using litho-friendly design (LfD) methodologies, 692510 (4 March 2008); doi: 10.1117/12.771885
Proc. SPIE 6925, Device performance-based OPC for optimal circuit performance and mask cost reduction, 692511 (4 March 2008); doi: 10.1117/12.772285
Proc. SPIE 6925, Concurrent development methodology from design rule to OPC in 45-nm node logic device, 692512 (17 March 2008); doi: 10.1117/12.772382
Proc. SPIE 6925, Improvement on OPC completeness through pre-OPC hot spot detection and fix, 692513 (1 April 2008); doi: 10.1117/12.772409
Proc. SPIE 6925, DFM application on dual tone sub 50nm device, 692514 (19 March 2008); doi: 10.1117/12.772430
Proc. SPIE 6925, SEM contour-based model OPC calibrated with optically sensitive patterns, 692516 (4 March 2008); doi: 10.1117/12.772485
Proc. SPIE 6925, Hot spot management with die-to-database wafer inspection system, 692517 (19 March 2008); doi: 10.1117/12.772563
Proc. SPIE 6925, 32nm design rule evaluation through virtual patterning, 692518 (17 March 2008); doi: 10.1117/12.772685
Proc. SPIE 6925, A new robust process window qualification (PWQ) technique to perform systematic defect characterization to enlarge the lithographic process window using a die-to-database verification tool (NGR2100), 692519 (1 April 2008); doi: 10.1117/12.772706
Proc. SPIE 6925, Continuous process window modeling for process variation aware OPC and lithography verification, 69251A (19 March 2008); doi: 10.1117/12.772737
Proc. SPIE 6925, Using composite gratings for optical system characterization through scatterometry, 69251B (4 March 2008); doi: 10.1117/12.772785
Proc. SPIE 6925, Rules based process window OPC, 69251C (4 March 2008); doi: 10.1117/12.772790
Proc. SPIE 6925, RET selection using rigorous, physics-based computational lithography, 69251D (4 March 2008); doi: 10.1117/12.772872
Proc. SPIE 6925, APF pitch-halving for 22nm logic cells using gridded design rules, 69251E (4 March 2008); doi: 10.1117/12.772905
Proc. SPIE 6925, Site portability and extrapolative accuracy of a predictive resist model, 69251F (4 March 2008); doi: 10.1117/12.772984
Proc. SPIE 6925, A comprehensive model of process variability for statistical timing optimization, 69251G (4 March 2008); doi: 10.1117/12.772980
Proc. SPIE 6925, Application of layout DOE in RET flow, 69251H (4 March 2008); doi: 10.1117/12.773059
Proc. SPIE 6925, Impact of gate line edge roughness on double-gate FinFET performance variability, 69251I (19 March 2008); doi: 10.1117/12.773065
Proc. SPIE 6925, Validation and application of a mask model for inverse lithography, 69251J (19 March 2008); doi: 10.1117/12.773081
Proc. SPIE 6925, Cell-based OPC with standard-cell fill insertion, 69251L (4 March 2008); doi: 10.1117/12.773192
Proc. SPIE 6925, Process variation in metal-oxide-metal (MOM) capacitors, 69251M (18 March 2008); doi: 10.1117/12.773197
Proc. SPIE 6925, Decomposition difficulty analysis for double patterning and the impact on photomask manufacturability, 69251O (19 March 2008); doi: 10.1117/12.773291
Proc. SPIE 6925, A method of obtaining optical lithography friendly layout using a model for first level defects, 69251P (4 March 2008); doi: 10.1117/12.774098
Proc. SPIE 6925, Checking design conformance and optimizing manufacturability using automated double patterning decomposition, 69251Q (12 March 2008); doi: 10.1117/12.774647
Proc. SPIE 6925, Layout patterning check for DFM, 69251R (19 March 2008); doi: 10.1117/12.775420
Proc. SPIE 6925, Design based binning for litho qualification and process window qualification, 69251S (4 March 2008); doi: 10.1117/12.775713