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Layout verification in the era of process uncertainty: target process variability bands vs actual process variability bands
Inverse lithography as a DFM tool: accelerating design rule development with model-based assist feature placement, fast optical proximity correction and lithographic hotspot detection
Implementation of silicon-validated variability analysis and optimization for standard cell libraries
A procedure to back-annotate process induced layout dimension changes into the post layout simulation netlist
ACLV- and process-window-aware extraction of transistor parameters using litho-friendly design (LfD) methodologies
A new robust process window qualification (PWQ) technique to perform systematic defect characterization to enlarge the lithographic process window using a die-to-database verification tool (NGR2100)
Decomposition difficulty analysis for double patterning and the impact on photomask manufacturability