PROCEEDINGS VOLUME 7275
SPIE ADVANCED LITHOGRAPHY | 22-27 FEBRUARY 2009
Design for Manufacturability through Design-Process Integration III
IN THIS VOLUME

0 Sessions, 56 Papers, 0 Presentations
Front Matter  (1)
Variability  (4)
Proceedings Volume 7275 is from: Logo
SPIE ADVANCED LITHOGRAPHY
22-27 February 2009
San Jose, California, United States
Front Matter
Proc. SPIE 7275, Front Matter: Volume 7275, 727501 (1 April 2009); doi: 10.1117/12.828060
Variability
Proc. SPIE 7275, Hierarchical modeling of spatial variability with a 45nm example, 727505 (6 March 2009); doi: 10.1117/12.814226
Proc. SPIE 7275, Layout electrical cooptimization for increased tolerance to process variations, 727506 (13 March 2009); doi: 10.1117/12.813969
Proc. SPIE 7275, Tiny footprint programmable electrical defocus monitors, 727507 (13 March 2009); doi: 10.1117/12.814448
Proc. SPIE 7275, The nebulous hotspot and algorithm variability, 727509 (13 March 2009); doi: 10.1117/12.816449
Design Rules for Manufacturability
Proc. SPIE 7275, Simplify to survive: prescriptive layouts ensure profitable scaling to 32nm and beyond, 72750A (13 March 2009); doi: 10.1117/12.814701
Proc. SPIE 7275, Illustration of illumination effects on proximity, focus spillover, and design rules, 72750B (13 March 2009); doi: 10.1117/12.814222
Proc. SPIE 7275, 2D design rule and layout analysis using novel large-area first-principles-based simulation flow incorporating lithographic and stress effects, 72750C (16 March 2009); doi: 10.1117/12.814947
Proc. SPIE 7275, Exploration of complex metal 2D design rules using inverse lithography, 72750D (13 March 2009); doi: 10.1117/12.814197
Variation Aware Design I
Proc. SPIE 7275, Compensating non-optical effects using electrically driven optical proximity correction, 72750E (13 March 2009); doi: 10.1117/12.814872
Proc. SPIE 7275, Impact of lithography variability on analog circuit behavior, 72750G (16 March 2009); doi: 10.1117/12.816509
Proc. SPIE 7275, Design specific variation in pattern transfer by via/contact etch process: full-chip analysis, 72750H (13 March 2009); doi: 10.1117/12.813882
Variation Aware Design II
Proc. SPIE 7275, Interval-value based circuit simulation for statistical circuit design, 72750J (13 March 2009); doi: 10.1117/12.814262
Proc. SPIE 7275, Variations in timing and leakage power of 45nm library cells due to lithography and stress effects, 72750K (13 March 2009); doi: 10.1117/12.816485
Proc. SPIE 7275, Parameter-specific electronic measurement and analysis of sources of variation using ring oscillators, 72750L (13 March 2009); doi: 10.1117/12.814227
Proc. SPIE 7275, Manufacturing system based on tolerance deduced from design intention, 72750M (14 March 2009); doi: 10.1117/12.814081
DFM for Future Nodes
Proc. SPIE 7275, Directional 2D functions as models for fast layout pattern transfer verification, 72750N (13 March 2009); doi: 10.1117/12.813421
Proc. SPIE 7275, Algorithm for determining printability and colouring of a target layout for double patterning, 72750O (13 March 2009); doi: 10.1117/12.814321
Poster Session
Proc. SPIE 7275, Score-based fixing guidance generation with accurate hot-spot detection method, 72750P (13 March 2009); doi: 10.1117/12.811840
Proc. SPIE 7275, Verification of extraction repeating pattern efficiency from many actual device data, 72750Q (13 March 2009); doi: 10.1117/12.811965
Proc. SPIE 7275, Design ranking and analysis methodology for standard cells and full chip physical optimization, 72750R (13 March 2009); doi: 10.1117/12.812972
Proc. SPIE 7275, Practical implementation of via and wire optimization at the SoC level, 72750S (13 March 2009); doi: 10.1117/12.813396
Proc. SPIE 7275, Test structures for 40 nm design rule evaluation, 72750T (13 March 2009); doi: 10.1117/12.813448
Proc. SPIE 7275, Computational requirements for OPC, 72750U (13 March 2009); doi: 10.1117/12.813522
Proc. SPIE 7275, Hotspot management for spacer patterning technology with die-to-database wafer inspection system, 72750V (13 March 2009); doi: 10.1117/12.813648
Proc. SPIE 7275, Source-mask selection using computational lithography incorporating physical resist models, 72750W (13 March 2009); doi: 10.1117/12.813725
Proc. SPIE 7275, Application of pixel-based mask optimization technique for high transmission attenuated PSM, 72750X (13 March 2009); doi: 10.1117/12.813753
Proc. SPIE 7275, Transistor layout configuration effect on actual gate LER, 72750Y (13 March 2009); doi: 10.1117/12.813953
Proc. SPIE 7275, The PIXBAR OPC for contact-hole pattern in sub-70-nm generation, 72750Z (13 March 2009); doi: 10.1117/12.813985
Proc. SPIE 7275, Computational technology scaling from 32 nm to 28 and 22 nm through systematic layout printability verification, 727511 (13 March 2009); doi: 10.1117/12.814253
Proc. SPIE 7275, Variability aware interconnect timing models for double patterning, 727513 (13 March 2009); doi: 10.1117/12.814281
Proc. SPIE 7275, Design-overlay interactions in metal double patterning, 727514 (13 March 2009); doi: 10.1117/12.814299
Proc. SPIE 7275, Detecting context sensitive hot spots in standard cell libraries, 727515 (13 March 2009); doi: 10.1117/12.814316
Proc. SPIE 7275, Clustering and pattern matching for an automatic hotspot classification and detection system, 727516 (13 March 2009); doi: 10.1117/12.814328
Proc. SPIE 7275, Developing DRC plus rules through 2D pattern extraction and clustering techniques, 727517 (14 March 2009); doi: 10.1117/12.814347
Proc. SPIE 7275, Electrical impact of line-edge roughness on sub-45nm node standard cell, 727518 (13 March 2009); doi: 10.1117/12.814355
Proc. SPIE 7275, Full flow for transistor simulation based on edge-contour extraction and advanced SPICE simulation, 727519 (13 March 2009); doi: 10.1117/12.814361
Proc. SPIE 7275, Circuit-topology driven OPC for increased performance/yield ratio, 72751A (13 March 2009); doi: 10.1117/12.814367
Proc. SPIE 7275, Systematic study of the impact of curved active and poly contours on transistor performance, 72751B (13 March 2009); doi: 10.1117/12.814369
Proc. SPIE 7275, Lithography aware statistical context characterization of 40nm logic cells, 72751C (13 March 2009); doi: 10.1117/12.814371
Proc. SPIE 7275, Implementing self-aligned double patterning on non-gridded design layouts, 72751E (13 March 2009); doi: 10.1117/12.814423
Proc. SPIE 7275, High-precision contouring from SEM image in 32-nm lithography and beyond, 72751F (13 March 2009); doi: 10.1117/12.814430
Proc. SPIE 7275, Uniformity-aware standard cell design with accurate shape control, 72751G (13 March 2009); doi: 10.1117/12.814445
Proc. SPIE 7275, Contour-based optical proximity correction, 72751H (13 March 2009); doi: 10.1117/12.814832
Proc. SPIE 7275, Model-based adaptive fragmentation, 72751I (13 March 2009); doi: 10.1117/12.814833
Proc. SPIE 7275, Process variation aware OPC modeling for leading edge technology nodes, 72751J (13 March 2009); doi: 10.1117/12.815094
Proc. SPIE 7275, Large-scale double-patterning compliant layouts for DP engine and design rule development, 72751K (13 March 2009); doi: 10.1117/12.815213
Proc. SPIE 7275, Statistical approach to design DRAM bitcell considering overlay errors, 72751L (13 March 2009); doi: 10.1117/12.815341
Proc. SPIE 7275, Enhanced layout optimization of sub-45nm standard: memory cells and its effects, 72751M (13 March 2009); doi: 10.1117/12.815413
Proc. SPIE 7275, Integration of mask and silicon metrology in DFM, 72751N (13 March 2009); doi: 10.1117/12.816108
Proc. SPIE 7275, Implementing a framework to generate a unified OPC database from different EDA vendors for 45nm and beyond, 72751O (13 March 2009); doi: 10.1117/12.816281
Proc. SPIE 7275, Timing-aware metal fill for optimized timing impact and uniformity, 72751P (13 March 2009); doi: 10.1117/12.816476
Proc. SPIE 7275, Process variability band analysis for quantitative optimization of exposure conditions, 72751Q (13 March 2009); doi: 10.1117/12.816501
Proc. SPIE 7275, Hotspot detection and design recommendation using silicon calibrated CMP model, 72751R (13 March 2009); doi: 10.1117/12.816556
Proc. SPIE 7275, Convergent automated chip level lithography checking and fixing at 45nm, 72751S (13 March 2009); doi: 10.1117/12.816593
Proc. SPIE 7275, Modeling and simulation of transistor performance shift under pattern-dependent RTA process, 72751T (13 March 2009); doi: 10.1117/12.816683
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