This PDF file contains the front matter associated with SPIE Proceedings Volume 7488, including the Title Page, Copyright information, Table of Contents, and the Conference Committee listing.

Microelectronics industry leaders routinely name the cost and cycle time of mask technology and mask supply as top critical issues. A survey was created with support from SEMATECH and administered by David Powell Consulting to gather information about the mask industry as an objective assessment of its overall condition. The survey is designed with the input of semiconductor company mask technologists and merchant mask suppliers. This year's assessment is the eighth in the current series of annual reports. With ongoing industry support, the report can be used as a baseline to gain perspective on the technical and business status of the mask and microelectronics industries. The report will continue to serve as a valuable reference to identify the strengths and opportunities of the mask industry. The results will be used to guide future investments pertaining to critical path issues. This year's survey is basically the same as the 2005 through 2008 surveys. Questions are grouped into categories: General Business Profile Information, Data Processing, Yields and Yield Loss Mechanisms, Delivery Times, Returns, and Services. Within each category is a multitude of questions that create a detailed profile of both the business and technical status of the critical mask industry. This in combination with the past surveys represents a comprehensive view of changes in the industry.

Computational lithography appeared with people's expectation expanding to reduce total lithography cost and to push the resolution limit for launching novel LSI fabrication processes and masks toward advanced LSI devices of 22 nm and beyond. Recently computational lithography grows up into an integration step to achieve the optimum solution between an illumination source and a mask for creating the resist image on a wafer. This integration scheme enables us not only to achieve ultimate single exposure but also to attain higher resolution beyond the physical limitation by means of double patterning technique. The advanced computational lithography requires massive data volume that urges us to construct further effective multi parallel methods. Photomask Japan highlighted the computational lithography in a panel discussion titled "Mask Manufacturing with Massive or Multi-parallel Method" and sub-titled "Massive or Multi-parallel" drives 22 nm (half pitch 32 nm) litho-mask solution?" We reached a conclusion of "Enhancing computation power and more sophisticated computation methods could solve the difficulties about further complicated computation".

Source Mask Optimization (SMO) describes the co-optimization of the illumination source and mask pattern in the frequency domain. While some restrictions for manufacturable sources and masks are included in the process, the resulting photomasks do not resemble the initial designs. Some common features of SMO masks are that the line edges are heavily fragmented, the minimum design features are small and there is no one-to-one correspondence between design and mask features. When it is not possible to link a single mask feature directly to its resist counterpart, traditional concepts of mask defects no longer apply and photomask inspection emerges as a significant challenge. Aerial Plane Inspection (API) is a lithographic inspection mode that moves the detection of defects to the lithographic plane. They can be deployed to study the lithographic impact of SMO mask defects. This paper briefly reviews SMO and the lithography inspection technologies and explores their applicability to 22nm designs by presenting SMO mask inspection results. These results are compared to simulated wafer print expectations.

Die-to-Model (D2M) inspection is an innovative approach to running inspection based on a mask design layout data. The D2M concept takes inspection from the traditional domain of mask pattern to the preferred domain of the wafer aerial image. To achieve this, D2M transforms the mask layout database into a resist plane aerial image, which in turn is compared to the aerial image of the mask, captured by the inspection optics. D2M detection algorithms work similarly to an Aerial D2D (die-to-die) inspection, but instead of comparing a die to another die it is compared to the aerial image model. D2M is used whenever D2D inspection is not practical (e.g., single die) or when a validation of mask conformity to design is needed, i.e., for printed pattern fidelity. D2M is of particular importance for inspection of logic single die masks, where no simplifying assumption of pattern periodicity may be done. The application can tailor the sensitivity to meet the needs at different locations, such as device area, scribe lines and periphery. In this paper we present first test results of the D2M mask inspection application at a mask shop. We describe the methodology of using D2M, and review the practical aspects of the D2M mask inspection.

At the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features (SRAFs) are required. However, their use results in significantly increased mask complexity, making mask defect disposition more challenging than ever. This paper describes how mask patterns can first be recovered from the inspection images by applying patented algorithms using Level Set Methods. The mask pattern recovery step is then followed by aerial/wafer image simulation, the results of which can be plugged into an automated mask defect disposition system based on aerial/wafer image. The disposition criteria are primarily based on wafer-plane CD variance. The system also connects to a post-OPC lithography verification tool that can provide gauges and CD specs, thereby enabling them to be used in mask defect disposition as well. Results on both programmed defects and production defects collected at Samsung mask shop are presented to show the accuracy and consistency of using the Level Set Methods and aerial/wafer image based automated mask disposition.

We report the development of Mask-LMC for defect printability evaluation from sub-200nm wavelength mask inspection images. Both transmitted and reflected images are utilized, and both die-to-die and die-to-database inspection modes are supported. The first step of the process is to recover the patterns on the mask from high resolution T and R images by de-convolving inspection optical effects. This step uses a mask reconstruction model, which is based on rigorous Hopkins-modeling of the inspection optics, and is pre-determined before the full mask inspection. After mask reconstruction, wafer scanner optics and wafer resist simulations are performed on the reconstructed mask, with a wafer lithography model. This step leverages Brion's industry-proven, hardware-accelerated LMC (Lithography Manufacturability Check) technology1. Existing litho process models that are in use for Brion's OPC+ and verification products may be used for this simulation. In the final step, special detectors are used to compare simulation results on the reference and defect dice. We have developed detectors for contact CD, contact area, line and space CD, and edge placement errors. The detection results on test and production reticles have been validated with AIMS^TM.

In addition to the conventional demands for high sensitivities with which the mask inspection system detects the minute size defects, capability to extract true defects from a wide variety of patterns that should not be counted as pseudo defects has been quite demanding. It is necessary to ascertain suppression of MEEF incurred by the combination of parameters such as LER and defects of SRAF. NFT and Brion are jointly developing a mask-image based printability verification system with functions combining their respective technologies with the results from ASET's research. This report describes such defect detection results and introduces the development of a mask inspection system with printability verification function.

The demand for aggressive image placement accuracy and CD uniformity for each generation is being increasingly accelerated by DPT deployment. The method of the correction with the scanner is in effect devised by obtaining the CD and IP maps of each mask after the mask pattern is drawn. We are developing a technology that generates CD and IP maps for each mask from the image data of inspection equipment with the ultimate goal of "in-die overlay improvement" optimizing scanner as well as writer performances. We evaluated the positional measurement function by using NPI inspection system with the evaluation mask.

Reticle defectivity has been a widely discussed topic in the last few years primarily due to ongoing haze issues but also because of the increasing number of the qualification methods available in the fab. Mask shops are taking a closer look at the alternatives to the direct reticle inspection [1], making a step towards wafer inspection as a valid option for reticle qualification. High MEEF patterns represent the most interesting and challenging case study due to potentially comparable sensitivity performance of the wafer inspection and reticle inspection tools as reported in [2]. A reticle with programmed defects in different environments was used to define detection limits, capture rates and noise levels for both direct reticle inspection and the inspection of the wafer print. Reticle inspection was performed using KLA587 tool. For the inspection of the wafer prints two most advanced DUV inspection tools were used. Defect sizes were defined on the reticle and on the wafer using SEM CD tools. The focus of this study was to identify gaps and opportunities existing in the reticle qualification chain starting with the outgoing qualification at the mask shop and continuing during the reticle lifetime in the fab. Results and conclusions of this investigation will be presented and discussed in conjunction with the prospects and possible modifications of pursued approach for 45nm and the future nodes.

The AFM-technology based technique of nanomachining has been well-proven in the area photomask repair since its introduction a decade ago. However, the problems and challenges facing the mask repair operator have changed significantly in this period, and ongoing engineering platform development has reflected these shifts, as well as refinements based on specialized experience with nanomachining repair technology. Improvements from this technical development include improved monitoring and control of the internal tool environment (to minimize AFM scan noise and thermal drift), and automation to easily and reliably clean and characterize the 3-dimensional shape of the NanoBit^TM apex. For repair applications, improvements will be shown for the automated and operator-intuitive reconstruction of 3-dimensional nanometer-scale patterns on the photomask with referenced z-depth and xy alignment regardless of pattern orthogonality. Multiple pattern repair capability is also reviewed due to a greater diversity of available process options and multi-repair box capability with a common quartz-level z-reference point. Finally, it will be shown how all of these individual improvements work together to provide extended repair capability down to the 32 nm technology node.

As the industry moves towards sub-65nm technology nodes, the mask inspection, with increased sensitivity and shrinking critical defect size, catches more and more nuisance and false defects. Increased defect counts pose great challenges in the post inspection defect classification and disposition: which defect is real defect, and among the real defects, which defect should be repaired and how to verify the post-repair defects. In this paper, we address the challenges in mask defect verification and disposition, in particular, in post repair defect verification by an efficient methodology, using SEM mask defect images, and optical inspection mask defects images (only for verification of phase and transmission related defects). We will demonstrate the flow using programmed mask defects in sub-65nm technology node design. In total 20 types of defects were designed including defects found in typical real circuit environments with 30 different sizes designed for each type. The SEM image was taken for each programmed defect after the test mask was made. Selected defects were repaired and SEM images from the test mask were taken again. Wafers were printed with the test mask before and after repair as defect printability references. A software tool SMDD-Simulation based Mask Defect Disposition-has been used in this study. The software is used to extract edges from the mask SEM images and convert them into polygons to save in GDSII format. Then, the converted polygons from the SEM images were filled with the correct tone to form mask patterns and were merged back into the original GDSII design file. This merge is for the purpose of contour simulation-since normally the SEM images cover only small area (~1 μm) and accurate simulation requires including larger area of optical proximity effect. With lithography process model, the resist contour of area of interest (AOI-the area surrounding a mask defect) can be simulated. If such complicated model is not available, a simple optical model can be used to get simulated aerial image intensity in the AOI. With built-in contour analysis functions, the SMDD software can easily compare the contour (or intensity) differences between defect pattern and normal pattern. With user provided judging criteria, this software can be easily disposition the defect based on contour comparison. In addition, process sensitivity properties, like MEEF and NILS, can be readily obtained in the AOI with a lithography model, which will make mask defect disposition criteria more intelligent.

In today's economic climate it is critical to improve mask yield as materials, processes and tools are more time and cost involved than ever. One way to directly improve mask yield is by reducing the number of masks scrapped due to defects which is one of the major mask yield reducing factors. The MeRiT^TM MG 45, with the ability to repair both clear and opaque defects on a variety of masks, is the most comprehensive and versatile repair tool in production today. The cost of owning multiple repair tools can be reduced and time is saved when fast turnaround is required, especially when more than one defect type is present on a single mask. This paper demonstrates the ability to correct repair errors due to human mistakes and presents techniques to repair challenging production line defects with the goal of maximizing mask repair yield and cycle time reduction.

The continuous shrinking of the semiconductor device nodes requires tough specifications of CD uniformity which result in narrowing of the lithography process window. Finding methods for expanding the process window will enable to continue manufacturing at least one more generation using the existing litho equipment. The CDC technology has been described in detail in past studies beginning in 2006; however it has typically been studied from a mask shop perspective. In this paper we will demonstrate a way to improve the CD Uniformity (CDU) on a new mask, which has a CD uniformity problem that leads to shrinking of the lithography process window, by using the Carl Zeiss CD Control (CDC) Technology. The methodology used and the process window improvement verification we show are based purely on fab available techniques and do not require any input from the mask shop. A production memory product in PSC fab P1/2 showed reduced yield due to reduced process window in one line/space (L/S) layer. A close investigation in the fab showed wafer CD non-uniformity of 6.5nm Range and 3.95nm 3S in this layer due to a mask CDU problem. A CDC process to improve the CDU was applied by the Carl Zeiss CDC200 tool based on wafer CD data only. Post CDC treatment results show that CD Range was reduced to 3.8nm (42% improvement) and 3S was reduced to 1.94nm (51% improvement). Further assessment of the litho process window of this layer showed an increase of CD-DOF from 0.15um before (Pre) CDC to 0.30um after (Post) CDC and an exposure latitude increase from 14.1% Pre to 26.7% Post CDC. To summarize our findings, applying the CDC process to the problematic layers allowed to increase the PW in

In optimizing e-beam resist process conditions for photomask lithography, the primary performance measurements for optimization are resolution, critical dimension uniformity (CDU), line edge roughness (LER), and linearity. Through technology nodes, one parameter that has consistently shown a critical impact on these factors is the post exposure bake (PEB) condition. With 32nm e-beam resist technologies having reduced temperature sensitivity, this paper investigates the current impact of PEB conditions. The PEB assessment will summarize the influence of PEB temperature, duration and environment flow on 32 nm positive tone resists by reporting and analyzing two of the primary performance measurements: CDU and LER.

According to the ITRS roadmap for lithography (2008 edition), the CD uniformity requirement of optical masks beyond 32nm HP is less than 1.5nm (3σ). Especially for double patterning lithography, not only the global uniformity but also the local uniformity is of very high concern. Therefore it is imperative that the develop process will yield CD-linewidth control independent of pattern sizes or pattern loading, following precisely those pattern size image correction strategies applied during mask writing (e.g. proximity and fogging correction). Conventional methods of resist develop cannot meet such requirement without negative side effects (e.g. increased dark loss, pattern collapse, global CD-uniformity degradation and/or defect issues). The ASonic® nozzle developed by HamaTech APE combines the very favorable dark loss, defect and global CD-linewidth control benefits of a fast and uniform low impact initial develop dispense (surface wetting), with an enhanced developer agitation through acoustic streaming, which provides improved local CD-control independent of pattern size and loading. The principle functionality of the ASonic® nozzle is described. Developing loading effect is examined with various conditions and CD linearity, proximity and CD uniformity are also verified.

Both Langmuir probe and spatial optical emission spectroscopy (OES) measurements have been used to characterize the Tetra^TM chrome etch chamber. Langmuir data was measured over a range of process pressures between 1.5mT and 10mT and source powers between 150W and 500W. At 350W, the data show electron and ion densities near 1 x 10⁹ cm^-3 for Ar and for Cl₂/O₂ etch plasmas. Ion density trends with pressure were observed to be opposite for the two plasmas. The effect of the third electrode designed in the chamber was demonstrated to reduce ion density by more than an order of magnitude for Ar plasma and still lower for Cl₂/O₂ plasma. Electron temperature and plasma potential are also reduced. Radial OES measurements are reported with a new apparatus that yields direct spatial emission data. Spatial scans of infrared emission from atomic Cl were measured under a range of several chamber conditions already measured with the Langmuir probe. The scans showed that the emission uniformity above the mask can be adjusted to a flat profile by selection of the process condition.

In order to embody high resolution at 32 nm and below, molybdenum silicide (MoSi) phase shift mask (PSM) is essential material in the ArF lithography process, generally. But some problems reported from for the variation of PSM characteristics like transmittance variation and chemical durability. This change in characteristics is an issue for the yield drop in the semiconductor device manufacturing. So we study the behavior of MoSi PSM thin film in the view point of the ArF laser exposure in this paper. Firstly, the problems of MoSi thin film by the 193 nm exposure are observed. From the result, 0.36 % of the transmittance was changed by 193 nm irradiation with 10 kJ of energy. Accordingly, MoSi thin film characteristics were degraded by the ArF laser irradiation. The reason for the transmittance degradation by irradiation for MoSi thin film was analyzed. Also, we found that the oxygen was activated by the ArF laser and this activated oxygen penetrated to MoSi thin film. Consequently, the transmittance increased by the penetrated oxygen. Then we investigated the improvement scheme for MoSi thin film's irradiation characteristic. First, the transmittance of the thin film was changed by the reactive gas ratio change. Also, the Si ratio in the MoSi thin film was changed. Lastly, densification process was applied. Consequently, the densification process for the MoSi thin film improved the irradiation characteristics.

Current high end chips require an extremely precise fabrication of lithographic masks. Some of the most critical parameters are the placement of structures on the masks as well as their dimensional tolerances. Improving these two key parameters has always been one of the central objectives of the Advanced Mask Technology Center (AMTC). To this end, the AMTC has complemented its process development by a set of enhancement schemes which are used to compensate residual process signatures. In this paper, improvements achieved in the area of CD uniformity (CDU) and pattern placement are shown. The correction schemes take first principle considerations as well as empirical findings into account. Based on this, a set of design and process parameters is used to determine the spatial corrections which will optimize mask quality parameters. This enables the AMTC to tailor the writing parameters to the needs of each mask design. Latest results for the 32nm technology show that values as low as 5nm image placement error and 3nm CDU can be reached at the same time.

Under laser exposure, bimetallic thin films of Bi/In and Sn/In oxidize becoming transparent. By controlling the power, direct-write binary and grayscale photomasks have been produced with the mask's transparency (optical density, OD), ranging between ~3.0 (unexposed) to <0.22 (fully exposed). Precise 3D micro-optics require both high vertical accuracy, gray levels over large OD changes, and precise lateral pattern creation. To achieve this result, an OD measurement system has been developed that provides real-time measurements while the masks are being written. Using stationary exposures of Bi/In and Sn/In films with varying laser powers, the reduction in OD of the films is measured with respect to time. Using 1-minute exposures, the films reach a 'saturated' level within a second at 180 mW while at 50 mW their OD gradually reduces. The influence of film's thickness is examined with thicker films requiring a longer exposure time in order to reach a similar OD level. For mask-writing, the optimal line spacing is dependent upon the laser beam's power distribution profile. Using a line-spacing 3-5 times smaller than the effective spot-size, variations in the patterned mask caused by a Gaussian-distributed beam can be minimized at the cost of increasing the writing time of the mask by the same factor. The Gaussian-distributed beam at different laser powers is also found to create shifts in the OD measurements that are problematic for a closed-loop mask-writing system. The influence of the beam's power distribution is discussed along with solutions to eliminate the problems.

Nanoimprint lithography (NIL) is a candidate of alternative, low cost of ownership lithography solution for deep nano-meter device manufacturing12. For the NIL template pattern making, we have been developing the processes with 100keV SB EB writer and 50keV VSB EB writer to achieve the fine resolution of near 20nm1-7. However, inspection of nanoimprint template posed a big challenge to inspection system due to the small geometry, 1x comparing to 4x of Optical mask and EUV mask. Previous studies of nanoimprint template inspection were performed indirectly on a stamped wafer and/or on a round quartz wafer13. Electron beam inspection (EBI) systems have been widely used in semiconductor fabs in nanometer technology nodes. Most commonly EBI applications are electrical defects, or voltage contrast (VC) defects detection and monitoring8-11. In this study, we used a mask EBI system developed by Hermes Microvision, Inc. (HMI) to directly inspect a NIL template with line/space and hole patterns half pitched from 22nm to 90nm and with program defects sized from 4nm to 92nm. Capability of inspection with 10nm pixel size has been demonstrated and capability of capturing program defects sized 12nm and smaller has been shown. This study proved the feasibility of EBI as inspection solution of nanoimprint template for 22nmHP and beyond.

Cost of ownership projections have often been used to determine the potential costs associated with the introduction of novel lithography applications. While they are often controversial and their accuracy or usefulness are a function of the validity of the assumptions used to build the model; they provide insight to the real technical issues, as well as, the critical areas that required the most financial and technical resources for success and profitability. This paper will provide a first look at the key technical and financial challenges of using nano-imprint technology for the fabrication of hard disk drives (HDD). The focus will be on the master template/stamp cost of ownership, pattern generation time, inspection and repair and yield. This paper will not address the costs associated with replication of the master template because many of the assumptions for replication robustness have yet to be realized in a production environment.

UV nanoimprint lithography (UV-NIL) is a high-throughput and cost-effective patterning technique for complex nanoscale features and is considered a candidate for CMOS manufacturing at the 22nm node and beyond. To achieve this target a complete template fabrication infrastructure including inspection and repair is needed. Due to the 1X magnification factor of imprint lithography the requirements for these steps are more challenging compared to those for 4X photomasks. E-beam repair is a very promising repair technology for high-resolution imprint templates. It combines the advantages of precise beam placement using fine resolution images and damage free repair by electron beam induced chemical reactions. In this work we performed template repair using a new test stand with improved beam and stage stability. Repeatability of 3D pattern reconstruction with main focus on shrunk lateral repair dimensions and height control was investigated. The evaluation was done on various features in a 40nm half pitch design. Additionally, the resolution capability of the new hardware was examined on selected programmed defects in a 32nm half pitch design. A first qualitative examination of the repaired template was done using top-view SEM images taken from the test stand before and after repair. The repaired template was then imprinted on 300mm silicon wafers, and the imprinted repaired defects were analyzed using a SEM Zeiss Ultra 60.

The Nano Imprint Lithography (NIL) process has been proposed as a method of making Discrete Track Media (DTM) for the next generation hard disc. The UV-NIL process is especially practical because of its minimal thermal expansion and high manufacturing throughput. Quartz template fabrication is a key issue in UV-NIL. Duplication from a Si master using NIL was studied as a method of such quartz template fabrication. In this method, the UV light radiated through the quartz substrate to reach the resist. This method avoids typically used Cr (and other hard masks) on the quartz substrate, eliminating the problem of low throughput caused by low transmission efficiency of the hard mask. The success of this method therefore depends crucially on the etching selectivity of quartz to NIL resist used as the resist mask. Using a newly developed NIL resist with high etching selectivity and duplicating by a "hard mask-less" method, a 125nm track pitch (TP), 2.5 inch full-surface quartz template with uniform pattern height was fabricated. A 75nm TP quartz template of 60nm pattern height was also fabricated using this method.

Masks computed by use of Inverse Lithography Technology (ILT) are being increasingly used in 32nm and below nodes for their significantly better litho performance outperforming model-based OPC [1,2]. This technique poses the design of photomasks as an inverse problem and then solves for the optimal photomask using rigorous mathematical approach [3,4]. One such approach is the level set based method [5] wherein a level set function φ(x,y) is made to represent the contour of the mask. The zero level set φ(x,y)=0 then represents the actual mask at a given instance. The same level-set technique has now been extended to determine the most optimized source φ(p,q) for a given target or mask. Cooptimization of both the source and mask is a natural extension of optimizing the mask alone in ILT. The same cost function, say maximizing DOF, which is used to compute the ILT mask can be used for the source optimization as well. This approach enables accurate and fast computation of the optimized source and mask for given set of patterns and also utilizes running on a distributed computing environment. In this paper, the level set based SMO approach will be first validated on simple contact array patterns and then extended to the optimization of sample 22nm logic contact design patterns, including array, SRAM and random logic. The effect of using different emphasis in defining the cost function will also be studied.

As the semiconductor industry moved to 4X technology nodes and below, low-k1 ArF lithography approached the theoretical limits of single patterning resolution, a regime typically plagued by marginally small process windows. In order to widen the process window bottleneck, projection lithography must fully and synergistically employ all available degrees of freedom. The holistic lithography source mask optimization (SMO) methodology aims to increase the overall litho performance and achieve a robust process window for the most challenging patterns by balancing between the mask and illumination source design influences. The typical complexity of both mask and illumination source that results from a generic SMO process exceeds the current norm in the lithographic industry. In particular, the SMO literature reports on masks that fully operate as diffractive optical elements, with features that have little resemblance to the final wafer-level pattern. Additionally, SMO illumination sources are characterized by parametric or pixelated shapes and a wide range of transmission values. As a consequence of the new mask and source designs, qualifying the mask for printing and non-printing defects and accurate assessment of critical dimensions becomes one of the main mask inspection challenges. The aerial imaging technologies of Applied Material's Aera2^TM mask inspection tool provide enabling solutions by separating out only the defects that matter and accurately measures aerial imaging critical dimensions. This paper presents the latest numerical and experimental SMO mask qualifications research results performed at Applied Materials with a mask containing two-dimensional DRAM production structures.

We proposed a new method of generating and optimizing sub-resolution assist features (SRAFs). This method is based on a newly proposed ILT algorithm-Cost-function-Reduction method (CFRM). CFRM is proved to be much effective and efficient than gradient-based algorithm and traditional simulated annealing method. We improve CFRM to be an initial condition independent algorithm (ICIA) by tuning some running parameters. The robustness of ICIA is verified numerically by six mask patterns and two mask technologies in partial-coherence image model using 100 randomly generated mask patterns. Results showed that all are converged to similar final mask patterns with less than 3% differences of the final image edge placement error (EPE). The skeleton of the final mask pattern can be decided by first tens of iterations. Based on the above properties, an efficient and effective algorithm is proposed to handle SRAFs placement. This effectiveness method is demonstrated by different patterns using different mask technologies.

Inverse Lithography Technology (ILT) is becoming one of the strong candidates for 32nm and below. ILT masks provide significantly better litho performance and need to be enabled for production as one of the leading candidates for low-k1 lithography. By the very nature ILT masks are computed, they could seem to be complicated to manufacture in production. In a prior publication [1], it has been shown at clip level that the Inverse Synthesizer (IS^TM) product has the capability to adjust for mask complexity to make it more manufacturable while maintaining the significant litho gains of nearly ideal ILT mask. The production readiness of ILT needs to be studied at full chip level with various aspects including mask data fracturing, MRC constraints, writing time, and inspection. The computation of ILT mask usually starts with the calculation of an optimized contoured mask then followed by manhattanization step to convert contour into horizontal-vertical segments. By varying the segmentation length during manhattanization, it can affectively change the mask complexity while maintains the shape of mask. The result of segmentation length impact on writing time and lithography performance at full-chip is presented. MRC is another important factor in mask manufacturability which needs to be carefully studied. Mask pattern transfer fidelity and inspectability at various selected MRC rules are also presented in the paper.

At 32 nm node and beyond, one of the most critical processes is the holes patterning due to the Depth of Focus (DOF) that becomes rapidly limited. Thus the use of Sub Resolution Assist Features (SRAF) becomes mandatory to keep DOF at a sufficient level through pitch. SRAF are generally generated using Rule Based OPC with a different cleaning step to avoid risk of SRAF printing or conflict with main feature. One of the key challenges of using such a technique is the ability of placing SRAF in random holes features. The rule based approach cannot treat all the configurations resulting in non-optimal SRAF placement for certain main feature. On the other hand, Inverse Lithography has shown the ability of generating SRAF at the ideal size and position (theoretically) 1 and interest of this technique has been proven experimentally 2,3. Nevertheless, this kind of technique is not yet ready for maskshop due to MRC limitation caused by the pixelated SRAF output, and the important mask writing time due to the shotcount 4. In this paper we propose to make a comparison of the two approaches on random 2D features. We will see that Inverse Lithography permits to keep a sufficient DOF on 2D features configurations where Rule based appears to be limited. Simulated and experimental results will be presented comparing Rule based, Ideal and MRC constraint SRAF in terms of DOF and Runtime performance for hole patterning

Inverse imaging has been long known to provide a true mathematical solution to the mask design problem. However, it is often times marred by problems like high run-time, mask manufacturability costs, and non-invertible models. In this paper, we propose a mask synthesis flow for advanced lithography nodes, which capitalizes on the inverse mask solution while still overcoming all the above problems. Our technique uses inverse mask technology (IMT) to calculate an inverse mask field containing all the useful information about the AF solution. This field is fed to a polygon placement algorithm to obtain initial AF placements, which are then cooptimized with the main features during an OPC/AF print-fix routine to obtain the final mask solution. The proposed flow enables process window maximization via IMT while guaranteeing fully MRC compliant masks. We present several results demonstrating the superiority of this approach. We also compare our IMT-AFs with the best AF solution obtained using extensive brute-force search (via a first principles simulator, S-litho), and prove that our solution is optimum.

In a recent paper15, we presented a novel method for fully automated model-based generation and optimization of sub-resolution assist features which, when placed on a contact layer photomask, minimize the variations in the printed pattern with respect to focus change. Here we extend that methodology to improve the contrast of the light intensity in addition to minimizing variations caused by focus change.

Image placement (IP) and overlay error specifications in the International Technology Roadmap for Semiconductors (ITRS) continue to get tighter with each successive technology node. One of the significant contributors to IP error is the non-flatness of the reticle substrate. In this paper, we will discuss in detail the effect of reticle substrate shape on the overlay performance in extreme ultraviolet (EUV) tools. Substrate shape-induced overlay effects are important when multiple device levels are printed using EUV lithography. We present an analysis of 20 blanks with different flatness specifications for overlay signatures when used for printing multiple device levels. A comprehensive analysis of scanner correctable and non-correctable errors for different substrate shapes will also be presented. Non-flatness specifications for EUV blanks will be reviewed based on these reticle-matching results. We will discuss results from flatness measurements and the effect on overlay budget due to mismatched substrates using several substrates with different flatness specifications.

When thinner absorber mask is practically applied to the EUVL for the ULSI chip production, it is inevitable to introduce EUV light shield area in order to suppress leakage of the EUV light from adjacent exposure shots. We believe that light-shield border of multilayer etching type is promising structure in terms of mask process flexibility for higher mask CD accuracy In this paper, we evaluate etching impact of absorber and multilayer on mask flatness and image placement change through mask process of thin absorber mask with light-shield border of multilayer etching type structure. And then, we clarify the relation between mask flatness and mask image placement shift.

Fabricating defect-free extreme ultraviolet lithography (EUVL) multi-layer (ML) mask blanks presents a big challenge in EUVL technology. ML defect sources primarily come from substrate defects and ML deposition adders. Defect reduction, therefore, needs to address many development aspects, such as substrate material, substrate polishing, substrate cleaning, blank handling, and ML deposition. High investment cost and potential low blank yield can quickly drive up EUVL cost of ownership. However, allowing a few defects on the ML blank can improve the blank yield drastically. Utilizing such defect-blanks through defect mitigation schemes has been proposed. It includes directly repairing small ML phase and amplitude defects, mask absorber pattern proximity repair, and using absorber pattern to cover the ML defects. It includes directly repairing small ML phase and amplitude defects,1-2 repairing mask absorber pattern to compensate the effect of an adjacent ML defect,3 and using absorber pattern to cover the ML defects.4 In each case, the ML defects will first need to be identified and located during the ML blank defect inspection. To precisely locate the ML defects on the blank, fiducial marks on the ML blank are needed for mask alignment and defect location identification. In this paper, we will present the details of the ML defect mitigation process flow, i.e., using absorber pattern to cover the ML defects, and the corresponding experimental validation of this mitigation flow. We will also discuss the fiducial marking scheme, its application in the defect mitigation flow, the error budget of ML defect mitigation, such as defect position measurement error, fiducial mask position error, e-beam alignment errors, etc.

We have been developing an actinic full-field mask blank inspection system to detect multilayer phase defects with dark field imaging. Using the current system, we have analyzed the probability of defect detection and occurrence of false defects with variations in defect signal intensity and in background intensity. The result indicates that the size of the smallest defect for 100 % detection with no false defect at full-field inspection is 2.0 nm in height and 78 nm in width. A 100 % detection of smaller defects, 1.5 nm high and 60 nm wide, with no false defect at full-field inspection requires 46 % reduction of the detection threshold. This means that for further improvement of defect sensitivity, a 46 % reduction of CCD noise level, or improvement of the defect detection algorithm, will be required.

Electron beam direct write lithography is used in the ASIC manufacturing industry to sustain optical lithography for prototyping applications, low volume production and for the development of the next technological nodes. However the standard proximity effects corrections based on dose modulation are not sufficient to provide the patterning accuracy required for the sub-32nm nodes. New methods are needed to push the resolution capabilities of electron beam lithography. In a previous paper, a new writing strategy based on multiple pass exposure has been introduced. It consists in adding small electron Resolution Improvement Features (eRIF) atop the nominal features. Thanks to this new method, critical lines have been patterned with enlarged energy latitude. In this paper, multiple pass exposure is applied to the sub-32nm nodes. The influence of the design of the eRIF is analysed in detail. The best conditions in terms of dose, size and placement of the eRIF are used to establish a methodology to optimize this new strategy. Using multiple pass exposure, the energy latitude was increased up to about 20% which is three times the energy latitude of the standard exposure. Then the impact of multiple pass exposure on the writing time of the electron beam tool is studied. It appears that a compromise has to be found between the writing time and the improvement of the energy latitude. Finally it is shown that the resolution capabilities of the electron beam lithography can be increased using the multiple pass exposure strategy.

A detailed evaluation study has been performed with respect to the suitability of projection electron and ion multi-beam lithography for the fabrication of leading-edge complex masks. The study includes recent results as obtained with electron and ion multi-beam proof-of-concept systems with 200x reduction projection optics where patterns are generated on substrates using a programmable aperture plate system (APS) with integrated CMOS electronics, generating several thousands of well defined beams in parallel. A comparison of electron and ion projection multi-beam writing is provided, in particular with respect to the suitability to expose non-chemically amplified resist (non-CAR) materials. The extendibility of projection multi-beam technologies for 16nm hp, 11nm hp and 8nm hp mask nodes is discussed as well as for wafer direct write for 22nm hp and below.

Optical lithography is facing resolution limit. To overcome this issue, highly complicated patterns with high data volume are being adopted for optical mask fabrications. With this background, new electron beam mask writing system, EBM- 7000 is developed to satisfy requirements of hp 32nm generation. Electron optical system with low aberrations is developed to resolve finer patterns like 30nm L/S. In addition, high current density of 200 A/cm² is realized to avoid writing time increase. In data path, distributed processing system is newly built to handle large amounts of data efficiently. The data processing speed of 500MB/s, fast enough to process all the necessary data within exposure time in parallel for hp32nm generation, is achieved. And this also makes it possible to handle such large volume dense data as 2G shots/mm² local pattern density. In this paper, system configuration of EBM-7000 with accuracy data obtained are presented.

In the Mask D2I project at ASET, the authors assembled an electron beam exposure system to prove the concept ofmulti column cell with character projection technology. They performed beam calibrations in individual column cells to evaluate the resolution capabilities and stitching accuracies of the deflection fields of the system. Isolated 35nm line pattern and 60nm 1:1 line-and-space pattern were exposed in each column cell. Present stitching errors among the deflection fields were less than 15nm. We also evaluated stitching errors of patterns exposed by the different column cells. The stitching errors among the column cells were estimated to be less than 20nm. We are now investigating the origins of these errors to improve the exposure accuracies of the multi column cell system.

In preparation for the international Nano1 linewidth comparison on photomasks between nine national metrology institutes, the National Institute of Standards and Technology (NIST) and the Physikalisch-Technische Bundesanstalt (PTB), initiated a bilateral linewidth comparison in 2008, independent of and prior to the Nano1 comparison in order to test the suitability of the mask standards and the general approach to be used for the Nano1 comparison. This paper reports on the current status of the bilateral comparison. In particular the methods for linewidth metrology applied at NIST and PTB and its major uncertainty contributions will be discussed based on actual measurements results for both of the mask standards chosen for the bilateral comparison.

Current methodologies for determining pattern placement errors on production masks are based primarily on limited sample sizes and Gaussian statistics. These methodologies and accepted practices may not be indicative of the true nature of pattern placement errors actually occurring on the photomasks. Pattern placement errors can originate from a variety of sources on e-beam generated photomasks. Random shot placement errors, localized charging and heating, proximity effects, global charging, and writing strategies may all have an impact on overall pattern placement errors. It is suspected therefore that pattern placement errors on photomasks are not all well approximated as Gaussian, but include a number of significant errors with unique spatial signatures that need to be addressed differently. This paper investigates different measurement sampling strategies on a single leading edge poly layer to determine what level or amount of measurements might be necessary to more accurately determine the probabilities of the true placement errors on the photomask, and what spatially dependent components may or may not be accurately represented in the measurements.

A novel optical critical dimension (CD) metrology tool equipped with a 193 nm laser source and a high numerical aperture objective (NA=0.9) is under development at the Physikalisch-Technische Bundesanstalt (PTB), the National Metrology Institute of Germany. The CD tool is designed for characterization of photomasks up to 6-inch and offers "atwavelength" measurements for current and future 193 nm lithography. Design, construction and realisation of the CD metrology tool is presented in this paper. The illumination system, which employs a multi-mode DUV fiber to reduce the lateral coherence of the laser beam, is detailed with numerical simulation and experimental investigation. Combined with precision optical modelling, this optical CD tool will be applicable for quantitative determination of the microstructures on 32 nm node photomasks with uncertainty less than 10 nm.

The demands on CD (critical dimension) metrology amount in terms of both reproducibility and measurement uncertainty steadily increase from node to node. Different mask characterization requirements have to be addressed like very small features, unevenly distributed features, contacts, semi-dense structures to name only a few. Usually this enhanced need is met by an increasing number of CD measurements, where the new CD requirements are added to the well established CD characterization recipe. This leads straight forwardly to prolonged cycle times and highly complex evaluation routines. At the same time mask processes are continuously improved to become more stable. The enhanced stability offers potential to actually reduce the number of measurements. Thus, in this work we will start to address the fundamental question of how many CD measurements are needed for mask characterization for a given confidence level. We used analysis of variances (ANOVA) to distinguish various contributors like mask making process, measurement tool stability and measurement methodology. These contributions have been investigated for classical photomask CD specifications e.g. mean to target, CD uniformity, target offset tolerance and x-y bias. We found depending on specification that the importance of the contributors interchanges. Interestingly, not only short and long-term metrology contributions are dominant. Also the number of measurements and their spatial distribution on the mask layout (sampling methodology) can be the most important part of the variance. The knowledge of contributions can be used to optimize the sampling plan. As a major finding, we conclude that there is potential to reduce a significant amount of measurements without loosing confidence at all. Here, full sampling in x and y as well as full sampling for different features can be shortened substantially almost up to 50%.

The current photomask linewidth Standard Reference Material (SRM) supplied by the National Institute of Standards and Technology (NIST), SRM 2059, is the fifth generation of such standards for mask metrology. The calibration of this mask has been usually done using an in house NIST ultra-violet transmission microscope and an Atomic Force Microscope (AFM). Recently, a new optical reflection scatterfield microscope has been developed at NIST for wafer inspection, Critical Dimension (CD) and overlay metrology purposes. Scatterfield microscopy relies on illumination engineering at a sufficiently large Conjugate Back Focal Plane (CBFP) of the microscope.1 Our new scatterfield reflection microscope uses 193 nm excimer laser light as well as sophisticated configurations to allow measurement of both the image plane and the Fourier plane using full-field and angle-resolved illumination. By reducing the wavelength compared to many current metrology tools that work in the visible light and near ultra-violet range, we have made substantial improvements in image resolution2 and commensurate gains in sensitivity to geometrical parameters. We present a preliminary study on the use of this new microscope to calibrate and measure features of this SRM photomask. The 193 nm scatterfield microscope is used in full-field mode with a NA range from 0.12 to 0.74 using our scatterfield imaging method. Experimental results obtained on isolated lines for different polarization states of the illumination are presented and discussed. Pitch measurements are compared to the measurements done on our NIST Ultra-Violet (UV) transmission microscope.

Double Patterning Lithography techniques place significantly greater demand on the requirements for pattern placement accuracy on photomasks. The influence of the pellicle on plate bending is also a factor especially when the pellicle distortions are not repeatable from substrate to substrate. The combination of increased demand for greater accuracy and the influence of pellicle distortions are key factors in the need for high resolution through-pellicle in-die measurements on actual device features. The above requirements triggered development of a new generation registration metrology tool based on in-depth experience with the LMS IPRO4. This paper reports on the initial experimental results of DUV laser illumination on features of various sizes using unique measurement algorithms developed specifically for pattern placement measurements.

New lithography techniques like Double Patterning, Computational Lithography and Source Mask Optimization will be used to drive immersion lithography to its limits. This results in several challenges for the mask maker. The extremely high MEEF values amplify small process variations on the mask features on the wafer. Complex mask features using sophisticated OPC and assist features as well as double patterning tightens the registration and CDU specification at the same time. Especially, overlay becomes more and more critical and must be ensured on every die. In-die registration and CD metrology on arbitrary features is required to measure mask performance precisely. In this paper an overview about several in-die metrology techniques will be given. Application of in-die CD measurements using the Zeiss WLCD32 tool as well as in-die registration measurements using the Zeiss Prove tool will be shown and discussed.

The Critical Dimension Uniformity (CDU) specification on photomasks continues to decrease with each successive node. The ITRS roadmap for optical masks indicates that the CDU (3 sigma) for dense lines on binary or attenuated phase shift mask is 3.4nm for the 45nm half-pitch (45HP) node and will decrease to 2.4nm for the 32HP node. The current capability of leading-edge mask shop patterning processes results in CDU variation across the photomask of a similar magnitude. Hence, we are entering a phase where the mask CDU specification is approaching the limit of the capability of the current Process of Record (POR). Mask shops have started exploring more active mechanisms to improve the CDU capability of the mask process. A typical application is feeding back the CDU data to adjust the mask writer dose to compensate for non-uniformity in the CDs, resulting in improved quality of subsequent masks. Mask makers are currently using the CD-SEM tool for this application. While the resolution of SEM data ensures its position as the industry standard and continued requirement to establish the photomask CD Mean to Target value, a dense measurement of CDs across the reticle with minimal cycle time impact would have value. In this paper, we describe the basic theory and application of a new, reticle inspection intensity-based CDU approach that has the advantage of dense sampling over larger areas on the mask. The TeraScanHR high NA reticle inspection system is used in this study; it can scan the entire reticle at relatively high throughput, and is ideally suited for collecting dense CDU data. We describe results obtained on advanced memory masks and discuss applications of CDU maps for optimizing the mask manufacturing process. A reticle inspection map of CDU is complementary to CD-SEM data. The dense data set has value for various applications, including feedback to mask writer and engineering analysis within the mask shop.

Scanner performance is influenced by the quality of its illumination, mechanical and optical elements and the impact of these factors on the printed wafer. Isolation of the aggregated scanner errors from other sources of error on the printed wafer is a challenging task since the total error budget of the lithography process consists of many dynamic sources, such as wafer planarity and film stack properties. The mask is conceptually part of the scanner optics and integral to the imaging process. Therefore the mask error contribution to the overall error becomes relevant for any advanced lithography process. Discrete mask measurement techniques are currently used to create across mask CDU maps. By subtracting these maps from their final wafer measurement CDU map counterparts, it is possible to assess within certain limitations the real scanner induced printed errors. The current discrete measurement methods are time consuming and some overlook errors other than linewidth variations, such as transmission and phase variations, all of which influence the final printed CD variability. In this paper we present a methodology, which leverages Applied Materials Aera2^tmmask inspection tool, based on a socalled IntenCDtm technology. IntenCD aerial imaging produces maps by scanning the mask at high speed, offer full mask coverage and accurate assessment of all mask induced errors simultaneously, making it ideal for mask CDU characterization and scanner qualification.

As the mask technology moves towards production of 36 nm and 22 nm DRAM half pitch nodes, printing features and sub-resolution assist features (SRAF) shrink below 80 nm. These narrow features become more fragile and place new demands on cleaning processes for a physically non damaging solution. These challenges include compatibility with new materials, oxidation, chemical contamination sensitivity, proportionally decreasing printable defect size, and a requirement for a damage-free clean. CO₂ cryogenic aerosol cleaning has, for many years, shown potential to offer a wide process window for meeting some of these new challenges. CO₂ cryogenic aerosol cleaning for post AFM repair debris cleaning has been used for many years on masks greater than 90 nm DRAM half pitch nodes. Until recently, CO₂ purity and delivery hardware issues resulted in foreign material adder (FMACO₂) contamination and SRAF damage below 150 nm critical feature size. Some key desirable properties of CO₂ cryogenic aerosol cleaning are the non-oxidizing and non-etching properties when compared to current chemical wet clean processes. In this paper, recent advancements of CO₂ cryogenic aerosol cleaning technology are presented, highlighting improvements in the areas of FMACO₂ reduction, lowering the critical feature size without damage, and electrostatic discharge (ESD) mitigation. Key aspects of successful CO₂ cryogenic aerosol cleaning include the spray nozzle design, CO₂ liquid purity, and integrated system design. The design of the nozzle directly controls the size, flux, and velocity of the CO₂ snow particles. Methodology and measurements of the solid CO₂ particle size and velocity distributions will be presented, and their responses to various control parameters will be discussed. FMACO₂ mitigation can be achieved only through use of highly purified CO₂ and careful materials selection of the delivery hardware. Recent advances in CO₂ purity will be discussed and data shown. The mask cleaning efficiency by CO₂ cryogenic aerosol and damage control is essentially an optimization of the momentum of the solid CO₂ particles and elimination FMA_CO2. Data on CO₂ tribocharge mitigation, the main cause of ESD, will be presented and application to current technology nodes discussed. The previous damage threshold of 150 nm SRAF structures have been reduced below 60 nm and data will be shown indicating sub-50 nm is possible. The tool capability has been improved from previously doing local cleaning of AFM repair sites to a full mask clean with prospects of replacing certain wet clean steps where phase and transmission are degraded.

Nanoimprint lithography (NIL) is one promising candidate for fabricating a patterned media to be used in the next generation of hard disk drives. It is expected that the pitch, characterizing the feature size of the media will become as small as about 50 nm for discrete-track recording (DTR) in 2010 or 2011. There are two major issues, one is fine groove formation and the other is long e-beam writing time. Writing time is estimated more than one week if we use ZEP520A-resist. To solve these problems, master template fabrication processes using combination of silicon substrate and new CAR were evaluated. As a result, the capability of 1:2 groove and land ratio 50 nm pitch LS pattern formation with new CAR which sensitivity is approximately 2.5 times higher than ZEP520A was shown.

We have developed a new x-ay metrology for profiling surface periodic structure of discrete track patterned media. X-rays irradiate surface of the discrete track media with a shallow glancing angle, which is close to the critical angle of total external reflection of the surface material. The measured x-ray scattering pattern is reflected to the average cross-sectional profile of the grating. Resist pattern of circular discrete track with120 nm-pitch on 65 mmφ magnetic disc is analyzed by the present x-ray metrology. The obtained profile, for example, line width, height of the track and so on are well agreed with that observed by cross-sectional scanning electron microscopy. The wavelength of x-ray that we use is 0.154093 nm and it is enough shorter than the critical length of the grating structure, even when the track width becomes 10 nm or less. Therefore, the resolution of the x-ray metrology will be maintained well that of required in future. In addition, x-ray metrology is able to profiling the cross-sectional structure with nondestructively due to hightransmissivity of x-rays for the materials. Furthermore, the optical parameter of the materials is well established in x-ray region, therefore, it is applicable not only resist patterns, but also real device patterns only with certain physical/optical parameters.

We used electron beam (e-beam) inspection (EBI) systems to inspect nano imprint lithography (NIL) resist wafers with programmed defects. EBI with 10nm pixel sizes has been demonstrated and capability of capturing program defects sized as small as 4nm has been proven. Repeating defects have been captured by the EBI in multiple die inspections to identify the possible mask defects. This study demonstrated the feasibility of EBI as the NIL defect inspection solution of 32nm and beyond.