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Exploring complex 2D layouts for 22nm node using double patterning/double etch approach for trench levels
Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations in 32-nm node standard cell
DRCPlus in a router: automatic elimination of lithography hotspots using 2D pattern detection and correction
Improving copper CMP topography by dummy metal fill co-optimizing electroplating and CMP planarization
Device performances analysis of standard-cells transistors using silicon simulation and build-in device simulation