PROCEEDINGS VOLUME 7641
SPIE ADVANCED LITHOGRAPHY | 21-25 FEBRUARY 2010
Design for Manufacturability through Design-Process Integration IV
Proceedings Volume 7641 is from: Logo
SPIE ADVANCED LITHOGRAPHY
21-25 February 2010
San Jose, California, United States
Front Matter
Proc. SPIE 7641, Front Matter: Volume 7641, 764101 (19 April 2010); doi: 10.1117/12.863953
DFM/DPI Keynote Session
Proc. SPIE 7641, Application of the cost-per-good-die metric for process design co-optimization, 764104 (3 April 2010); doi: 10.1117/12.846556
Proc. SPIE 7641, Taming the final frontier of optical lithography: design for sub-resolution patterning, 764105 (3 April 2010); doi: 10.1117/12.847222
Proc. SPIE 7641, Realizing a 45-nm system on chip in the age of variability, 764106 (11 March 2010); doi: 10.1117/12.848023
Design and Lithography Co-optimization
Proc. SPIE 7641, Joint-optimization for SRAM and logic for 28nm node and below, 764107 (11 March 2010); doi: 10.1117/12.846595
Proc. SPIE 7641, Layout pattern minimization for next-generation technologies, 764108 (3 April 2010); doi: 10.1117/12.846367
Proc. SPIE 7641, 16nm with 193nm immersion lithography and double exposure, 764109 (3 April 2010); doi: 10.1117/12.846677
Proc. SPIE 7641, Exploring complex 2D layouts for 22nm node using double patterning/double etch approach for trench levels, 76410A (3 April 2010); doi: 10.1117/12.848350
Proc. SPIE 7641, 3D physical modeling for patterning process development, 76410B (3 April 2010); doi: 10.1117/12.846637
Designing for Manufacturing Uncertainty
Proc. SPIE 7641, Systematic failure debug and defective pattern extraction for FPGA product yield improvement, 76410C (3 April 2010); doi: 10.1117/12.848185
Proc. SPIE 7641, Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations in 32-nm node standard cell, 76410D (3 April 2010); doi: 10.1117/12.846654
Proc. SPIE 7641, Process sizing aware flow for yield calculation, 76410E (3 April 2010); doi: 10.1117/12.846607
Proc. SPIE 7641, Foundry verification of IP and incoming designs for manufacturing variability, 76410F (3 April 2010); doi: 10.1117/12.848018
Proc. SPIE 7641, 45nm transistor variability study for memory characterization, 76410G (3 April 2010); doi: 10.1117/12.846704
Proc. SPIE 7641, Variability aware timing models at the standard cell level, 76410H (3 April 2010); doi: 10.1117/12.846689
Electrical DFM
Proc. SPIE 7641, Measurement and optimization of electrical process window, 76410J (3 April 2010); doi: 10.1117/12.849066
Proc. SPIE 7641, Development of a design intent extraction flow for mask manufacturing, 76410K (3 April 2010); doi: 10.1117/12.846334
Proc. SPIE 7641, Design intention application to tolerance-based manufacturing system, 76410L (3 April 2010); doi: 10.1117/12.846542
Proc. SPIE 7641, 45nm-generation parameter-specific ring oscillator monitors, 76410N (3 April 2010); doi: 10.1117/12.846719
Layout Verification and Optimization
Proc. SPIE 7641, A kernel-based DFM model for process from layout to wafer, 76410O (3 April 2010); doi: 10.1117/12.844671
Proc. SPIE 7641, Stat-LRC: statistical rules check for variational lithography, 76410P (3 April 2010); doi: 10.1117/12.846606
Proc. SPIE 7641, DRCPlus in a router: automatic elimination of lithography hotspots using 2D pattern detection and correction, 76410Q (3 April 2010); doi: 10.1117/12.846650
Restrictive and Prescriptive Design Methodologies
Proc. SPIE 7641, Demonstrating the benefits of template-based design-technology co-optimization, 76410R (3 April 2010); doi: 10.1117/12.848244
Proc. SPIE 7641, The role of strong phase shift masks in Intel's DFM infrastructure development, 76410S (3 April 2010); doi: 10.1117/12.849022
Proc. SPIE 7641, Decomposition strategies for self-aligned double patterning, 76410T (3 April 2010); doi: 10.1117/12.848387
Proc. SPIE 7641, Towards nanoimprint lithography-aware layout design checking, 76410U (3 April 2010); doi: 10.1117/12.846499
Proc. SPIE 7641, Using a highly accurate self-stop Cu-CMP model in the design flow, 76410V (3 April 2010); doi: 10.1117/12.845653
Proc. SPIE 7641, Improving copper CMP topography by dummy metal fill co-optimizing electroplating and CMP planarization, 76410W (3 April 2010); doi: 10.1117/12.845496
Poster Session
Proc. SPIE 7641, Library-based performance-based OPC, 76410X (3 April 2010); doi: 10.1117/12.846469
Proc. SPIE 7641, Tracking of design related defects hidden by random defectivity in production environment, 76410Y (3 April 2010); doi: 10.1117/12.848763
Proc. SPIE 7641, Device performances analysis of standard-cells transistors using silicon simulation and build-in device simulation, 764110 (3 April 2010); doi: 10.1117/12.845622
Proc. SPIE 7641, Detection of OPC conflict edges through MEEF analysis, 764111 (3 April 2010); doi: 10.1117/12.846673
Proc. SPIE 7641, Practical use of the repeating patterns in mask writing, 764112 (3 April 2010); doi: 10.1117/12.846019
Proc. SPIE 7641, EM calibration based on Post OPC layout analysis, 764113 (3 April 2010); doi: 10.1117/12.846567
Proc. SPIE 7641, OPC on a single desktop: a GPU-based OPC and verification tool for fabs and designers, 764114 (3 April 2010); doi: 10.1117/12.846636
Proc. SPIE 7641, A GPU-based full-chip inverse lithography solution for random patterns, 764115 (3 April 2010); doi: 10.1117/12.846638
Proc. SPIE 7641, Line width roughness effects on device performance: the role of the gate width design, 764116 (3 April 2010); doi: 10.1117/12.853317
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