PROCEEDINGS VOLUME 7974
SPIE ADVANCED LITHOGRAPHY | 27 FEBRUARY - 3 MARCH 2011
Design for Manufacturability through Design-Process Integration V
IN THIS VOLUME

0 Sessions, 36 Papers, 0 Presentations
Front Matter  (1)
Design  (6)
Proceedings Volume 7974 is from: Logo
SPIE ADVANCED LITHOGRAPHY
27 February - 3 March 2011
San Jose, California, United States
Front Matter
Proc. SPIE 7974, Front Matter: Volume 7974, 797401 (27 April 2011); doi: 10.1117/12.897032
Keynote Session
Proc. SPIE 7974, Moore's Law in the innovation era, 797402 (30 March 2011); doi: 10.1117/12.883462
Design
Proc. SPIE 7974, Using templates and connectors for layout pattern minimization in 20nm and below technology nodes, 797405 (4 April 2011); doi: 10.1117/12.879234
Proc. SPIE 7974, Lithographic variation aware design centering for SRAM yield enhancement, 797406 (4 April 2011); doi: 10.1117/12.879503
Proc. SPIE 7974, Multi-selection method for physical design verification applications, 797407 (4 April 2011); doi: 10.1117/12.878463
Proc. SPIE 7974, Applying litho-aware timing analysis to hold time fixing reduces design cycle time and power dissipation, 797408 (4 April 2011); doi: 10.1117/12.878695
Proc. SPIE 7974, Lithography aware design optimization using ILT, 797409 (4 April 2011); doi: 10.1117/12.879393
Proc. SPIE 7974, Is manufacturability with double patterning a burden on designer? Analyses of device and circuit aspects, 79740A (4 April 2011); doi: 10.1117/12.882565
Optical/DFM: Joint Session with Conference 7973
Proc. SPIE 7974, A new fast resist model: the Gaussian LPM, 79740B (4 April 2011); doi: 10.1117/12.881109
Proc. SPIE 7974, Methodology for balancing design and process tradeoffs for deep-subwavelength technologies, 79740C (4 April 2011); doi: 10.1117/12.879537
Proc. SPIE 7974, Double patterning compliant logic design, 79740D (4 April 2011); doi: 10.1117/12.879846
Proc. SPIE 7974, Single exposure contacts are dead. Long live single exposure contacts!, 79740E (4 April 2011); doi: 10.1117/12.879681
Manufacturing
Proc. SPIE 7974, Integrated model-based retargeting and optical proximity correction, 79740F (4 April 2011); doi: 10.1117/12.879531
Proc. SPIE 7974, Validation of process cost effective layout refinement utilizing design intent, 79740G (4 April 2011); doi: 10.1117/12.881485
Proc. SPIE 7974, New double patterning technology for direct contact considering patterning margin and electrical performance, 79740H (4 April 2011); doi: 10.1117/12.879125
Proc. SPIE 7974, Performance and manufacturability trade-offs of pattern minimization for sub-22nm technology nodes, 79740I (4 April 2011); doi: 10.1117/12.879514
Double Patterning
Proc. SPIE 7974, Decomposition-aware standard cell design flows to enable double-patterning technology, 79740K (4 April 2011); doi: 10.1117/12.879643
Proc. SPIE 7974, Layout decomposition of self-aligned double patterning for 2D random logic patterning, 79740L (4 April 2011); doi: 10.1117/12.879500
Proc. SPIE 7974, A state-of-the-art hotspot recognition system for full chip verification with lithographic simulation, 79740M (4 April 2011); doi: 10.1117/12.881596
Poster Session
Proc. SPIE 7974, Extending analog design scaling to sub-wavelength lithography: co-optimization of RET and photomasks, 79740N (4 April 2011); doi: 10.1117/12.877487
Proc. SPIE 7974, Self-aligned double-patterning (SADP) friendly detailed routing, 79740O (4 April 2011); doi: 10.1117/12.877601
Proc. SPIE 7974, Partial least squares-preconditioned importance sampling for fast circuit yield estimation, 79740P (4 April 2011); doi: 10.1117/12.878725
Proc. SPIE 7974, Applications of DBV (design-based verification) for steep ramp-up manufacture, 79740Q (5 April 2011); doi: 10.1117/12.879033
Proc. SPIE 7974, Rerouting and guided-repair strategies to resolve lithography hotspots, 79740R (5 April 2011); doi: 10.1117/12.879237
Proc. SPIE 7974, Accurately predicting copper interconnect topographies in foundry design for manufacturability flows, 79740S (5 April 2011); doi: 10.1117/12.879310
Proc. SPIE 7974, Characterization of the performance variation for regular standard cell with process nonidealities, 79740T (5 April 2011); doi: 10.1117/12.879326
Proc. SPIE 7974, Efficient approach to early detection of lithographic hotspots using machine learning systems and pattern matching, 79740U (5 April 2011); doi: 10.1117/12.879546
Proc. SPIE 7974, Fast process-hotspot detection using compressed patterns, 79740V (5 April 2011); doi: 10.1117/12.879548
Proc. SPIE 7974, In-design DFM CMP flow for block level simulation using 32nm CMP model, 79740W (5 April 2011); doi: 10.1117/12.880899
Proc. SPIE 7974, Hotspot detection using image pattern recognition based on higher-order local auto-correlation, 79740X (5 April 2011); doi: 10.1117/12.881193
Proc. SPIE 7974, The effective etch process proximity correction methodology for improving on chip CD variation in 20 nm node DRAM gate, 79740Y (5 April 2011); doi: 10.1117/12.881472
Proc. SPIE 7974, Defect-aware reticle floorplanning for EUV masks, 79740Z (5 April 2011); doi: 10.1117/12.881667
Proc. SPIE 7974, Standard cell electrical and physical variability analysis based on automatic physical measurement for design-for-manufacturing purposes, 797410 (5 April 2011); doi: 10.1117/12.881841
Proc. SPIE 7974, Aerial image retargeting (AIR): achieving litho-friendly designs, 797411 (5 April 2011); doi: 10.1117/12.882073
Proc. SPIE 7974, Timing variability analysis for layout-dependent-effects in 28nm custom and standard cell-based designs, 797412 (5 April 2011); doi: 10.1117/12.882508
Proc. SPIE 7974, Statistical approach to specify DPT process in terms of patterning and electrical performance of sub-30nm DRAM device, 797413 (5 April 2011); doi: 10.1117/12.869978
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