This PDF file contains the front matter associated with SPIE Proceedings Volume 8081, including the Title Page, Copyright information, Table of Contents, and the Conference Committee listing.

In this study, we investigate what kind of mask blank material is optimum for the resolution enhancement techniques (RET) of leading-edge ArF lithography. The source mask optimization (SMO) is one of the promising RET in 2Xnm-node and it optimizes mask pattern and illumination intensity distribution simultaneously. We combine SMO with the blank material optimization and explore the truly optimized SMO. This study consists of three phases. In the first phase, we evaluate maximum exposure latitude (Max.E.L.) and mask error enhancement factor (MEEF) of fictitious materials that have typical real (n) and imaginary (k) value of refractive index by 3D rigorous simulator as the basic analysis. The simulation result shows that there are two high lithographic performance combinations of n and k values; one is low-n/high-k and the other is high-n/low-k. In the second phase, we select actual blank material that has similar optical parameters with the result of the previous phase. The lithographic performance of the selected material is investigated more precisely. We find that the candidate material has good lithographic performance at the semi-dense pitch. In the final phase, we create a test mask of this candidate blank material and verify simulation result by experimental assessment. The exposures are performed on NA1.30 immersion scanner (Nikon NSR-S610C). The experimental result shows the improvement of Max.E.L. in head to head type pattern. This study will discuss the potential of blank material tuning for the ArF lithography extension.

Recently, the progressive contamination of photomasks has become a major concern for long-term LCD-TFT manufacturing, as it is the cause of significant defects. We have deciphered the chemical structure and growth mechanism of progressive contamination, and have devised an accelerated test procedure which simulates 2 years of TFT processes in order to determine how best to inhibit its growth (UG Series). By using the photomask with a new type of pellicle (UG series), we were able to inhibit the growth of progressive contamination to the extent that no contamination was confirmed on the photomask for approximately two years.

While cleanness of Large Size Photomask (LSPM) is as important as that of LSI masks, the unit price of the pellicle for LSPM is much higher and pellicle removing from and remounting to LSPM is accompanied by troublesome tasks. Considering these facts, an automated pellicle inspection and mounting system that allows large size pellicle to be inspected and mounted onto a photomask automatically under a super clean condition is developed. The system size ranges from G6 to over G10. After picking up a pellicle from a carrier case, jigs remove liner sheet of the pellicle to allow stress free mounting of the pellicle on the LSPM using special chucks. Tow types of inspection heads are developed. One head has a sensitivity of 0.25 μm PSL with 150 seconds inspection time for 6 inch pellicle. Another head has a sensitivity of around 5 μm PSL with 20 minutes inspection time for size of G10. The jig can be flipped along with the Pellicle to allow inspection / blowing of the particles even on the inner side of the pellicle. Rejected pellicles are returned to the carrier case. The pellicle that passes a certain criteria is carried toward the Photomask Holder in the inspection system and mounted on the Photomask in the Holder.

In order to improve sensitivity and line edge roughness (LER) for electron beam (EB) lithography, the positive-type polymer resists with various molecular weights and controlled dispersion were newly synthesized and examined. The synthesized resists have the same composition as ZEP520A (Nippon Zeon). With the low molecular and the narrow dispersion resist, improvements of both the sensitivity and LER are confirmed by obtaining the SEM images of line and space resist patterns exposed by EB writing system at an acceleration voltage of 100 kV. The polymer resist with molecular weight (Mw: 30k) and dispersion (1.4) exhibited 22 nm hp resolution, 20% improved LER and 15 % improved sensitivity compared with original ZEP520A.

To improve lithography performance, resolution enhancement technique (RET) such as source mask optimization (SMO) will be applied to 22 nm node and beyond. We examine if lithography performance is improved by altering mask 3D topography. In this paper, we report that we have confirmed what topography is effective for lithography performance improvement in the dense region of 22nm technology node. Since shadowing effect is strong at the dense region, we focus on sidewall angle that decreases shadowing effect. As a basic analysis, we evaluate maximum exposure latitude (EL) and mask error enhancement factor (MEEF) of mask 3D topographic patterns that have various sidewall angles by 3D rigorous simulator. This result shows the increasing of maximum exposure latitude when changing sidewall angle. As a next step, we fabricate a test mask which has optimized sidewall angle and the exposure is performed on NA1.30 immersion scanner (Nikon NSR-S610C). Then we compare wafer printing results and simulation results. These results induce that the optimization of mask 3D topography has a potential to improve lithographic performance.

A new method to describe the resist surface charging effect more accurately is proposed. In our previous work, we handled only the static portion of the surface charging and it was applicable only to a limited situation. The scope of this paper is to add a new model to handle the dynamic, discharging behavior on top of the existing static model to make the whole charging model closer to what is really happening on the plate during the exposure. With the new model, the correction accuracy has been improved not only for the equilibrium state but also for the state when the tool is dynamically writing the main pattern. We conclude that our Charging Effect Correction (CEC) was advanced by this new model to become completely production ready.

We are evaluating the resolution capability of character projection (CP) exposure method using a Multi Colum Cell Proof of Concept (MCC-POC) tool. Resolving of 14nm half pitch (HP) 1:1 line and space (LS) patterns are confirmed with fine openings of a DNP fabricated CP mask for 10:1 de-magnification ratio. CP exposure has been proven to exhibit high resolution capabilities even under the most challenging optimization conditions that are required for throughput enhancement. As a result of evaluating the resolution capability of CP technology, it became apparent that the CP technology has strong potentials to meet future challenges in two areas. One is where an increased number of CP with variable illumination technology gives a higher throughput which has been the main objective behind the development of this technology, and the other is to achieve higher resolution capability that is one of the strengths of CP exposure method. We also evaluated the resolution on Quartz mask blanks instead of Si wafers and obtained 18nm HP 1:1 resolution with CP exposure.

Through the four years of study in Association of Super-Advanced Electronics Technologies (ASET) on reducing mask manufacturing Turn Around Time (TAT) and cost, we have been able to establish a technology to improve the efficiency of the review process by applying a printability verification function that utilizes computational lithography simulations to analyze defects detected by a high-resolution mask inspection system. With the advent of Source-Mask Optimization (SMO) and other technologies that extend the life of existing optical lithography, it is becoming extremely difficult to judge a defect only by the shape of a mask pattern, while avoiding pseudo-defects. Thus, printability verification is indispensable for filtering out nuisance defects from high-resolution mask inspection results. When using computational lithography simulations to verify printability with high precision, the image captured by the inspection system must be prepared with extensive care. However, for practical applications, this preparation process needs to be simplified. In addition, utilizing Mask Data Rank (MDR) to vary the defect detection sensitivity according to the patterns is also useful for simultaneously inspecting minute patterns and avoiding pseudo-defects. Combining these two technologies, we believe practical mask inspection for next generation lithography is achievable. We have been improving the estimation accuracy of the printability verification function through discussion with several customers and evaluation of their masks. In this report, we will describe the progress of these practical mask verification functions developed through customers' evaluations.

A new metrology method for CD-SEM has been developed to measure the side wall angle of a pattern on photomask. The height and edge width of pattern can be measured by the analysis of the signal intensity profile of each channel from multiple detectors in CD-SEM. The edge width is measured by the peak width of the signal intensity profile. But it is not possible to measure the accurate edge width of the pattern, if the edge width is smaller than the primary electron beam diameter. Using four detectors, the edge width can be measured by the peak width which appears on the subtracting signal profile of two detectors in opposition to each other. Therefore, the side wall angle can be calculated if the pattern height is known. The shadow of the side wall appears in the signal profile from the detector of the opposite side of the side wall. Furthermore, we found that there was the proportional relation between pattern height and the shadow length of the signal on one side. This paper describes a method of measuring the side wall width of a pattern and experimental results of the side wall angle measurements.

EUV is considered as the most promising candidate for manufacturing advanced semiconductors at the 32nm HP technology generation and beyond. It has been demonstrated that the ASML TWINSCAN NXE:3100 is able to print 27nm lines and spaces and 32nm contact holes with NA0.25. Moving forward, higher NA EUV system such as the ASML TWINSCAN NXE:3300B can generate a higher contrast aerial image due to improved diffractive order collection efficiency and is expected to achieve a greater percentage of under-exposure or dose reduction via mask biasing. In this work, we study by simulation the benefit of EUV high NA imaging in the MRC (Mask Rule Check) trade-offs required to achieve the viable manufacturing solutions for two device application scenarios: 6T-SRAM contact layer for the logic 14 nm technology node, and 32nm half pitch NAND Flash contact layer. The 3D mask effects versus Kirchhoff mask for these two applications are also investigated.

The computer cost for mask data processing grows increasingly more expensive every year. However the Graphics Processing Unit (GPU) has evolved dramatically. The GPU which originally was used exclusively for digital image processing has been used in many fields of numerical analysis. We developed mask data processing techniques using GPUs together with distributed processing that allows reduced computer costs as opposed to a distributed processing system using just CPUs. Generally, for best application performance, it is important to reduce conditional branch instructions, to minimize data transfer between the CPU host and the GPU device, and to optimize memory access patterns in the GPU. Hence, in our optical proximity correction (OPC), the light intensity calculation step, that is the most time consuming part of this OPC, is optimized for GPU implementation and the other inefficient steps for GPU are processed by CPUs . Moreover, by fracturing input data and balancing a computational road for each CPU, we have put the powerful distributed computing into practice. Furthermore we have investigated not only the improvement of software performance but also how to best balance computer cost and speed, and we have derived a combination of the CPU hosts and the GPU devices to maximize the processing performance that takes computer cost into account . We have also developed a recovery function that continues OPC processing even if a GPU breaks down during mask data processing for a production. By using the GPUs and distributed processing, we have developed a mask data processing system which reduces computer cost and has high reliability.

For actinic mask inspection and metrology, we have developed a coherent EUV scatterometry microscope (CSM) at NewSUBARU of a synchrotron radiation facility. The CSM is composed of φ5-mm pinhole, turning and focusing multilayer mirrors, a test EUV mask and a back-illuminated CCD camera. Thus this system is lens-less system, records diffraction EUV light from a mask pattern, which is exposed with coherent EUV light. The CSM inspects defect on the EUV mask by the coherent-diffraction-imaging method. Aerial images of periodic and aperiodic patterns on the EUV mask were well reconstructed by the iterative calculation. Since the CSM data include only the diffraction intensity, the missing phase information is reconstructed. A defect with 10-nm width was well inspected. The CSM also evaluates critical dimension (CD) of the mask patterns by diffraction intensities. The mask is illuminated with six-degree angle of the incidence, which equals to the EUV lithography scanners. The test EUV mask of 6025 glass substrate has line-and-space (L/S) patterns of 22-nm nodes. Absorber thickness is about 70 nm. The CSM result is well corresponding with the CD-SEM result at whole mask area. And, high repeatability of 0.3 nm (3φ) is achieved.

The increasing demands for registration metrology for repeatability, accuracy, and resolution in order to be able to perform measurements in the active area on production features have prompted the development of PROVE^TM, the nextgeneration registration metrology tool that utilizes 193nm illumination and a metrology stage that is actively controlled in all six degrees of freedom. PROVE^TM addresses full in-die capability for double patterning lithography and sophisticated inverse-lithography schemes. Innovative approaches for image analysis, such as 2D correlation, have been developed to achieve this demanding goal. In order to take full advantage of the PROVE^TM resolution and measurement capabilities, a direct link to the mask data preparation for job automation and marker identification is inevitable. This paper describes an integrated solution using Synopsys' CATS^R for extracting and preparing tool-specific job input data for PROVE. In addition to the standard marking functionalities, CATS^R supports the 2D correlation method by providing reference clips in OASIS.MASK format.

Techniques for identifying and mitigating effects of process variation on the electrical performance of integrated circuits are described. These results are from multi-discipline, collaborative university-industry research and emphasize anticipating sources of variation up-stream early in the circuit design phase. The lithography physics research includes design and testing electronic monitors in silicon at 45 nm and fast-CAD tools to identify systematic variations for entire chip layouts. The device research includes the use of a spacer (sidewall transfer) gate fabrication process to suppress random variability components. The Design-for-Manufacturing research includes double pattern decomposition in the presence of bimodal CD behavior, process-aware reticle inspection, tool-aware dose trade-off between leakage and speed, the extension of timing analysis methodology to capture across process-window effects and electrical processwindow characterization.

Process models have been in use for performing proximity corrections to designs for placement on lithography masks for a number of years. In order for these models to be used they must provide an adequate representation of the process while also allowing the corrections themselves to be performed in a reasonable computational time. In what is becoming standard Optical Proximity Correction (OPC), the models used have a largely physical optical model combined with a largely empirical resist model. Normally, wafer data is collected and fit to a model form that is found to be suitable through experience. Certain process variables are considered carefully in the calibration process-such as exposure dose and defocus - while other variables-such film thickness and optical parameter variations are often not considered. As the semiconductor industry continues to march toward smaller and smaller dimensions-with smaller tolerance to errorwe must consider the importance of those process variations. In the present work we describe the results of experiments performed in simulations to examine the importance of many of those process variables which are often regarded as fixed. We show examples of the relative importance of the different variables.

In this paper, we provide new yield-aware mask strategies to mitigate emerging variability and defectivity challenges. To address variability, we analyze CD variability with respect to reticle size, and its impact on parametric yield. With a cost model that incorporates mask, wafer, and processing cost considering throughput, yield, and manufacturing volume, we assess various reticle strategies (e.g., single layer reticle (SLR), multiple layer reticle (MLR), and small and large size) considering field-size dependent parametric yield. To address defectivity, we compare parametric yield due to EUV mask blank defects for various reticle strategies in conjunction with reticle floorplan optimizations such as shifting of the mask pattern within a mask blank to avoid defects being superposed by performance-critical patterns of a design.

Based on an acceptable wafer critical dimension (CD) variation that takes device performance into consideration, we presented a methodology for deriving an acceptable mask defect size using defect printability [1]-[3]. The defect printability is measurable by Aerial Image Measurement System (AIMS^TM) and simulated by lithography simulation without exposure. However, the defect printability of these tools is not always the same as the actual one. Therefore, the accuracy of these tools is confirmed by fabricating the programmed defect mask and exposing this mask on wafer. Advanced Binary Film (ABF) photomask has recently been studied as a substitute for the conventional MoSi phase shift mask. For ABF photomask fabrication, mask performance for process and guarantee for mask defects by repair and inspection are important. With regard to the mask performance, the ABF photomask has high performance in terms of resolution of pattern making, placement accuracy, and cleaning durability [4]. With regard to the guarantee for mask defects, it has already been confirmed that the defect on the ABF photomask is repairable for both clear and opaque defects. However, it has not been evaluated for inspection yet. Therefore, it is necessary to evaluate the defect printability, to derive the acceptable mask defect size, and to confirm the sensitivity of mask inspection tool. In this paper, the defect printability of the ABF photomask was investigated by the following process. Firstly, for opaque and clear defects, sizes and locations were designed as parameters for memory cell patterns. Secondly, the ABF programmed defect mask was fabricated and exposed. Thirdly, mask defect sizes on the ABF programmed defect mask and line CD variations on the exposed wafer were measured with CD-SEM. Finally, the defect printability was evaluated by comparing the correlation between the mask defect sizes and the wafer line CD variations with that of the AIMSTM and the lithography simulation. From these results, the defect printability of AIMS^TM was almost the same as the actual one. On the other hand, the defect printability of the lithography simulation was relaxed from the actual one for the isolated defect types for both clear and opaque defects, though the defect printability for the edge defect types was almost the same. Additionally, the acceptable mask defect size based on the actual defect printability was derived and the sensitivity of the mask inspection tool (NPI-7000) was evaluated. Consequently, the sensitivity of the NPI-7000 was detectable for the derived acceptable mask defect size. Therefore, it was confirmed that the ABF photomask could be guaranteed for mask defects.

We analyzed the lithographic performance of a double patterning technology (DPT) with resist freeze (LFLE) process for printing dense contact holes (CH). For the first time, we quantified the contribution of the substrate - frozen resist and topography effects. The impact on image contrast, and NILS was studied through-pitch. In comparing to the case of a uniform L/S, the image through-pitch performance is degraded in LFLE CH. This is resulted from diffraction by the underlying topography and materials. The process steps (between first-and-second Litho) cause additional challenges in the fabrication of CHs using DPT. Current inspection of the process effects only observes the reflected signal for position alignment. We have introduced simulations of a phase change in polarized signal (ellipsometry) after first and second lithography steps for suggesting a new methodology for detection and validation of topography changes in DPT flow. In DPT the first Litho result is fabricated in substrate, so the analysis of ellipsometry signal can be applied to sensitively detect correlations between two steps. The spectroscopic ellipsometry simulation results were shown; α and β parameters demonstrate the sensitivity w.r.t. substrate topography, by changing the incident optical direction from x-z to y-z plane. This represents the correlation between parameters observed by respective Litho steps of perpendicular orientation. Furthermore, ellipsometry signal was used to optimize the "frozen" resist n and k values w.r.t aerial image performance, which can be fed back to DPT design. Concluding, the information obtained by ellipsometry is useful to characterize substrate topography in DPT design.

A persistent problem in verification flows is to eliminate waivers defined as patterns that are known to be safe on silicon even though they are flagged by the verification recipes. The difficulty of the problem stems from the complexity of these patterns, and thus, using a standard verification language to describe them becomes very tedious and can deliver unexpected results. In addition, these patterns have a dynamic nature, hence, updating all production verification recipes to waive these non critical patterns becomes more time consuming. In this work, we are presenting a new method to eliminate waivers directly after verification recipes have been executed, where a new rule file will be generated automatically based on the type of errors under investigation. The core of the method is based on pattern matching to compare generated errors from verifications runs with a library of pattern waivers. This flow will eliminate the need to edit any production recipe, and complicated coding will not be required. Finally, this flow is compatible with most of the technology nodes.

Depth of focus has always been of great concern in lightography as a result of processes optimized for specific feature dimensions and pitches. Insertion of sub-resolution assist features (SRAFs) or scatter bars ois a common technique used to equalize DOF through the variety of geometries used in a design. SRAFs can be inserted into the layout by a variety of means ranging from methods based on simple rule-tables to full-fledged layout simulations. Various tools are available from electronic design automation (EDA) vendors that are capable of placing srafs based on elaborate simulations of the design layout, but, a tool that can determine rule-table is not available. Each resolution enhancement technique (RET) engineer has his/her own methodology of extracting rules based on simulation of a large layout with design and sraf rule variations. Significant computational resources are required to carry-out these extensive simulations affecting the time required to formulate the rule table and restricting the variation that can be considered for the simulations. In this paper, we discuss an efficient method which overcomes this problem by searching in the design and dsraf rule domain to obtain a comprehensive set of sraf rules, thereby resulting in a better rule-set by using significantly lesser computational resources.

Using Model-Based Mask Data Preparation (MB-MDP) complex masks with complex sub-resolution assist features (SRAFs) can be written in practical write times with today's leading-edge production VSB machines by allowing overlapping VSB shots. This simulation-based approach reduces shot count by taking advantage of the added flexibility in being able to overlap shots. The freedom to overlap shots, it turns out, also increases mask fidelity, CDU on the mask, and CDU on the wafer by writing sub-100nm mask features more accurately, and with better dose margin. This paper describes how overlapping shots enhance mask and wafer quality for various sub-100nm features on ArF masks. In addition, this paper describes how EUV mask accuracy can be enhanced uniquely by allowing overlapping shots.

As the lithography roadmap unfolds on its path towards ever smaller geometries, the pattern placement (Registration) requirements are increasing dramatically. This trend is further enhanced by anticipating the impact of innovative process solutions as double patterning where mask to mask overlay on the wafer is heavily influenced by mask registration error. In previous work1 a laser based registration control (RegC) process in the mask periphery (outside the exposure field) was presented. While providing a fast and effective improvement of registration, the limitation of writing with the laser outside of the active area limits the registration improvement to ~25%. The periphery process can be applied after the pattern generation or after pellicle mounting and allows fine tuning of the mask registration. In this work we will show registration correction results where the full mask area is being processed. While processing inside the exposure field it is required to maintain the CD Uniformity (CDU) neutral .In order to maintain the CDU neutral several different laser writing steps are utilized. A special algorithm and software were developed in order to compute the process steps required for maintaining the CDU neutral from one side while correcting for mask placement errors on the other side. By applying the correction process inside the active area improvements of up to 50% of the 3S registration and values as low as 3 nm 3S after scale and ortho correction have been achieved. These registration improvements have been achieved while maintaining the CDU signature of the mask as measured by areal imaging with WLCDTM (Wafer Level CD Metrology tool from Carl Zeiss SMS).

193nm binary photomasks are still used in the semiconductor industry for the lithography of some critical layers for the nodes 90nm and 65nm, with high volumes and over long period. These 193nm binary masks seem to be well-known but recent studies have shown surprising degrading effects, like Electric Field induced chromium Migration (EFM) [1] or chromium migration ^{[2] [3]} . Phase shift Masks (PSM) or Opaque MoSi On Glass (OMOG) might not be concerned by these effects ^{[4] [6]} under certain conditions. In this paper, we will focus our study on two layers gate and metal lines. We will detail the effects of mask aging, with SEM top view pictures revealing a degraded chromium edge profile and TEM chemical analyses demonstrating the growth of a chromium oxide on the sidewall. SEMCD measurements after volume production indicated a modified CD with respect to initial CD data after manufacture. A regression analysis of these CD measurements shows a radial effect, a die effect and an isolated-dense effect. Mask cleaning effectiveness has also been investigated, with sulphate or ozone cleans, to recover the mask quality in terms of CD. In complement, wafer intrafield CD measurements have been performed on the most sensitive structure to monitor the evolution of the aging effect on mask CD uniformity. Mask CD drift have been correlated with exposure dose drift and isolated-dense bias CD drift on wafers. In the end, we will try to propose a physical explanation of this aging phenomenon and a solution to prevent from it occurring.

Dimensions on mask continue to shrink to keep up with the ITRS roadmap. This has implications on the material of choice for the blanks. For example, the new binary OMOG stack (Opaque MOSi on Glass) was successfully introduced to meet the mask specifications at the 32nm technology node. Obviously 193-nm optical lithography will be further used in production at even higher NA and lower k1 emphasizing, for example, the impact on wafer of any electromagnetic field migration effects. Indeed, long term radiation damage inducing CD growth and consequently, device yield loss, has already been reported [1, 2]. This mechanism, known as Electric Field induced Migration of chrome (EMF) often shortens the mask's lifetime. Here, a study was conducted to investigate the impact of intensive ArF scanner exposure both on final wafer and mask performances. The Si printed wafers measured with top-down CD-SEM were characterized with respect to CD uniformity, linearity, Sub Resolution Assist Feature (SRAF) printability through process window, MEEF, DOF, and OPC accuracy. The data was also correlated to advanced mask inspection results (e.g. AIMSTM) taken at the same location. More precisely, this work follows a preliminary study [1] which pointed out that OMOG is less sensitive to radiation than standard COG (Chrome On Glass). And, in this paper, we report on results obtained at higher energy to determine the ultimate lifetime of OMOG masks.