PROCEEDINGS VOLUME 8327
SPIE ADVANCED LITHOGRAPHY | 12-16 FEBRUARY 2012
Design for Manufacturability through Design-Process Integration VI
Proceedings Volume 8327 is from: Logo
SPIE ADVANCED LITHOGRAPHY
12-16 February 2012
San Jose, California, United States
Frontmatter
Proc. SPIE 8327, Front Matter: Volume 8327, 832701 (17 April 2012); doi: 10.1117/12.928432
Keynote Session
Proc. SPIE 8327, Implications of triple patterning for 14nm node design and patterning, 832703 (7 March 2012); doi: 10.1117/12.920028
DFDP: Design for Double Patterning
Proc. SPIE 8327, Layout optimization through robust pattern learning and prediction in SADP gridded designs, 832705 (15 March 2012); doi: 10.1117/12.916583
Proc. SPIE 8327, Self-aligned double patterning (SADP) compliant design flow, 832706 (15 March 2012); doi: 10.1117/12.917775
Proc. SPIE 8327, Design friendly double patterning, 832707 (15 March 2012); doi: 10.1117/12.915713
Proc. SPIE 8327, Pattern matching for double patterning technology-compliant physical design flows, 832708 (15 March 2012); doi: 10.1117/12.916581
Design Rules and Routing
Proc. SPIE 8327, Design-of-experiments based design rule optimization, 832709 (15 March 2012); doi: 10.1117/12.918067
Proc. SPIE 8327, Fully integrated litho aware PnR design solution, 83270A (15 March 2012); doi: 10.1117/12.916138
Proc. SPIE 8327, Replacing design rules in the VLSI design cycle, 83270B (15 March 2012); doi: 10.1117/12.916428
Proc. SPIE 8327, Smart double-cut via insertion flow with dynamic design-rules compliance for fast new technology adoption, 83270C (15 March 2012); doi: 10.1117/12.915796
Proc. SPIE 8327, Local loops for robust inter-layer routing at sub-20 nm nodes, 83270D (15 March 2012); doi: 10.1117/12.916290
Design Implementation and Variability
Proc. SPIE 8327, A primer of physical design for lithographers, 83270E (15 March 2012); doi: 10.1117/12.917447
Proc. SPIE 8327, Analysis, quantification, and mitigation of electrical variability due to layout dependent effects in SOC designs, 83270F (15 March 2012); doi: 10.1117/12.916458
Proc. SPIE 8327, Design level variability analysis and parametric yield improvement methodology, 83270H (15 March 2012); doi: 10.1117/12.916153
Proc. SPIE 8327, Analysis of layout-dependent context effects on timing and leakage in 28nm, 83270I (15 March 2012); doi: 10.1117/12.916208
Proc. SPIE 8327, Variability aware compact model characterization for statistical circuit design optimization, 83270J (15 March 2012); doi: 10.1117/12.916512
Joint Session with Conference 8326
Proc. SPIE 8327, Design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14 nm node, 83270K (15 March 2012); doi: 10.1117/12.916104
Proc. SPIE 8327, A novel methodology for triple/multiple-patterning layout decomposition, 83270M (15 March 2012); doi: 10.1117/12.916636
Proc. SPIE 8327, Overlay, decomposition and synthesis methodology for hybrid self-aligned triple and negative-tone double patterning, 83270N (15 March 2012); doi: 10.1117/12.916495
Proc. SPIE 8327, Computational lithography work flows and design rule exploration automation, 83270O (15 March 2012); doi: 10.1117/12.918057
Hotspots, CMP, and Fill
Proc. SPIE 8327, Thickness-aware LFD for the hotspot detection induced by topology, 83270P (15 March 2012); doi: 10.1117/12.917998
Proc. SPIE 8327, The complexity of fill at 28nm and beyond, 83270Q (15 March 2012); doi: 10.1117/12.916011
Proc. SPIE 8327, In-design process hotspot repair using pattern matching, 83270S (15 March 2012); doi: 10.1117/12.916199
Proc. SPIE 8327, Clean pattern matching for full chip verification, 83270T (15 March 2012); doi: 10.1117/12.916316
Poster Session
Proc. SPIE 8327, Framework for identifying recommended rules and DFM scoring model to improve manufacturability of sub-20nm layout design, 83270U (15 March 2012); doi: 10.1117/12.916288
Proc. SPIE 8327, Self-aligned double and quadruple patterning layout principle, 83270V (15 March 2012); doi: 10.1117/12.916678
Proc. SPIE 8327, In-design hierarchical DFM closure for DFM-clean IP, 83270W (15 March 2012); doi: 10.1117/12.916219
Proc. SPIE 8327, Automated yield enhancements implementation on full 28nm chip: challenges and statistics, 83270X (15 March 2012); doi: 10.1117/12.915920
Proc. SPIE 8327, A study of pattern variability for device performance, 83270Y (15 March 2012); doi: 10.1117/12.915934
Proc. SPIE 8327, Intra-cell process variability and compact modeling of LWR effects: from self-aligned multiple patterning to multiple-gate MOSFETs, 83270Z (15 March 2012); doi: 10.1117/12.916503
Proc. SPIE 8327, Consideration of correlativity between litho and etching shape, 832710 (15 March 2012); doi: 10.1117/12.915785
Proc. SPIE 8327, Advanced techniques for design assembly and characterization for the 14nm node with LFD using a black box API, 832711 (15 March 2012); doi: 10.1117/12.916431
Proc. SPIE 8327, Fast optical proximity correction with timing optimization ready standard cells, 832714 (15 March 2012); doi: 10.1117/12.916124
Proc. SPIE 8327, Electrical design for manufacturability and lithography and stress variability hotspot detection flows at 28nmn, 832715 (15 March 2012); doi: 10.1117/12.916742
Proc. SPIE 8327, Yield impacting systematic defects search and management, 832716 (15 March 2012); doi: 10.1117/12.918068
Proc. SPIE 8327, Model-based searching method to find the integrated critical failure on the wafer, 832717 (15 March 2012); doi: 10.1117/12.917881
Proc. SPIE 8327, A scoring methodology for quantitatively evaluating the quality of double patterning technology-compliant layouts, 832718 (15 March 2012); doi: 10.1117/12.916494
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