This PDF file contains the front matter associated with SPIE Proceedings Volume 8681, including the Title Page, Copyright Information, Table of Contents, and the Conference Committee listing.

Variations in key device parameters such as gate width, fin height, and storage node aspect ratio can lead to performance variations device to device and within die. Extreme excursions can result in yield loss. Metrology and process control are enablers to detect and keep these variations to within certain bounds. As the features of devices continue to shrink, the allowable tolerances for critical dimensions and overlay errors likewise must shrink, in turn forcing the metrology budgets to shrink in step. At the same time, more data is required per wafer to generate higher order analyses while at the same time greater productivity in terms of silicon area processed in unit time is needed to keep the economics favorable. It is essential we develop the strategies needed for metrology in times of shrinking budgets.

Metrology tools are increasingly challenged by the continuing decrease in the device dimensions, combined with complex disruptive materials and architectures. These demands are not being met appropriately by existing/forthcoming metrology techniques individually. Hybrid Metrology (HM) – the practice to combine measurements from multiple toolset types in order to enable or improve the measurement of one or more critical parameters – is being incorporated by the industry to resolve these challenges. Continuing our previous work we now take the HM from the lab into the fab. This paper presents the first-in-industry implementation of HM within a High Volume Manufacturing (HVM) environment. Advanced 3D applications are the first to use HM: 20nm Contact etch and 14nm FinFET poly etch. The concept and main components of this Phase-1 Host-based implementation are discussed. We show examples of communication protocols/standards that have been specially constructed for HM for sharing data between the metrology tools and fab host in GLOBALFOUNDRIES, as well as the HM recipe setup and HVM results. Finally we discuss our vision and phased progression/roadmap for Phase-2 HM implementation to fully reap the benefits of hybridization.

Aggressive on-product overlay requirements in advanced nodes are setting a superior challenge for the semiconductor industry. This forces the industry to look beyond the traditional way-of-working and invest in several new technologies. Integrated metrology², in-chip overlay control, advanced sampling and process correction-mechanism (using the highest order of correction possible with scanner interface today), are a few of such technologies considered in this publication.

The continuous need for lithography overlay performance improvement is a key point for advanced integrated circuit manufacturing. Overlay control is more and more challenging in the 2x nm process nodes regarding functionality margin of the chip and tool capability. Transistor architecture rules which are set, confirm poly to contact space as the most critical one for 28nm technology node. Critical Dimension variability of these layers, even with best in class process stability, in addition to design constraint lead to on product overlay specifications of around 7nm. In order to ensure that the target is met in production environment and to identify potential ways for improvement, identification of the contributors to overlay errors is essential. We have introduced a novel budget breakdown methodology using both bottom-up and top-down overlay data. For the bottom up part, we have performed extensive testing with very high sampling scheme so as to quantify the main effects. In-line overlay metrology data has been used for top down approach to verify the overall performance in production. In this paper we focused on the 28nm contact to gate overlay in a FDSOI process. The initial inconsistency between bottom up and top down results led us to further exploration of the root cause of these inconsistencies. We have been able to highlight key figures to focus on, like reticle heating, wafer table contamination and etch processing effects. Finally, we conclude on 7nm overlay target achievement feasibility in high volume manufacturing environment.

To fulfil advanced process control requirements for 1X node production, the semiconductor industry must cope with multiple parallel metrology requirements such as resolution, precision and accuracy enhancement in all directions to answer to new 3D integrated circuit fabrication methods. At the 1D and 2D levels, CDSEM and Scatterometry techniques are the workhorse techniques for production and process control. However, for process control of 3D devices and high resolution patterning such as direct self-assembly lithography, reference metrology is necessary to maintain a global process control uncertainty that is sufficient for production standards. CD-SEM and Scatterometry have intrinsic limitations that limit their utility for these cases, and new characterization methods are needed. Among the industrial reference techniques currently available, TEM and CD-AFM are generally employed to address this issues but both of these techniques have their own limitations for 1X node production. Nevertheless, they are also very useful for engineers to calibrate production CD metrology techniques and for more accurate process window and process development definition at the R&D level. Thus, there is a critical need to develop new technologies that build upon these capabilities while overcoming the limitations.

The automated metrology capabilities of a STEM using a commercially available 22nm microprocessor were evaluated. Artifact-free TEM samples with a thickness of 10-15nm were prepared from inverter structures at various locations within an SRAM array. Static and dynamic precision measurements made on fin and gate stack features show sub-nm precision, suggesting that fully automated STEM metrology on finFET devices is capable of supporting finFET production. This paper also discusses sample preparation, automated data acquisition and data analysis, as well as the throughput benefits that arise from hardware connectivity between the sample prep and data acquisition tools. Simultaneous STEM imaging and compositional analysis is also briefly discussed.

The Critical Dimension Scanning Electron Microscope (CDSEM) is the traditional workhorse solution for inline process control. Measurements are extracted from top-down images based on secondary electron collection while scanning the specimen. Secondary electrons holding majority of detection yield. These images provide more on the structural information of the specimen surface and less in terms of material contrast. In some cases there is too much structural information in the image which can irritate the measurement, in other cases small but important differences between various material compounds cannot be detected as images are limited by contrast information and resolution of primary scanning beam. Furthermore, accuracy in secondary electron based metrology is limited by charging. To gather the exact required information for certain material compound as needed, a technique, known from material analytic SEM´s has been introduced for inline CDSEM analysis and process control: Low Loss Back Scattered Electron Imaging (LL-BSE). The key at LL-BSE imaging is the collection of only the back scattered electrons (BSE) from outermost specimen surface which undergo the least amount possible of energy loss in the process of image generation following impact of the material by a primary beam. In LL-BSE very good and measurable material distinction and sensitivity, even for very low density material compounds can be achieved. This paper presents new methods for faster process development cycle, at reduced cost, based on LL-BSE mass data mining instead of sending wafers for destructive material analysis.

Traditional control of critical dimensions (CD) on photolithographic masks considers the CD average and a measure for the CD variation such as the CD range or the standard deviation. Also systematic CD deviations from the mean such as CD signatures are subject to the control. These measures are valid for mask quality verification as long as patterns across a mask exhibit only size variations and no shape variation. The issue of shape variations becomes especially important in the context of contact holes on EUV masks. For EUV masks the CD error budget is much smaller than for standard optical masks. This means that small deviations from the contact shape can impact EUV waver prints in the sense that contact shape deformations induce asymmetric bridging phenomena. In this paper we present a detailed study of contact shape variations based on regular product data. Two data sets are analyzed: 1) contacts of varying target size and 2) a regularly spaced field of contacts. Here, the methods of statistical shape analysis are used to analyze CD SEM generated contour data. We demonstrate that contacts on photolithographic masks do not only show size variations but exhibit also pronounced nontrivial shape variations. In our data sets we find pronounced shape variations which can be interpreted as asymmetrical shape squeezing and contact rounding. Thus we demonstrate the limitations of classic CD measures for describing the feature variations on masks. Furthermore we show how the methods of statistical shape analysis can be used for quantifying the contour variations thus paving the way to a new understanding of mask linearity and its specification.

We have succeeded in quantifying changes in 2D pattern shape, which are induced by exposure condition and Optical Proximity Correction (OPC), from CD-SEM image. In the current lithography technology, micro patterns which are close to resolution limit are printed on wafer by fully utilizing aggressive OPC technology. In such lithography technology, controlling the shape of printed patterns is extremely difficult. In order to control such difficult patterning process, a demand to precisely quantify the pattern shape of 2D patterns is significantly growing. SEM images captured by CD-SEM are used mainly for the measurement of one dimensional size such as line width and contact hole diameter. It has been said not easy to measure shape variation of 2D patterns such as corner and line end from SEM images. However, we have succeeded in quantifying pattern shape of 2D pattern by utilizing Advanced SEM contouring technology which is combined with CD-gap-free contouring technology [1] and Fine SEM Edge (FSE) technology [2]. By this, we could quantitatively measure shape variation which are induced by exposure condition variability and/ or OPC, which used to be considered difficult to quantify. For the verification of this new measurement technology, wafers on which printed 2D patterns that are exposed in different conditions and with varied SRAF changed in size and position are prepared. The 2D patterns are measured by CD-SEM and SEM images of the 2D patterns are taken. To the SEM images of the 2D patterns, this new measurement technology is applied to quantitatively analyze how the expose condition and SRAF variation affect the printed 2D pattern shape. In this paper, the results of above experiments are reported.

The impact on yield loss due to systematic defect which remains after Optical Proximity Correction (OPC) modeling has increased, and achieving an acceptable yield has become more difficult in the leading technology beyond 20 nm node production. Furthermore Process-Window has become narrow because of the complexity of IC design and less process margin. In the past, the systematic defects have been inspected by human-eyes. However the judgment by human-eyes is sometime unstable and not accurate. Moreover an enormous amount of time and labor will have to be expended on the one-by-one judgment for several thousands of hot-spot defects. In order to overcome these difficulties and improve the yield and manufacturability, the automated system, which can quantify the shape difference with high accuracy and speed, is needed. Inspection points could be increased for getting higher yield, if the automated system achieves our goal. Defect Window Analysis (DWA) system by using high-precision-contour extraction from SEM image on real silicon and quantifying method which can calculate the difference between defect pattern and non-defect pattern automatically, which was developed by Hitachi High-Technologies, has been applied to the defect judgment instead of the judgment by human-eyes. The DWA result which describes process behavior might be feedback to design or OPC or mask. This new methodology and evaluation results will be presented in detail in this paper.

Overlay control is becoming increasingly more important with the scaling of technology. It has become even more critical and more challenging with the move toward multiple-patterning lithography, where overlay translates into CD variability. Design rules and overlay have strong interaction and can have a considerable impact on the design area, yield, and performance. This paper offers a framework to study this interaction and evaluate the overall design impact of rules, overlay characteristics, and overlay control options. The framework can also be used for designing informed, design-aware overlay metrology and control strategies. In this work, The framework was used to explore the design impact of LELE doublepatterning rules and poly-line end extension rule defined between poly and active layer for different overlay characteristics (i.e., within-field vs. field-to-field overlay) and different overlay models at the 14nm node. Interesting conclusions can be drawn from our results. For example, one result shows that increasing the minimum mask-overlap length by 1nm would allow the use of a third-order wafer/sixth-order field-level overlay model instead of a sixth-order wafer/sixth-order field-level model with negligible impact on design.

Metrology measurement and defect inspection steps in routes are more pervasive than many people realize and the number continues to grow. Digging deeper, it turns out that E-beam metrology and defect inspection tools typically occupy the most overall steps and therefore are extremely critical tools for semiconductor development and manufacturing. The Critical Dimension Scanning Electron Microscope (CDSEM) is an E-beam tool responsible for image-based structural metrology measurements while the E-beam review (EBR) and E-beam inspection (EBI) tools are responsible for defect inspection. The CDSEM faces significant future challenges in a world where device architectures are changing (as with the FinFET device), increasing the need for more structural measurement parameters such as sidewall angle, height and undercut, than the CDSEM can deliver. These applications are now migrating to scattering-based tools, also referred to as model- or computational-based structural metrology techniques. We explore the history of the CDSEM, the key fundamental limits (primarily resolution) of the CDSEM preventing it from capturing these applications and assess if an image-based structural metrology tool is still needed given the niche that scattering tools are filling. The answer is yes. Next we discuss whether the CDSEM will eventually meet those needs or if other alternative solutions are needed. Lastly, we discuss an industry survey on which image-based technique holds the most promise to solve these challenges. Regarding defect inspection, resolution is also a concern for the applications that need to detect extremely small defects which current optical-based Brightfield tools cannot address. While resolution is a primary concern in structural metrology, current EBI and EBR tools possess the resolution needed for defect inspection and have extendibility through at least the next advanced technology node. We also explore the niche E-beam is filling in defect inspection, evaluate the idea that a better synergistic solution exists today between the CDSEM and the EBI tools and propose a future E-beam landscape where E-beam tool variety in future fabs is significantly reduced to enhance productivity.

To measure the new SEMATECH 9 nm node Intentional Defect Array (IDA) and subsequent small, complex defects, a methodology has been used to exploit the rich information content generated when simulating or acquiring several images of sub-wavelength-sized defects through best focus. These images, which are xy planes, collected using polarized illumination are stacked according to focus position, z, and through interpolation, volumetric pixels (“voxels”) are formed sized approximately 40 nm per side. From the image data, an intensity can be assigned to each (x,y,z) position. These four-dimensional matrices are extensively filtered for defect detection using multi-dimensional intensity thresholding, nearest-neighbor criteria, continuity requirements, and other techniques standard to optical defect inspection. A simulation example with oblique angles of illumination is presented. Experimental results are shown from the NIST λ=193 nm Microscope using full-field illumination. Volumetric data analysis is compared against the processing of single 2-D images. Defect metrics for comparing planar and volumetric data are developed with the potential shown for a five-fold increase in defect sensitivity using volumetric data versus conventional imaging.

In this paper we present a novel mode of electron beam inspection (EBI), entitled super wide optics (SWO) mode, which can effectively detect buried defects in tungsten (W) plugs and copper (Cu) wires. These defects are defects of interest (DOI) to integrated circuit (IC) manufacturers because they are not detectable in optical inspection, voltage contrast (VC) mode EBI or physical mode EBI. We used engineering systems to study two samples, a tungsten chemical mechanical polish (CMP) wafer and a copper CMP wafer with a silicon carbon nitride (SiCN) cap layer. EBI with our novel SWO mode was found to capture many dark defects on these two wafers. Furthermore, defect review with all three EBI modes found some of these dark defects were unique to SWO mode. For verification, physical failure analysis was performed on some SWO-unique DOI. The cross-sectional scanning electron microscope (SEM) images and transmission electron microscope (TEM) images confirmed that the unique DOI were buried voids in W-plugs and copper wire thinning caused by either buried particles or buried particle induced metal trench under-etch. These DOI can significantly increase the resistance of metal interconnects of IC chip and affect the chip yield. This new EBI mode can provide an in-line monitoring solution for these DOI, which does not exist before this study.

We applied epi-illumination diffraction phase microscopy to measure the amplitude and phase of the scattered field from a SEMATECH 22 nm node intentional defect array (IDA) wafer. We used several imaging processing techniques to remove the wafer’s underlying structure and reduce both the spatial and temporal noise and eliminate the system calibration error to produce stretched panoramic amplitude and phase images. From the stretched images, we detected defects down to 20 nm × 160 nm for a parallel bridge, 20 nm × 100 nm for perpendicular bridge, and 35 nm × 70 nm for an isolated dot.

Coherent diffractive imaging (CDI) using EUV/X-rays has proven to be a powerful microscopy method for imaging nanoscale objects. In traditional CDI, the oversampling condition limits its applicability to small, isolated objects. A new technique called keyhole CDI was demonstrated on a synchrotron X-ray source to circumvent this limitation. Here we demonstrate the first keyhole CDI result with a tabletop extreme ultraviolet (EUV) source. The EUV source is based on high harmonic generation (HHG), and our modified form of keyhole CDI uses a highly reflective curved EUV mirror instead of a lossy Fresnel zone plate, offering a ~10x increase in photon throughput of the imaging system, and a more uniform illumination on the sample. In addition, we have demonstrated a record 22 nm resolution using our tabletop CDI setup, and also the successful extension to reflection mode for a periodic sample. Combining these results with keyhole CDI will open the path to the realization of a compact EUV microscope for imaging general non-isolated and non-periodic samples, in both transmission and reflection mode.

Although fin metrology presents many challenges, the single crystal nature of the fins also provides opportunities to use a combination of measurement methods to determine stress and pitch. While the diffraction of light during a scatterometry measurement is well known, X-ray diffraction from a field (array) of single crystal silicon fins can also provide important information. Since some fins have Si_1-xGe_x alloys at the top of the fin, determination of the presence of stress relaxation is another critical aspect of fin characterization. Theoretical studies predict that the bi-axially stressed crystal structure of pseudomorphic alloy films will be altered by the fin structure. For example, one expects it will be different along the length of the fin vs the width. Reciprocal space map (RSM) characterization can provide a window in the stress state of fins as well as measure pitch walking and other structural information. In this paper, we describe the fundamentals of how RSMs can be used to characterize the pitch of an array of fins as well as the stress state. We describe how this impacts the optical properties used in scatterometry measurement.

Photoresist shrinkage (i.e., line slimming) is an important systematic uncertainty source in critical dimension-scanning electron microscope (CD-SEM) metrology of lithographic features [1] [2] [3] [4] [5]. It influences both the precision and the accuracy of CD-SEM measurements, while locally damaging the sample. Minimization or elimination of shrinkage is desirable, yet elusive. This error source will be a factor in CD-SEM metrology on polymer materials in EUV lithography. Recent work has demonstrated improved understanding of the trends in the shrinkage response depending on electron beam and target parameters in static measurements [2] [3] [4] [5] [6]. Some research has highlighted a second mode of shrinkage that is apparent over time and progresses as a function of time between consecutive measurements, a form of “dynamic shrinkage” that appears to be activated by electron beam, in which the activated feature perpetually and logarithmically shrinks [7] [8]. Another work has demonstrated that as pitches continue to get smaller with resulting reductions in spaces between lines, charging may emerge as an additional, competing, unpredictable error source for CD-SEM metrology on dense photoresist features, an issue that is predicted to become more common as these spaces become more confined [9]. In this work, we explore the static shrinkage behaviors of various EUV photoresists into the 16 nm half-pitch node, with samples generated using the advanced EUV lithography capable of generating such tight pitches [10]. Dynamic shrinkage behavior was explored on these materials last year [15]. The static shrinkage behaviors will be validated to show compliance with the SEMATECH shrinkage model [5] [6] on small EUV resist features. Using the results of the model fits, a simulation study will predict the shrinkage trends at future nodes. Further studies will confirm whether or not charging phenomena are observable, and the beginning of a charging simulation study will be discussed.

The mechanism of photoresist shrinkage induced by electron-beam (EB) irradiation was studied. A precise cross-sectional profile of a photoresist pattern was obtained by a scanning transmission electron microscope (STEM) after atomic layer deposition of HfO₂ on the sample patterns. Photoresist lines and spaces fabricated with positive-tone development and negative-tone development were exposed to an EB with much higher dose than a practical dose (to accelerate shrinkage intentionally). The obtained STEM images of the patterns before and after EB irradiation show that the shrinkage of the negative-tone-developed patterns is smaller than that of the positive-tone-developed patterns. This observation is explained by the fact that negative-tone-developed photoresist molecules do not contain protection groups, whose volatilization caused by EB irradiation is one of the origins of shrinkage. Another finding is that the EB irradiation causes top-rounding and necking of the pattern profile as well as linewidth slimming. The rounding of the pattern top profile suggests that the pattern’s shape was elastically deformed. In addition, EB irradiation only onto the spaces caused sidewall shrinkage and a necking profile, although no electrons were irradiated directly onto the pattern. These phenomena are considered to be due to the electrons scattered from the spaces to the pattern sidewall. Finally, a Monte Carlo simulation of electron scattering showed that the distribution of the deposited EB energy on the pattern surface corresponds to the above-described change in pattern shape. Consequently, these observations and simulation results clarify the importance of the effect of elastic shape change and the impact of the electrons scattered from the underlying layer onto the sidewall in the mechanism of photoresist shrinkage.

We have demonstrated that transmission critical dimension small angle X-ray scattering (CD-SAXS) provides high accuracy and precision CD measurements on advanced 3D microelectronic architectures. The competitive advantage of CD-SAXS over current 3D metrology methods such as optical scatterometry is that CD-SAXS is able to decouple and fit cross-section parameters without any significant parameter cross-correlations. As the industry aggressively scales beyond the 22 nm node, CD-SAXS can be used to quantitatively measure nanoscale deviations in the average crosssections of FinFETs and high-aspect ratio (HAR) memory devices. Fitting the average cross-section of 18:1 isolated HAR contact holes with an effective trapezoid model yielded an average pitch of 796.9 ± 0.4 nm, top diameter of 70.3 ± 0.9 nm, height of 1088 ± 4 nm, and sidewall angle below 0.1°. Simulations of dense 40:1 HAR contact holes and FinFET fin-gate crossbar structures have been analyzed using CD-SAXS to inquire the theoretical precision of the technique to measure important process parameters such as fin CD, height, and sidewall angle; BOX etch recess, thickness of hafnium oxide and titanium nitride layers; gate CD, height, and sidewall angle; and hafnium oxide and titanium nitride etch recess. The simulations of HAR and FinFET structures mimic the characteristics of experimental data collected at a synchrotron x-ray source. Using the CD-SAXS simulator, we estimate the measurement capabilities for smaller similar structures expected at future nodes to predict the applicability of this technique to fulfill important CD metrology needs.

The uses of strained channel became prevalent at the 65 nm node and have continued to be a large part of logic device performance improvements in every technology generation. These material and integration innovations will continue to be important in sub-22nm devices, and are already being applied in finFET devices where total available in-channel strains are potentially higher. The measurement of structures containing these materials is complicated by the intrinsic correlation of the measured optical thickness and variation of optical properties with strain, as well as the dramatic reduction in total volume of the device. Optical scatterometry has enabled characterization of the feature shape and dimensions of complex 3D structures, including non-planar transistors and memory structures. Ellipsometric methods have been successfully applied to the measurement of thin films of SiGe and related strained structures. A direction for research is validating that the thin film stress results can be extended into the much more physically complex 3D shape. There are clear challenges in this: the stress in a SiGe fin is constrained to match the underlying Si along one axis, but the sides and top are free, leading to very large strain gradients both along the fin width and height. Practical utilization of optical techniques as a development tool is often limited by the complexity of the scatterometry model and setup, and this added material complexity presents a new challenge. In this study, generalized spectroscopic ellipsometric measurements of strained grating was undertaken, in parallel with reference cross sectional and top down SEM data. The measurements were modeled for both anisotropy calculations, as well as full scatterometry calculations, fitting the strain and structure. The degree to which strain and CD can be quickly quantified in an optical model is discussed. Sum decomposition method has been implemented to extract the effective anisotropic coefficients and a discussion on the effect of anisotropy toward modeling is presented. Finally, errors in the scatterometry measurement are analyzed, and the relative strengths and limitations of these optical measurements compared.

Photoacoustic nanometrology using coherent extreme ultraviolet (EUV) light detection is a unique and powerful tool for probing ultrathin films with a wide range of mechanical properties and thicknesses well under 100 nm. In this technique, short wavelength acoustic waves are generated through laser excitation of a nano-patterned metallic grating, and then probed by diffracting coherent EUV beams from the dynamic surface deformation. Both longitudinal and surface acoustic waves within thin films and metallic nanostructures can be observed using EUV light as a phase-sensitive probe. The use of nanostructured metal transducers enables the generation of particularly short wavelength surface acoustic waves, which truly confine the measurement within the ultrathin film layer of interest, to thicknesses < 50 nm for the first time. Simultaneous measurement of longitudinal and transverse surface wave velocities yields both the Young’s modulus and Poisson’s ratio of the film. In the future, this approach will make possible precise mechanical characterization of nanostructured systems at sub-10 nm length scales.

One of the key challenges to high resolution resist patterning is pattern collapse. Using a new scanning probe microscopy (SPM), Peak Force^TM tapping, we map nano-mechanical properties-- modulus, adhesion, and dissipation-- of the exposed/developed resist structures with sub-10 nm resolution. Properties are compared across a carbon based negative resist with and without cross-linking. The SPM technique reveals that cross-linking significantly enhances the mechanical properties to give a champion resolution of sub 20 nm half-pitch in a chemically amplified negative resist system. Beyond mechanical properties, surface morphology and redistribution kinetics were examined using complementary techniques and reveal additional benefits with cross-linking.

In this paper we will review typical applications of photoluminescence (PL) metrology in high volume LED manufacturing environments. PL is a well-established method for analysis of semiconductor properties. The technique is non-contact, non-destructive and rapid. We will describe the principles of the measurement and review PL data from LED process wafers. We will discuss how PL measurement results like peak wavelength, dominant wavelength and PL intensity are obtained. We will summarize the accuracy, precision, stability and other considerations of the measurement. Finally, metrology considerations for manufacturing LEDs on large diameter substrates, including the possibility of 8” silicon substrates, will be presented.

In this paper, we present a comparison of profile measurements of vertical field effect transistor (FinFET) fin arrays by optical critical dimension (OCD) metrology and critical dimension small angle X-ray scattering (CD-SAXS) metrology. Spectroscopic Muller matrix elements measurements were performed at various azimuthal angles for OCD, and X-ray diffraction intensities were collected for different incident angles in CD-SAXS measurements. A common trapezoidal model was used to compute the OCD and CD-SAXS signatures, using rigorous coupled wave (RCW) analysis and a 2D Fourier transform, respectively. Profile parameters, some material parameters, and instruments parameters were adjusted by a non-linear fitting procedure of the data. Results from both measurement techniques were compared and found in reasonable agreement with one another, although some of the parameters have differences that exceed the estimated uncertainties.

Gate patterning control for 28nm Fully Depleted Silicon On Insulator (FD-SOI) technology faces several challenges. For lithography and etch , usage of DoseMapper requires extensive and accurate metrology to compute adequate dose recipes. From etch side we will have to control both polysilicon and metal gate CD’s. For device integration it will be extremely important to monitor N and PMOS devices and get appropriate gate profiles since transistor morphology is a key contributor to device performances. In parallel of CD control, thin silicon film on top of buried oxide layer will also require a strict control of its thickness. Scatterometry is the only way to get all these informations from a patterned environment [1]. We will show in this paper how scatterometry has been proven to be accurate enough to support the realization of DOE’s for metal gate profile optimisation at gate patterning without doing hundred’s of TEM. Scatterometry results are correlated to parametric tests and TEM for ultimate validation.

Optical critical dimension (OCD) metrology using scatterometry has been demonstrated to be a viable solution for fast and non-destructive in-line process control and monitoring. As extreme ultraviolet lithography (EUVL) is more widely adopted to fabricate smaller and smaller patterns for electronic devices, scatterometry faces new challenges due to several reasons. For 14nm node and beyond, the feature size is nearly an order of magnitude smaller than the shortest wavelength used in scatterometry. In addition, thinner resist layer is used in EUVL compared with conventional lithography, which leads to reduced measurement sensitivity. Despite these difficulties, tolerance has reduced for smaller feature size. In this work we evaluate 3D capability of scatterometry for EUV process using spectroscopic ellipsometry (SE). Three types of structures, contact holes, tip-to-tip, and tip-to-edge, are studied to test CD and end-gap metrology capabilities. The wafer is processed with focus and exposure matrix. Good correlations to CD-SEM results are achieved and good dynamic precision is obtained for all the key parameters. In addition, the fit to process provides an independent method to evaluate data quality from different metrology tools such as OCD and CDSEM. We demonstrate 3D capabilities of scatterometry OCD metrology for EUVL using spectroscopic ellipsometry, which provides valuable in-line metrology for CD and end-gap control in electronic circuit fabrications.

CD and shape control of extreme ultraviolet lithography (EUVL) structures is critical to ensure patterning performance at the 10 nm technology node and beyond. The optimum focus/dose control by EUV scanner is critical for CD uniformity, and the scanner depends on reliable and rapid metrology feedback to maintain control. The latest advances in scatterometry such as ellipsometry (SE), reflectometry (NISR), and Mueller matrix (MM) offers complete pattern profile, critical dimensions (CD), side-wall angles, and dimensional characterization. In this study, we will present the evaluation results of CD uniformity and focus dose sensitivity of line and space EUV structures at the limit of current ASML NXE 3100 scanner printability and complex 3D EUV structures. The results will include static and dynamic precision and CD-SEM correlation data.

Fast and robust metrologies for retrieving large amount of accurate wafer data is the key to meet the ever stricter semiconductor manufacturing process control such as critical dimension (CD) and overlay as the industry moving towards 22 nm or smaller designs. Scatterometry emerges due to its non-destructivity and rapid availability for accurate wafer data. In this paper we simulate the ability of a new scatterometry method to show its accurate control over lithography model and OPC model calibrations. The new method directly utilizes scattering signals of scatterometry to control the process instead of using numerically analyzed dimensional parameters such as CD and side wall angle (SWA). The control can be achieved by optimizing the scattering signal of one process by tuning numerical aperture (NA), sigma, or lens aberration to match the signal of the target process. In this work only sigma is used for optimization. We found that when the signals of both processes are matched with minimized optimization error, CD of the grating profiles on the wafers are also minimized. This result enables valid lithography process control and model calibration with the new method.

The ongoing transition from 2D to 3D structures in logic and memory has led to an increased adoption of scatterometry CD (SCD) for inline metrology. However, shrinking device dimensions in logic and high aspect ratios in memory represent primary challenges for SCD and require a significant breakthrough in improving signal-to-noise performance. We present a report on the new generation of SCD technology, enabled by a new laser-driven plasma source. The developed light source provides several key advantages over conventional arc lamps typically used in SCD applications. The plasma color temperature of the laser driven source is considerably higher than available with arc lamps resulting in >5X increase in radiance in the visible and >10X increase in radiance in the DUV when compared to sources on previous generation SCD tools while maintaining or improving source intensity noise. This high radiance across such a broad spectrum allows for the use of a single light source from 190-1700nm. When combined with other optical design changes, the higher source radiance enables reduction of measurement box size of our spectroscopic ellipsometer from 45×45um box to 25×25um box without compromising signal to noise ratio. The benefits for 1×nm SCD metrology of the additional photons across the DUV to IR spectrum have been found to be greater than the increase in source signal to noise ratio would suggest. Better light penetration in Si and poly-Si has resulted in improved sensitivity and correlation breaking for critical parameters in 1xnm FinFET and HAR flash memory structures.

Resist spin coating has already been applied to IC industry for a very long time. Uniform spin coat of photoresist has been demonstrated on 12” wafers with conventional 6” and 8” methods. Meanwhile, resist dispense volume reduction has also been widely studied and investigated. In our paper, we focus on the physical properties of photoresist and prewet solvent. We try to figure out the interfacial behavior/mechanism between ArF resist and its related pre-wet solvent by systematic methods and DOE splits. In the experiments, different ArF resists among various solvent systems and two distinct pre-wet systems are tested and researched. Certain ArF resists generate smaller dispense volume compared with other PRs even under the same process condition. Eventually, from the splits we find out the trend which correlates to the interaction between resist and pre-wet solvent. The trend proves that our hypothesis is correct. The conclusion will contribute to our future resist selection. The conclusion will also provide new resist design concept to resist vendors. Basic studies and experiments are carried out under our limited resources, equipment and time. We have tried our best to find out the mechanism and have proved it.

As device features continue to shrink, achieving acceptable yields becomes increasingly challenging. In the photolithography process, mask error is one of the most critical error sources, since any imperfections on a mask will be amplified and transferred onto a wafer due to Mask Error Enhancement Factor (MEEF) [1]. Furthermore, due to complexity of lithography optical proximity effect correction in advanced technology nodes, more and more 2D structures are applied into mask patterns. Furthermore, more 2D pattern configurations are susceptible to pattering failures due to their much high MEEF factor than 1D pattern. As a result, the conventional mask error control mechanisms for 1D [2] [3] [4] only, such as mean-to-target (MTT) and CD uniformity, are no longer adequate to deal with high MEEF 2D structures. In this paper, a novel 2D structure mask error monitoring technique is introduced to prevent fatal wafer printing errors such as CD error, line-end pull back and other pattern distortions to ensure high quality mask manufacturing and to improve wafer yield in advanced technology nodes. We will demonstrate the flow using typical 2D structure test patterns in 28nm technology node design or beyond. The SEM image would be taken and measured by this novel technique are used to monitor mask fidelity performance. This monitoring technique is based on Image-to-layout, as one of Anchor Semiconductor’s pattern centric techniques, which can extract contour and convert it into pattern layouts from SEM or optical image of masks. Further pattern signature analysis can be performed on the pattern (inner /outer vertex, space distance and edge distance), so that we can quickly identify target locations for 2D pattern measurements. We monitor the severity of 2D corner rounding on selected 28nm design rule masks by Pattern Fidelity (PF) ratio and correlate them with wafer printing results. 2D pattern measurement techniques and PF ratio monitoring system from SEM image is an effective approach to ensure high quality mask making in 28nm and advanced technology nodes. This PF ratio monitoring from 2D pattern SEM images is an effective approach to ensure high quality mask making in advanced 28nm node and beyond, which can overcome the inadequacy of current 1D measurement only method, especially for the masks are generated without source mask optimization (SMO) [6].

Advanced thermal annealing processes used for transistor enhancing for the state of the art process nodes induce wafer grid deformations. RTA (Rapid Thermal Anneal) and LSA (Laser Scanning Anneal) processes are a few examples. High Order Wafer Alignment (HOWA) method is an effective wafer alignment strategy for wafers with distorted grid signature especially when wafer-to-wafer grid distortion variations are also present. However, usage of HOWA in high volume production environment requires 1) careful initial determination of optimum polynomial order and alignment sampling to be implemented, and 2) matched tool monitoring and controlling strategies and infrastructures to avoid potential HOWA induced drawbacks (i.e. alignment walking).

As device dimensions shrink, the measurement of layer-to-layer overlay is becoming increasingly important. Overlay is currently measured using target patterns fabricated within scribe lines. However, there are residual errors between the measurement values at the scribe lines and the actual values at the circuit pattern regions. Therefore, in-die overlay measurements using circuit patterns are required for precise overlay control. We have developed an in-die overlay measurement method based on SEM images. The overlay is directly measured by comparing a golden image and a test image captured at the circuit pattern region. Each layer is automatically recognized from the images, and the placement error between the two images is determined and used to calculate the overlay. This enables measurement without a specially designed target pattern or the setting up of measurement cursors. In the simulation experiments, the proposed method has linearity and sensitivity for the sub-pixel-order overlay even if the patterns have size variations. The basic performance of this method was evaluated using a defect review SEM. For advanced memory devices, a measurement repeatability of less than 1.0 nm was achieved, and a reasonable wafer map of the overlay was obtained.

Defect inspection of EUV substrates and mask blanks must be controlled consistently to ensure repeatable and accurate defect counts. Initial sensitivity must be maintained without producing false counts. Various constructed and native defect monitors are created on substrates to track inspection tool performance. Remedies are applied to an inspection tool when monitors go out of control.

Traditionally, an optical proximity correction model is to evaluate the resist image at a specific depth within the photoresist and then extract the resist contours from the image. Calibration is generally implemented by comparing resist contours with the critical dimensions (CD). The wafer CD is usually collected by a scanning electron microscope (SEM), which evaluates the CD based on some criterion that is a function of gray level, differential signal, threshold or other parameters set by the SEM. However, the criterion does not reveal which depth the CD is obtained at. This depth inconsistency between modeling and SEM makes the model calibration difficult for low k₁ images. In this paper, the vertical resist profile is obtained by modifying the model from planar (2D) to quasi-3D approach and comparing the CD from this new model with SEM CD. For this quasi-3D model, the photoresist diffusion along the depth of the resist is considered and the 3D photoresist contours are evaluated. The performance of this new model is studied and is better than the 2D model.

Fingerprint edge roughness (FER) is proposed to characterize high frequency roughness of fingerprint pattern edges assembled by lamella forming block copolymer (BCP). The FER is a roughness index which does not include the roughness component of the fingerprint curvature. A technique to evaluate FER by using CD-SEM is also proposed. Centerline of the fingerprint patterns were extracted by utilizing binarization and slimming algorithm, and line width, line width roughness and line edge roughness along the centerline were measured. The FER thus measured showed a good agreement with those determined by utilizing conventional line edge roughness analyzing algorithm. The FERs of fingerprint patterns assembled with various BCP formulations were analyzed. As a result, the proposed technique successfully detected the line edge roughness difference between each BCP formulations with different compositions. The results indicate that the FER might be a useful index to evaluate the patterning performance of BCP as a material for DSA process. The proposed technique will provide a method for fast and easy development of BCP materials and processes

In dark-field particle inspection, the limiting factor for sensitivity is the amount of background scatter due to substrate roughness. This scatter forms a speckle pattern and shows an intensity distribution with a long tail. To reduce falsepositives to an acceptable level, a high detection threshold should be chosen such that the tail of the background distribution is avoided. We have modeled an optimized illumination mode, that reduces the variance in the background distribution. This illumination mode illuminates the substrate from multiple azimuth angles. We show that the speckle patterns generated by each azimuth angle can be independent from each other. Therefore by combining the angles, the variance of the background signal is reduced. We show that for the parameters of our inspection system the detection threshold can be reduced by a factor three, resulting in a lower detection limit that is 20% smaller in particle size. The change in the background scattering distribution was confirmed by experiments.

We introduced a very simple overlay feed forward correction based on lot data issued from previous lithography operations. Simple method for correction factor optimization was also proposed. We applied this method in various cases based on 28nm node early production: implants lithography on 248nm tools, contact holes double patterning on 193nm immersion tool, and we also tried to improve contact holes patterning based on 248nm lithography data. All analysis were based on early production 28nm node data mixing 28LP and 28FDSOI technologies. We first optimized the correction based on our simple approach, and then compute the dispersion of all linear overlay parameters. Maximum modeled overlay error was also computed. In most cases we obtained significant improvements. The interest of such a very simple approach that requires reduced software development and allows simple implementation was thus demonstrated.

We introduced a simple method based on scatterometry measurement performed on dense contact holes matrix to investigate intrafield focus deviation on 28nm FDSOI real production wafers at contact holes patterning lithography operation. A complex three-dimensional scatterometry model with all patterned resist geometrical parameters left as degree of freedom. Then simple linear relationships between patterned resist geometrical parameters on the one hand, and applied dose and focus offset on the other hand were used to determine a focus and dose decorrelation model. This model was then used to investigate the effect of ASML AGILE^TM scanner option on intrafield focus deviation. A significant 16% intrafield focus standard deviation improvement was found with AGILE^TM, which validated our method and shows the possibilities of AGILE^TM option for intrafield focus control. This focus investigation method may be used to improve advanced CMOS manufacturing process control.

A method for automatic computation of parameter derivatives of numerically computed light scattering signals is demonstrated. The finite-element based method is validated in a numerical convergence study, and it is applied to investigate the sensitivity of a scatterometric setup with respect to geometrical parameters of the scattering target. The method can significantly improve numerical performance of design optimization, parameter reconstruction, sensitivity analysis, and other applications.

This paper discusses the defect density detection and analysis methodology using advanced optical wafer inspection capability to enable accelerated development of a DSA process/process tools and the required inspection capability to monitor such a process. The defectivity inspection methodologies are optimized for grapho epitaxy directed self-assembly (DSA) contact holes with 25 nm sizes. A defect test reticle with programmed defects on guide patterns is designed for improved optimization of defectivity monitoring. Using this reticle, resist guide holes with a variety of sizes and shapes are patterned using an ArF immersion scanner. The negative tone development (NTD) type thermally stable resist guide is used for DSA of a polystyrene-b-poly(methyl methacrylate) (PS-b-PMMA) block copolymer (BCP). Using a variety of defects intentionally made by changing guide pattern sizes, the detection rates of each specific defectivity type has been analyzed. It is found in this work that to maximize sensitivity, a two pass scan with bright field (BF) and dark field (DF) modes provides the best overall defect type coverage and sensitivity. The performance of the two pass scan with BF and DF modes is also revealed by defect analysis for baseline defectivity on a wafer processed with nominal process conditions.

In this paper, we show the 2D and 3D scatterometry simulation software which has spectroscopy calculation and optimization algorithm systems. The scatterometry analysis for 3D-structure requires a lot of memory and along calculation time. The calculation is sped up by parallel computing using the GPU (Graphics Processor Unit). Here, we use the programming language CUDA (Compute Unified Device Architecture) and CULA (CULApack) for the NVIDIA GPU. Then, we use the real-coded GA (RCGA) to increase the population, to make a more sensitive solution and to get better fitting groove figures. The scatterometry characteristic is examined by choosing the n-th power cosine type period groove.

High-K/metal gate technology, introduced by Intel, to replace the conventional oxide gate dielectric and polysilicon gate has truly revolutionized transistor technology more than any other change over the last 40 years. First introduced at the 45nm node, this complex process has now been adopted for advanced nodes. The capability of picosecond ultrasonic measurements (PULSE^TM) for in-line monitoring of High-K/metal gate structures was evaluated and the benefits of this technology for measuring various structures including SRAM, pad array, and line array key with excellent correlation to cross sectional TEM was demonstrated. We have shown that, only a direct measurement of SRAM structures can represent true variations of the metal gate height due to CMP process and is strongly affected by the design and layout of pattern, including pattern density, dummy design, and spacing. The small spot, non-contact, non-destructive nature of this technology allows for in-line measurements directly on these structures with excellent repeatability at a very high throughput.

In this paper, we propose advanced overlay stability control improving conventional stability control, Baseliner™ and reference wafers with new vertical structure for effective stability control. We verify improved overlay stability control experimentally by using this stability control method. Also we suggest that additional improvements can be achieved by controllable process terms. For focus stability control, we make reference wafers which can measure overlay and focus simultaneously on the same wafer to minimize monitoring wafers.

This paper presents a methodology for detecting defects more effectively that have a substantial yield impact on several critical layers using a simulation program, which is considerably helpful in analyzing defects on the wafer. First, this paper presents a simple analysis method that uses mathematical treatment for multi thin film layers. This instantly gives us a highly intuitive idea for selecting an inspection mode based on the reflectivity and transmittivity. Second, we introduce numerical method for wafer defect of interest with finite difference time domain (FDTD) method, and provide correlation between the expectation and experimental results. The goal of these studies is to determine the feasibility of implementing theoretical approaches with numerical method at wafer defect inspection. Overall, this paper discusses the effective wafer inspection methodology and the advantages of defect simulation with numerical analysis at semiconductor manufacturing for accelerated development of advanced design node devices.

Continued tightening of overlay control budget in semiconductor lithography drives the need for improved metrology capabilities. Aggressive improvements are needed for overlay metrology speed, accuracy and precision. This paper is dealing with the on product metrology results of a scatterometry based platform showing excellent production results on resolution, precision, and tool matching for overlay. We will demonstrate point to point matching between tool generations as well as between target sizes and types. Nowadays, for the advanced process nodes a lot of information is needed (Higher order process correction, Reticle fingerprint, wafer edge effects) to quantify process overlay. For that purpose various overlay sampling schemes are evaluated: ultra- dense, dense and production type. We will show DBO results from multiple target type and shape for on product overlay control for current and future node down to at least 14 nm node. As overlay requirements drive metrology needs, we will evaluate if the new metrology platform meets the overlay requirements.

In order to fulfill the ever tightening requirements of advanced node overlay budgets, overlay metrology is becoming more and more sensitive to even the smallest imperfections in the metrology target. Under certain circumstances, inaccuracy due to such target imperfections can become the dominant contribution to the metrology uncertainty and cannot be quantified by the standard TMU contributors. In this paper we describe a calibration method that makes the overlay measurement robust to target imperfections without diminishing its sensitivity to the target overlay. The basic assumption of the method is that overlay measurement result can be approximated as the sum of two terms: the accurate overlay and the measurement inaccuracy (independently of the conventional contributors). While the first term (the “real overlay”) is robust it is known that the overlay target inaccuracy depends on the measurement conditions. This dependence on measurement conditions is used to estimate quantitative inaccuracy by means of the overlay quality merit which was described in previous publications. This paper includes the theoretical basis of the method as well as experimental validation.

With decreasing of critical dimension (CD), the availability of depth of focus (DOF) goes down from technology node to technology node. Monitoring and controling of scanner focus on product wafers will be necessary. A technique entitled Iso-Dense Focus Monitor(IDFM) is developed to measure the focus errors of scanner systems. This IDFM method uses double side chrome mask and iso-dense binary overlay mark. The accuracy of this IDFM technique using binary mark may equal to the conventional PGFM method, and the IDFM technique only expose the wafer one time comparing with Z-SPIN which may expose two times. This method was simulated and also implemented on a litho tool of SMEE SSA600/10.

Atomic force microscopy (AFM) is increasingly used in the semiconductor industry as a versatile monitoring tool for highly critical lithography and etching process steps. Applications range from the inspection of the surface roughness of new materials, over accurate depth measurements to the determination of critical dimension structures. The aim to address the rapidly growing demands on measurement uncertainty and throughput more and more shifts the focus of attention to the AFM tip, which represents the crucial link between AFM tool and the sample to be monitored. Consequently, in order to reach the AFM tool’s full potential, the performance of the AFM tip has to be considered as a determining parameter. Currently available AFM tips made from silicon are generally limited by their diameter, radius, and sharpness, considerably restricting the AFM measurement capabilities on sub-30nm spaces. In addition to that, there’s lack of adequate characterization structures to accurately characterize sub-25nm tip diameters. Here, we present and discuss a recently introduced AFM tip design (T-shape like design) with precise tip diameters down to 15nm and tip radii down to 5nm fabricated from amorphous, high density diamond-like carbon (HDC/DLC) using electron beam induced processing (EBIP). In addition to that advanced design, we propose a new characterizer structure, which allows for accurate characterization and design control of sub-25nm tip diameters and sub-10nm tip edges radii. We demonstrate the potential advantages of combining a small tip shape design, i.e. tip diameter and tip edge radius, and an advanced tip characterizer for the semiconductor industry by the measurement of advanced lithography patterns.

The semiconductor industry is moving toward 20nm nodes and below. As the Overlay (OVL) budget is getting tighter at these advanced nodes, the importance in the accuracy in each nanometer of OVL error is critical. When process owners select OVL targets and methods for their process, they must do it wisely; otherwise the reported OVL could be inaccurate, resulting in yield loss. The same problem can occur when the target sampling map is chosen incorrectly, consisting of asymmetric targets that will cause biased correctable terms and a corrupted wafer. Total measurement uncertainty (TMU) is the main parameter that process owners use when choosing an OVL target per layer. Going towards the 20nm nodes and below, TMU will not be enough for accurate OVL control. KLA-Tencor has introduced a quality score named ‘Qmerit’ for its imaging based OVL (IBO) targets, which is obtained on the-fly for each OVL measurement point in X & Y. This Qmerit score will enable the process owners to select compatible targets which provide accurate OVL values for their process and thereby improve their yield. Together with K-T Analyzer’s ability to detect the symmetric targets across the wafer and within the field, the Archer tools will continue to provide an independent, reliable measurement of OVL error into the next advanced nodes, enabling fabs to manufacture devices that meet their tight OVL error budgets.

The new measuring method that we developed executes a contour shape analysis that is based on the pattern edge information from a SEM image. This analysis helps to create a highly precise quantification of every circuit pattern shape by comparing the contour extracted from the SEM image using a CD measurement algorithm and the ideal circuit pattern. The developed method, in the next phase, can generate four shape indices by using the analysis mass measurement data. When the shape index measured using the developed method is compared the CD, the difference of the shape index and the CD is negligibly small for the quantification of the circuit pattern shape. In addition, when the 2D patterns on a FEM wafer are measured using the developed method, the tendency for shape deformations is precisely caught by the four shape indices. This new method and the evaluation results will be presented in detail in this paper.

Scatterometry is one of the most promising CD profile metrology technologies for future technology nodes. As critical dimension (CD) continues to decrease, sensitivity of scatterometry needs to be improved to measure even more subtle structures. Sensitivity of a scatterometer highly depends on film stack structure and optical properties of the sample and wavelength, incident angle and polarization implemented by the scatterometer. When measuring different types of sample, scatterometer should be capable of optimizing measuring configurations to get best sensitivity. In this work, we attempt to optimize the measuring sensitivity by introducing a hybrid scatterometer, which is able to measure reflected light from a sample through either an angle-resolved method or a spectroscopic method using two complementary measuring arms. In this setup, improvement of sensitivity can be achieved by choosing better measuring method and adjusting light wavelength, incident angle and polarization.

In preparation for EUV lithography (EUVL) in high volume manufacturing, a preproduction ASML NXE:3100 step-and- scan system was used to assess overlay performance under mix-and-match between EUV and ArF lithography, which will be critical for the successful insertion of EUV lithography into high volume 1x node production. Overlay sources of variation associated with EUV were investigated, including mask pattern-placement error (PPE), scan direction, and processing order. Furthermore, this study also looks into overlay control strategy development specifically for EUV/ArF mix-and-match lithography. Systematic and random overlay components will be discussed, as well as possible overlay modeling and control options.

As leading edge lithography moves to advanced nodes which requires better critical dimension (CD) control ability within wafer. Current methods generally make exposure corrections by field via factory automation or by sub-recipe to improve CD uniformity. KLA-Tencor has developed a method to provide CD uniformity (CDU) control using a generated Focus/Exposure (F/E) model from a representative process. Exposure corrections by each field can be applied back to the scanner so as to improve CD uniformity through the factory automation. CDU improvement can be observed either at after lithography or after etch metrology steps. In addition to corrections, the graphic K-T Analyzer interface also facilitates the focus/exposure monitoring at the extreme wafer edge. This paper will explain the KT CDFE method and the application in production environment. Run to run focus/exposure monitoring will be carried out both on monitoring and production wafers to control the wafer process and/or scanner fleet. CDU improvement opportunities will be considered as well.

High aspect ratio defects are more critical at sub 20nm design rule. The impact of these defects in the FEOL module is very critical as it leads to gate leakage which directly translates to yield loss at sub 20nm devices. Image 1a) and 1b) shown below is one such example of a high aspect ratio protrusion seen during the HiK stack for gate last process on a sub 20nm device. False and nuisance defects detected by optical inspection tools, degrade the inspection sensitivity of the tool to real and critical defects[1]. The intention of this paper would be to target two critical FEOL layers post Litho and post etch to detect these critical yield impacting defects using KLA-Tencor 2905 broadband brightfield inspection system for early development learning. In this paper we will discuss the DOE on all the different inspection points to intentionally generate these defects and summarize all the findings.

Semiconductor nanocrystals, also called quantum dots (QDs), have been proven as powerful fluorescent probes. This paper presents a new method to evaluate the retention efficiency of nanofiltration membranes using sub-10 nm fluorescent QDs in organic solvents. Two different Cd-based QDs with uniformed sizes (nominal 8 nm and 4 nm) were used as challenge particles in this study. Fluorescence spectrophotometer was used as a detector to measure the QDs concentration before and after filtration. High resolution transmission electron microscope (HRTEM) and dynamic light scattering (DLS) were employed for measuring particle size and size distribution, which revealed the QDs used in this study were with a narrow size distribution. Three different types of Entegris UPE membranes were tested by using this method. The filters were rated at 3 nm, 5 nm and 10 nm using bubble-point extrapolative methods were further confirmed by the QDs retention tests in solvents.

A non-destructive and fast optical solution for characterization of high aspect ratio and isolated 3D hard disk drive writer head air bearing surface structure is presented in this paper. While 2D gratings are plagued by line bending and accuracy problems, the 3D scatterometry test structures show superior mechanical stability and device resemblance necessary for an accurate measurement capability at a reactive ion etch process step enabling further ion mill shape predictability prior to a point of no return in the process. The scatterometry post RIE measurement on the 3D test targets show R^2 about five times better than dual beam FIB and a correlation slope roughly 3 times closer to unity. The post RIE scatterometry wafer sigma is in average 49% of the post RIE FIB sigma and 77% of the post ion mill FIB sigma.

Scatterometry-based metrology is a well proven method to measure and monitor the critical dimensions of interest in advanced sub-28nm process development and high volume manufacturing [1][3][4][6][7]. In this paper, a proposed solution to control and achieve the optimal gate critical dimension uniformity (CDU) was explored. The proposed solution is named a novel scatterometry slot gate CDU control flow. High performance measurement and control during the slot gate step is critical as it directly controls the poly line cut profile to the active area which then directly impacts the final device performance. The proposed flow incorporates scatterometry-based CD (SCD) measurement feedback and feed forward to the Automation Process Control (APC) system, further process recipe fine tuning utilizing the data feedback and forward, and two dimensional (2D) and three dimensional (3D) scatterometry-based CD (SCD) measurement of gate after developer inspection (ADI) and after etch inspection (AEI) [1]. The methodologies and experiment results presented in this study started from the process development through the SCD model optimization of the DOE wafers, to the final implementation of the process control flow and measurement loop into the production line to evaluate its capability for long term in-line monitoring in high volume manufacturing environment. The result showed significant improvement in the gate CD uniformity that met the sub-28nm process manufacturing requirement.

The introduction of early test wafer (ETW) 450mm Surface Scanning Inspection Systems (SSIS) into Si manufacturing has brought with it numerous technical, commercial, and logistical challenges on the path to rapid recipe development and subsequent qualification of other 450mm wafer processing equipment. This paper will explore the feasibility of eliminating the Polystyrene Latex Sphere deposition process step and the subsequent creation of SSIS recipes based upon the theoretical optical properties of both the SSIS and the process film stack(s). The process of Polystyrene Latex Sphere deposition for SSIS recipe generation and development is generally accepted on the previous technology nodes for 150/200/300mm wafers. PSL is deposited with a commercially available deposition system onto a non-patterned bare Si or non-patterned filmed Si wafer. After deposition of multiple PSL spots, located in different positions on a wafer, the wafer is inspected on a SSIS and a response curve is generated. The response curve is based on the the light scattering intensity of the NIST certified PSL that was deposited on the wafer. As the initial 450mm Si wafer manufacturing began, there were no inspection systems with sub-90nm sensitivities available for defect and haze level verification. The introduction of a 450mm sub-30nm inspection system into the manufacturing line generated instant challenges. Whereas the 450mm wafers were relatively defect free at 90nm, at 40nm the wafers contained several hundred thousand defects. When PSL was deposited onto wafers with these kinds of defect levels, PSL with signals less than the sub-90nm defects were difficult to extract. As the defectivity level of the wafers from the Si suppliers rapidly improves the challenges of SSIS recipe creation with high defectivity decreases while at the same time the cost of PSL deposition increases. The current cost per wafer is fifteen thousand dollars for a 450mm PSL deposition service. When viewed from the standpoint of the generations of hundreds of SSIS recipes for the global member companies of ISMI, it is simply not economically viable to create all recipes based on PSL based light scattering response curves. This paper will explore the challenges/end results encountered with the PSL based SSIS recipe generation and compare those against the challenges/end results of SSIS recipes generated based strictly upon theoretical Bidirectional reflectance distribution function (BRDF) light scattering modeling. The BRDF modeling will allow for the creation of SSIS recipes without PSL deposition, which is greatly appealing for a multitude of both technical and commercial considerations. This paper will also explore the technical challenges of SSIS recipe generation based strictly upon BRDF modeling.

Circuit layout and design rules have continued to shrink to the point where a few nanometers of pattern misalignment can negatively impact process capability and device yields. As wafer processes and film stacks have become more complex, overlay and alignment performance in high-volume manufacturing (HVM) have become increasingly sensitive to process and tool variations experienced by incoming wafers. Current HVM relies on overlay control via advanced process control (APC) feedback, single-exposure tool grid stability, scanner-to-scanner matching, correction models, sampling strategies, overlay mark design, and metrology. However, even with improvements to those methods, a large fraction of the uncorrectable errors (i.e., residuals) still remains. While lower residuals typically lead to increased yield performance, it is difficult to achieve in HVM due to the large combinations of wafer history in terms of prior tools, recipes, and ongoing process conversions. Hence, it is critical to understand the effect of residual errors on measurement sampling and model parameters to enable process control. In this study, we investigate the following: residual errors of sub-40nm processes as a function of correction models, sensitivity of the model parameters to residue, and the impact of data quality.

Extreme ultraviolet lithography (EUVL) is one of the most leading lithography technologies for high volume manufacturing. The EUVL is based on reflective optic system therefore critical patterning issues are arisen from the surface of photomask. Defects below and inside of the multilayer or absorber of EUV photomask is one of the most critical issues to implement EUV lithography in mass production. It is very important to pick out and repair printable mask defects. Unfortunately, however, infrastructure for securing the defect free photomask such as inspection tool is still under development furthermore it does not seem to be ready soon. In order to overcome the lack of infrastructures for EUV mask inspection, we will discuss an alternative methodology which is based on wafer inspection results using DBM (Design Based Metrology) tool. It is very challenging for metrology to quantify real mask defect from wafer inspection result since various sources are possible contributor. One of them is random defect comes from poor CD uniformity. It is probable that those random defects are majority of a defect list including real mask defects. It is obvious that CD uniformity should be considered to pick out only a real mask defect. In this paper, the methodology to determine real mask defect from the wafer inspection results will be discussed. Experiments are carried out on contact layer and on metal layer using mask defect inspection tool, Teron(KLA6xx) and DBM (Design Based Metrology) tool, NGR2170™.

As optical lithography continues to extend into low-k1 regime, resolution of mask patterns continues to diminish. The limitation of 1.35 NA posed by water-based lithography has led to the application of various resolution enhancement techniques (RET), for example, use of strong phase-shifting masks, aggressive OPC and sub-resolution assist features, customized illuminators, etc. The adoption of these RET techniques combined with the requirements to detect even smaller defects on masks due to increasing MEEF, poses considerable challenges for a mask inspection engineer. Inspecting masks under their actinic-aerial image conditions would detect defects that are more likely to print under those exposure conditions. However, this also makes reviewing such defects in their low-contrast aerial images very challenging. On the other hand, inspecting masks under higher resolution inspection optics would allow for better viewing of defects post-inspection. However, such inspections generally would also detect many more defects, including printable and nuisance, thereby making it difficult to judge which are of real concern for printability on wafer. Often, an inspection engineer may choose to use Aerial and/or high resolution inspection modes depending on where in the process flow the mask is and the specific device-layer characteristics of the mask. Hence, a comprehensive approach is needed in handling defects both post-aerial and post-high resolution inspections. This analysis system is designed for the Applied Materials Aera™ mask inspection platform, all data reported was collected using the Aera.

This work presents how the combination of EDA and CDSEM tools enable development and manufacturing engineers to collect CDSEM data of a large diversity of features and contexts seamlessly for OPC model calibration and validation, process development, and inline manufacturing monitoring. We will present the application and results of a solution proposed in a previously published paper[1] and then review the benefits of enabling development and manufacturing engineers to make metrology-related decisions within their environments. Finally, new applications for automated CDSEM recipe generation and data collection will be discussed.

Traditionally, product development for reticle defect inspection mostly addressed operational requirements of the mask shops with highly individualized manufacturing. As a result, limited automation capability was available as compared to the standards in wafer production. Wafer fabs are guided by completely different conditions. Thousands of active reticles exist in a single fab requiring frequent re-inspections without interruption of wafer exposures. This requires high throughput of inspection tools, smart management of tool fleet, sophisticated scheduling and in-time execution of reticle inspections linked to the wafer manufacturing. The paper reports about the successful implementation of fully automated reticle defect inspection in a high-volume advanced logic fab. Automation scenarios - created based on existing SEMI standards - included inspection scheduling, reticle transport and inspection tool operation. A considerable productivity gain for the operation of Lasertec MATRICS X700 series inspection tools was obtained. Based on the learning throughout implementation, the requirements to the automation capability and tool operation as well as adjustments to working procedures are discussed.

The main driver for Semiconductor and Bio-MEMS industries is decreasing the feature size, moving from the current state-of-the-art at 22 nm towards 10 nm node. Consequently smaller defects and particles become problematic due to size and number, thus inspecting and characterizing them are very challenging. Existing industrial metrology and inspection methods cannot fulfil the requirements for these smaller features. Scanning probe Microscopy (SPM) has the distinct advantage of being able to discern the atomic structure of the substrate. It can image the 3D topography, but also a variety of material, mechanical and chemical properties. Therefore SPM has been suggested as one of the technologies that can fulfil the future requirements in terms of resolution and accuracy, while being capable of resolving 3D futures. However, the throughput of the current state-of-the-art SPMs are extremely low, as compared to the high-volume manufacturing requirements. This paper presents the development of an architecture^[1] for a fully automated high throughput SPM, which can meet the requirements of future process metrology and inspection for 450 mm wafers. The targeted specifications of the concept are 1) inspecting more than 20 sites per wafer, 2) each site with dimension of about 10 × 10 μm² (scalable to 100 × 100 μm²) and 3) with a throughput of more than 7 wafers per hour, or 70 wafers per hour with a coarse/fine scanning approach. The progress of the high throughput SPM development is discussed and the baseline design of the critical sub-modules and the research issues are presented.

Photo resist shrinkage during CD-SEM measurements has been a well known phenomenon. It presents great difficulties and challenges in CD-SEM metrology, for example, in the CD-SEM tool matching. The “check board” method currently popular in CD-SEM tool matching avoids measuring the same location twice and resorts to the statistical averaging out the CD difference in each paired measurements. This paper presents a new cross sampling method which inherently eliminates the CD difference in each paired measurement. The pro and con of these two sampling methods are studied with resort to a resist shrinkage model. A conceptual equation of the real tool difference on ADI pattern is proposed. Through this equation, we are able to determine the magnitude of the real difference via the shrinkage model combining the measurements from the cross sampling method. A quantitative study of the resist shrinkages with multiple subsequent measurements is carried out. An exponential model is assumed and proved to have good fit with the experimental data. From such resist shrinkage model, we are able to deduce the original resist line/hole CD size without any e-beam disturbance. The relative change of the CD after the first measurement is revealed quantitatively from such a model with very good accuracy. Combing the fitted models with the cross sampling measurement results we are able to determine the real CD difference, if they were measured by these two CD-SEM tools, which cannot be obtained by direct measurements because of the memory of any previous measurements.

The measurement accuracy of phase shifting shadow moiré is limited by the spatially non-uniform and random phase shift error. Substantial work has been developed to overcome this difficulty. But few works are proposed to deal with the two error sources above simultaneously. In the presented paper, we describe a solution that can compensate the both error sources at the same time. In our proposed method, a binocular stereovision system is integrated into our test configuration. By measuring the coordinates of marks attached to the measurement grating, the stereovision system obtains the position and the setting parameters are calibrated. Then, the acquiring three fringe patterns are analyzed by iterative least squares method in temporal and the phase shift is calibrated by the least squares fitting in spatial. Because a local cost function is used, the proposed calibration technique is insensitive to spatial variations in detector response. Numerical simulations and optical experiments show that the proposed method can effectively minimize the two phase-shift error sources and possess a superior performance than the existing typical phase shifting algorithm.

We present a fast phase shifting shadow moiré device for the measurement of surface topography. In our set-up, the phase shift across the field of view shadow moiré is introduced by using two light sources illuminate the grating sequentially. Therefore, it is possible to capture the two fringe patterns at high speed. Due to the effect of bias modulation, the proposed phase demodulation method first removes the DC term of the sampling data. Then a spiral phase transform (SPT) based technique is developed to determine the introduced phase shift pointwisely. After that, the tunable two-frame algorithm is used to extract the wrapped phase map with no spatially non-uniform phase shift error. We implemented a fast technique to determine the topography of a surface by a simple experimental set-up. The proposed technique was applied to obtain an external surface of a specimen. The experimental results show the validity of this technique.

As a non-imaging optical measurement technique, spectroscopic Mueller matrix polarimetry (MMP) has been introduced for critical dimension (CD) and overlay metrology with recent great success. Due to the additional information provided by the Mueller matrices when the most general conical diffraction configuration is considered, MMP has demonstrated a great potential in semiconductor manufacturing. In order to make full use of the additional information provided by the Mueller matrices, it is of great importance for MMP to optimize the measurement configuration. In this paper, we introduce the norm of a configuration error propagating matrix as the cost function to optimize the measurement configuration for spectroscopic MMP with the aim of finding an optimal combination of fixed incidence and azimuthal angles, which provides higher measurement accuracy. The optimal measurement configuration can be achieved by minimizing the norm of the configuration error propagating matrix in the available ranges of incidence and azimuthal angles. Experiments performed on a silicon grating with a dual-rotating compensator Mueller matrix polarimeter have demonstrated the validity of the proposed measurement configuration optimization method.

Directed self-assembly (DSA) and nanoimprint lithography (NIL) have been widely developed for low-cost nanoscale patterning. Although they are currently regarded as "alternative lithography," some papers show their potential to be candidates for next-generation lithography (NGL). To actualize the potential, the contribution of metrology engineers is necessary. Since the characteristics of the lithography techniques are different from those of conventional lithography, new metrology schemes correlated with each characteristic are required. In DSA of block copolymer (BCP), a guide is needed to control the direction and position of BCP. Therefore, it is necessary to monitor the relationship between the guide and the BCP pattern. Since the depth of guide or the coating thickness variation of BCP over guide influences the behavior of phase separation of BCP, 3D metrology becomes increasingly important. In NIL, residual resist thickness (RLT) underneath the pattern should be measured because its variation affects the CD variation of transferred pattern. 3D metrology is also important in NIL. Optical critical dimension (OCD) metrology will be a powerful tool for 3D metrology. In this work, some applications of OCD for alternative lithography have been studied. For DSA, we have tried to simultaneously monitor the guide and BCP pattern in a DSA-based contact hole shrinking process. Sufficient measurement accuracy for CD and shapes for guide and BCP patterns was achievable. For NIL, sufficient sensitivity to RLT measurement was obtained.

Directed Self Assembly (DSA) for contact layers is a challenging process in need of reliable metrology for tight process control. Key parameters of interest are guide CD, polymer CD, and residual polymer thickness at the bottom of the guide cavity. We show that Optical CD (OCD) provides the needed performance for DSA contact metrology. The measurement, done with a multi-channel spectroscopic reflectometry (SR) system, is enhanced through elements of a Holistic Metrology approach such as Injection and Hybrid Metrology.

This paper reports on an investigation to determine whether through-focus scanning optical microscopy (TSOM) is applicable to micrometer-scale through-silicon via (TSV) reveal metrology. TSOM has shown promise as an alternative inspection and dimensional metrology technique for FinFETs and defects. In this paper TSOM measurements were simulated using 546 nm light and applied to copper TSV reveal pillars with height in the 3 μm to 5 μm range and diameter of 5 μm. Simulation results, combined with white light interferometric profilometry, are used in an attempt to correlate TSOM image features to variations in TSV height, diameter, and sidewall angle (SWA). Simulations illustrate the sensitivity of Differential TSOM Images (DTI’s) using the metric of Optical Intensity Range (OIR), for 5 μm diameter and 5 μm height TSV Cu reveal structures, for variation of SWA (Δ = 2°, OIR = 2.35), height (Δ = 20 nm, OIR = 0.28), and diameter (Δ = 40 nm, OIR = 0.57), compared to an OIR noise floor of 0.01. In addition, white light interferometric profilometry reference data is obtained on multiple TSV reveal structures in adjacent die, and averages calculated for each die’s SWA, height, and diameter. TSOM images are obtained on individual TSV’s within each set, with DTI’s obtained by comparing TSV’s from adjacent die. The TSOM DTI’s are compared to average profilometry data from identical die to determine whether there are correlations between DTI and profilometry data. However, with several significant TSV reveal features not accounted for in the simulation model, it is difficult to draw conclusions comparing profilometry measurements to TSOM DTI’s when such features generate strong optical interactions. Thus, even for similar DTI images there are no discernible correlations to SWA, diameter, or height evident in the profilometry data. The use of a more controlled set of test structures may be advantageous in correlating TSOM to optical images.

In-line metrologies currently used in the semiconductor industry are being challenged by the aggressive pace of device scaling and the adoption of novel device architectures. In defect inspection, conventional bright field techniques will not likely be able to meet defect capture rate requirements beyond the 16 nm node. Electron beam-based inspection is able to meet resolution limits well below this node, but operates at a significantly lower throughput. It, therefore, has become necessary to explore alternative approaches with the potential to meet both resolution and throughput requirements. Critical dimension (CD) metrology, on the other hand, is less challenged by resolution than by the increasingly 3D nature of the information that needs to be collected from modern device structures. It is therefore valuable to explore metrology techniques that are sensitive to spatial variations across the entire volume of the interrogated feature. Through-focus scanning optical microscopy (TSOM) is a novel method that allows conventional optical microscopes to collect dimensional information down to the nanometer level by combining 2D optical images captured at several through-focus positions. This relatively simple technique is inexpensive and has high throughput, making it attractive for a variety of semiconductor metrology applications, such as CD, photomask, overlay, and defect metrologies. In this work, we expand on the analysis of TSOM as a potential technique for defect inspection and study its ability to characterize 3D high aspect ratio (HAR) features. For defect inspection applications, we extend the simulation space well beyond the 11 nm node, based on dense features with CDs ranging from 13 nm to 7 nm. The optical response of a variety of patterned defect modes, sizes, and heights was likewise explored under different polarization and wavelength illumination conditions. Results indicate TSOM has the ability to extract defect signal for most of the cases studied. Work on HAR features focused on exploring 3D sensitivity to features such as bottom CD, sidewall angle, and depth. HAR targets were studied using simulations down to the 11 nm node. Promising results were observed in terms of sensitivity to bottom CD, sidewall angle, and depth.

A non-linear phase retrieval algorithm is used to characterise the aberrations in an Extreme Ultraviolet (EUV) stepper. The retrieval is based on intensity measurement in a single plane in the focal volume. A statistical-based characterisation of the robustness of the algorithm with respect to the out-of-focus distance has been carried out. This allows to identify a measurement plane that is optimal for the phase retrieval and reduces the computation time and the complexity of the problem. Experimental results obtained in the visible spectrum range confirm the predictions of the simulations and are in a good agreement with an independent wavefront measurement. The phase retrieval method can be used to implement a dedicated adaptive optics system in a EUV stepper.

Measurement of the power spectral density (PSD) of a rough surface or feature involves large random and systematic errors. While random errors can be reduced by averaging together many PSDs, systematic errors can be reduced only by carefully studying and understanding the sources of these systematic errors. Using both analytical expressions and numerical simulations for the measurement of the PSD of line-edge roughness, three sources of systematic errors are evaluated: aliasing, leakage, and averaging. Exact and approximate expressions for each of these terms are derived over a range of roughness exponents, allowing a measured PSD to be corrected for its systematic biases. The smallest measurement bias is obtained when appropriate data windowing is used, and when the sampling distance is set to twice the measurement signal width. Uncorrected PSD measurements are likely to systematically bias the extracted roughness exponent to higher values.

With the advent of FinFETs, precise control of sidewall roughness (SWR) has taken on a new importance in semiconductor manufacturing. The sidewall of the fin is the largest area of contact between the gate and channel. Controlling this contact requires precise and accurate metrology, which in turn requires calibration. Developing a calibration standard for sidewall roughness is therefore vital. This paper describes initial work towards creating such a standard, by demonstrating mutually supporting reference metrology on a patterned roughness feature. To create the standard, photoresist features were patterned using a programmed and controlled line edge roughness (LER). Initial roughness data was obtained by critical dimension atomic force microscopy (CD-AFM), a conformal film was then deposited to provide contrast for transmission electron microscopy (TEM), and full 3D roughness information across the entire sidewall was acquired by TEM tomography. The following serves as proof of concept for using these two measurements to check each other, moving towards development of a usable sidewall roughness standard.

Surface roughness(SR) of the EUV resists exposed to EUV, ArF and KrF radiation has been investigated using three tools: spectroscopic ellipsometry (SE), AFM and SEM. The purpose of this paper is to do determine whether SE can effectively monitor the change in resist SR, and also whether we can see the effect of photon shot noise in resist patterning. EUV resists were coated on three blank wafers, and on the shot basis, exposed to different dose of each radiation. After completion of resist process, the SR was measured first with SE. Then the wafer was sliced into patches of different dose before AFM and SEM measurements were made. SE used effective medium approximation to calculate the roughness-layer thickness as a parameter for fitting to experimental data. Thus obtained thicknesses showed a monotonic correlation with AFM-measured roughness, indicating SE can be a fast, precise and nondestructive tool to evaluate resist SR, once being calibrated with AFM. In order to examine the photon shot noise effect on the resist pattern, all the steps of the resist process was kept the same except the exposure wavelength and its dose. SE results for the three exposures were compared over the full range of doses in common. The three roughness values near the dose to clear, Eclear, apparently provide an evidence that the photon shot noise played a significant role in our experiment.

The aim of this paper is to contribute to the understanding of the effects of noise on LER/LWR parameters when they are measured through the analysis of top-down CD-SEM images. To this end, first we present a methodology for the generation of synthesized CD-SEM images including resist lines with predetermined CD/pitch and LER/LWR parameters in which the noise level can be tuned at will. The sources of noise can be the shot noise of SEM electron beam (Poisson-type) and the microscope electronics (Gaussian-type). Then we use the generated CD-SEM images to evaluate three methods devised for the reduction of noise effects and the extraction of noise-free LER/LWR parameters. The first method (called fractal method) is presented for first time while the next two (model filtering and Power Spectral Density) have been already proposed and applied in literature. We compare the output of each method with the noise-less LER/LWR parameters for various noise levels, number of images and LER/LWR initial parameters and discuss their advantages and limitations.

Metrology of line-edge roughness (LER) or line-width roughness (LWR) reduced less than a few nanometers in recent advanced-process is one of issues because measured LER is strongly dependent on measurement conditions such as magnification and beam dose. It may happen that different organizations measure different LERs on an identical sample. By using an ultra-low LER sample we demonstrate intolerable change of measured LER between with and without necessary key-points in the measurement conditions of critical-dimension secondary electron microscope (CD-SEM).

One of the main challenges for lithography step is the overlay control. For the advanced technology node like 28nm and 14nm, the overlay budget becomes very tight. Two overlay techniques compete in our advanced semiconductor manufacturing: the Diffraction based Overlay (DBO) with the YieldStar S200 (ASML) and the Image Based Overlay (IBO) with ARCHER (KLA). In this paper we will compare these two methods through 3 critical production layers: Poly Gate, Contact and first metal layer. We will show the overlay results of the 2 techniques, explore the accuracy and compare the total measurement uncertainty (TMU) for the standard overlay targets of both techniques. We will see also the response and impact for the Image Based Overlay and Diffraction Based Overlay techniques through a process change like an additional Hardmask TEOS layer on the front-end stack. The importance of the target design is approached; we will propose more adapted design for image based targets. Finally we will present embedded targets in the 14 FDSOI with first results.

In image-based overlay (IBO) measurement, the measurement quality of various measurement spectra can be judged by quality indicators and also the ADI-to-AEI similarity to determine the optimum light spectrum. However we found some IBO measured results showing erroneous indication of wafer expansion from the difference between the ADI and the AEI maps, even after their measurement spectra were optimized. To reduce this inconsistency, an improved image calculation algorithm is proposed in this paper. Different gray levels composed of inner- and outer-box contours are extracted to calculate their ADI overlay errors. The symmetry of intensity distribution at the thresholds dictated by a range of gray levels is used to determine the particular gray level that can minimize the ADI-to-AEI overlay inconsistency. After this improvement, the ADI is more similar to AEI with less expansion difference. The same wafer was also checked by the diffraction-based overlay (DBO) tool to verify that there is no physical wafer expansion. When there is actual wafer expansion induced by large internal stress, both the IBO and the DBO measurements indicate similar expansion results. The scanning white-light interference microscope was used to check the variation of wafer warpage during the ADI and AEI stages. It predicts a similar trend with the overlay difference map, confirming the internal stress.

Scanning electron-microscope (SEM) has been successfully applied to CD measurement as promising tools for qualifying and controlling quality of semiconductor devices in in-line manufacturing process since 1985. Furthermore SEM is proposed to be applied to in-die overlay monitor in the local area which is too small to be measured by optical overlay measurement tools any more, when the overlay control limit is going to be stringent and have un-ignorable dependence on device pattern layout, in-die location, and singular locations in wafer edge, etc. In this paper, we proposed new overlay measurement and inspection system to make an effective use of in-line SEM image, in consideration of trade-off between measurement uncertainty and measurement pattern density in each SEM conditions. In parallel, we make it clear that the best hybrid overlay metrology is in considering each tool’s technology portfolio.

One of the main issues with overlay error metrology accuracy is the bias between results based on overlay (OVL) targets and actual device overlay error. In this study, we introduce the concept of Device Correlated Metrology (DCM), which is a systematic approach to quantifying and overcoming the bias between target-based overlay results and device overlay issues. For systematically quantifying the bias components between target and device, we introduce a new hybrid target integrating an optical OVL target with a device mimicking CD-SEM (Critical Dimension – Scanning Electron Microscope) target. The hybrid OVL target is designed to accurately represent the process influence found on the real device. In the general case, the CD-SEM can measure the bias between target and device on the same layer at AEI (After Etch Inspection) for all layers, the OVL between layers at AEI for most cases and at ADI (After Develop Inspection) for limited cases such as DPL (Double Patterning Lithography). The results shown demonstrate that for the new process compatible hybrid targets the bias between target and device is small, of the order of CD-SEM measurement uncertainty. Direct OVL measurements by CD-SEM show excellent correlation with optical OVL measurements in certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for imaging based OVL metrology methods using AIM or AIMid OVL targets, and scatterometry-based overlay methods such as SCOL (Scatterometry OVL). Future plans include broadening the hybrid target design to better mimic each layer’s process conditions such as pattern density. We are also designing hybrid targets for memory devices.

As device design rule has been made pattern size shrink, overlay control has become one of the most critical issues for semiconductor manufacturing. Advanced lithographic exposure tools, such as EUV and i-ArF scanners, require high-order overlay corrections. In conventional overlay metrology, several overlay targets are arranged in scribe area on product wafer. However, the number of measurement point is not sufficient for high-order overlay corrections and these positions are too far from device patterns to estimate its overlay. High-order overlay corrections should be calculated from overlay measurement data by using a considerable number of in-die targets near device pattern. In this case, smaller target area size is expected for advanced lithography. In this paper we introduce in-die overlay metrology by using critical dimension scanning electron microscope (CD-SEM). It has several advantages over a conventional optical overlay measurement tool, 1) the target area size can be set smaller than 5 x 5 μm, 2) the size and feature of measurement pattern can be set similar to device design, therefore WIS (Wafer Induced Shift) is assumed to be small, 3) TIS (Tool Induced Shift) by CD-SEM, which we measure, is small. Furthermore, we show repeatability and accuracy of the overlay measurement by CD-SEM. And overlay distribution measured by die-to-die can be verified by sufficient number of the dedicated targets in-die.

The understanding and control of stresses accumulated during device fabrication is becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for the management of overlay and depth of focus during lithography. This paper describes the use of a comprehensive stress inspection technology, the Coherent Gradient Sensing (CGS) interferometer, for the characterization of stress-induced overlay errors. Using CGS, stresses and wafer distortions induced by any upstream process (or series of processes) can be measured, and the relative contribution of stress-induced overlay associated with individual processes can be evaluated. The CGS technology has two key features that enable the application of stress metrology to lithographic overlay: 1) whole-wafer stress measurement with approximately 800,000 points on a 300mm wafer, 2) patterned wafer stress measurement that is highly insensitive to variations in device structures or materials, such that any location within a die or wafer can be characterized without the need for traditional test structures. Fundamentally, thin-plate theory relates the in-plane stresses in a thin film structure to in-plane strains and displacements. The in-plane displacements in the film due to stress are related to the lithographic overlay. The approach presented here demonstrates the relationship between stress gradients are related to in-plane displacements. Data from case-studies are presented that further shows the correlation between in-plane displacements, measured from wafer distortion and traditional measurement of overlay targets.

One of the main challenges related to the growing number of Litho layers and most specifically to Multi Patterning, is the ability to align to many layers at once. In the past things were simple, the alignment tree was set so that every layer aligns to one layer and at the most is measured versus two layers, such as contact to poly and Isolation. Today, even at the 20 nm node there are double and triple patterning for critical layers such as Isolation, poly, contact and Metal 1. This forces a much more complex alignment tree and Overlay (OVL) measurement. Layers are sometimes aligned to an average of previous layers, to different layers at different orientations and disposition is done based on several measurements. This growing challenge increases the number of Overlay measurements significantly, increases the target area and present the need to make many measurement from different layers consistent. Another challenge is the increased number of recipes and the need for flexible alignment tree scheme during development. These challenges are addressed by Multi layer targets such as Triple AIM, Multilayer AIMid and the Blossom and micro-Blossom targets where alignment marks from multiple patterning steps and layers were densely populated. A single OVL reading is calculated by the metrology tool on a selected pair or multiple pair average¹. Here we propose the Multi-Layer measurement that provides an additional degree of metrology and solution to these challenges: in one measurement several overlay results are achieved, the results are always self-consistent. It allows at the same measurement grab to look back and disposition previous layers after their processing was completed. It allows a flexible alignment tree without the need to add or change targets, even during ramp and production. It reduces the number of recipes that need to be created and managed. And it also reduces significantly the area needed for the targets. In this paper we will show recent results from IMEC, on Back-End (BE) stack of four layers including one double patterning layer. We compared several target sizes, showing that such a target can fit within the Indie requirements of 10x10 μm. Results show that there is not a lot of need to compromise on performance in order to get good Multi-Layer measurements. Eventually we will describe process compatible targets which are needed more in the Front End (FE) layers. Looking forward at the increased complexity needed for future nodes and multiple pitch splitting lithography, it is encouraging to see that for Overlay we can simplify metrology instead of making it follow the complexity trend.

We characterized the roughness and side wall morphology of lithographically produced nanostructures of resistmultilayer materials using the recently developed three-dimensional atomic force microscopy (3D-AFM), which has an independent Z scanner intentionally tilted to a certain angle access the sidewall. In order to produce different degrees of Line Edge Roughness (LER) in a given photoresist sample, we systematically varied the Aerial Image Contrast (AIC) at a constant dose for optically imaged resists. We describe herein the effects of AIC on KrF resists that were observed by using 3D-AFM and Critical Dimension-Scanning Electron Microscopy (CD-SEM). High-resolution sidewall images and line profiles obtained by the 3D-AFM technique demonstrate its advantages to characterize the shape and roughness of device patterns throughout the development and pattern transfer process. Taken together, we demonstrate that AFM imaging can identify a trend in Sidewall Roughness (SWR) as a function of AIC effects on photoresist sample, and CDSEM imaging provided supporting evidence to establish the LER trend.

A new method for calculating critical dimension (CDs) at the top and bottom of three-dimensional (3D) pattern profiles from a critical-dimension scanning electron microscope (CD-SEM) image, called as “T-sigma method”, is proposed and evaluated. Without preparing a library of database in advance, T-sigma can estimate a feature of a pattern sidewall. Furthermore, it supplies the optimum edge-definition (i.e., threshold level for determining edge position from a CDSEM signal) to detect the top and bottom of the pattern. This method consists of three steps. First, two components of line-edge roughness (LER); noise-induced bias (i.e., LER bias) and unbiased component (i.e., bias-free LER) are calculated with set threshold level. Second, these components are calculated with various threshold values, and the threshold-dependence of these two components, “T-sigma graph”, is obtained. Finally, the optimum threshold value for the top and the bottom edge detection are given by the analysis of T-sigma graph. T-sigma was applied to CD-SEM images of three kinds of resist-pattern samples. In addition, reference metrology was performed with atomic force microscope (AFM) and scanning transmission electron microscope (STEM). Sensitivity of CD measured by T-sigma to the reference CD was higher than or equal to that measured by the conventional edge definition. Regarding the absolute measurement accuracy, T-sigma showed better results than the conventional definition. Furthermore, T-sigma graphs were calculated from CD-SEM images of two kinds of resist samples and compared with corresponding STEM observation results. Both bias-free LER and LER bias increased as the detected edge point moved from the bottom to the top of the pattern in the case that the pattern had a straight sidewall and a round top. On the other hand, they were almost constant in the case that the pattern had a re-entrant profile. T-sigma will be able to reveal a re-entrant feature. From these results, it is found that T-sigma method can provide rough cross-sectional pattern features and achieve quick, easy and accurate measurements of top and bottom CD.

Imaging of suspended silicon nanonwires (SiNW) by SEM reveals that some of the SiNW are buckled. Buckling can impact device performance and it is therefore important to characterize this phenomenon. Measuring the buckling of suspended silicon nanowires (SiNW) poses significant challenges: (1) Small dimensions - SiNW are made with diameters ranging from about 3 to 10 nm and the buckling is of a similar scale. (2) Accurate height measurements – buckling is a three dimensional phenomena.
To meet these challenges a new height map reconstruction technique was introduced, using the CDSEM side detectors signal. Measuring pixel by pixel position in X, Y and Z (height) dimensions, we can obtain the buckling vector gradient along the wire in three dimensions. In this paper we present: (1) A description of the height map reconstruction technique used. (2) Three dimensional characterization of SiNW: (a) SiNW buckling measurements (b) Characterization of buckling as a function of the SiNW length and width.

As semiconductor industry moves towards advanced technology node, requirement for tighter Critical Dimension (CD) control constantly raises the bar for CD metrology. Yet despite various intrinsic bias origins, CD-SEM is still serving as the workhorse and ‘go to’ metrology mean for inline CD control in modern IC fabrication day in and day out. Such confidence comes from extensive studies around the underlying physics of SEM as major bias types are all marked as 'accountable' and some even 'predictable' nowadays. Still there are times when unexpected metrology results slip through with no obvious trace leading to any well established theories. And it is none the less necessary and challenging to single out the root cause from the complex physics models. Such a case is presented in this work. A reproducible CD diving behavior on the scale of 0.4~0.8nm during the very first one or two measurements by SEM on Poly-Si sample is described and verified. Various experiments are conducted to identify the physical origin. We propose that this ‘first measurement effect (FME)’ is related to SEM proximity shadowing and e-beam seasoning on pattern sidewall material.

The novel method of sub-nanometer uncertainty for the line width measurement and line profile measurement using STEM (Scanning Transmission Electron Microscope) images is proposed to calibrate CD-SEM line width measurement and standardization of line profile measurement as reference metrology. In accordance with the proposed method, we already have established the methodology of Si line profile and line width measurement for reference metrology. In this article, we applied the proposed method to edge determination methodology of the photoresist feature. Using the proposed method, a specimen of photoresist feature is coated with metal, and then it is sliced as a thin specimen of 100 nm thickness by FIB (Focused Ion Beam) micro sampling system. Then the dark-field cross-sectional images of the specimen are obtained by STEM. The edge position of the photoresist is defined at the distance of half metal coating thickness from the peak positions of metal coating area. Then the detected line profiles are compared with the measurement results by CD-AFM. From series of analyses, we established the edge detection methodology of photoresist feature for reference metrology.

The demand for growing precision of shrinking structures on photolithographic masks makes fast, reliable, and robust testing tools necessary. Scanning electron microscopes (SEM) therefore are standard metrology tools for critical dimension (CD) measurements. An algorithm that is independent of `a priory knowledge of material parameters of the nanostructure is employed to determine CD. The analysis procedure is optimized in particular for fast scanning and small current probing beams to measure line structures on photolithographic masks. The edge characterization with SEM has been complemented with AFM measurements. In particular, the width of the edge transition estimated from height and slope of AFM topography information has been compared to that obtained from SEM scans. Height and slope are unidirectional parameters, so their determination does not need tip deconvolution. To characterize corner roundings the convolution process has to be understood. Therefore, simulations of physical processes of atomic force microscopy have been carried out to understand the influence of force gradients on the probing process causing a double convolution of tip and sample geometry, firstly of the geometries directly and secondly because of the changing interaction due to changing geometries. The analysis method to estimate edge parameters from SEM images works stable for line widths down to 50 nm. A long term stability down to ±0.6 nm has been observed.

In recent years, semiconductor makers have been developing 1Xnm HP (Half Pitch) node devices. It is a requirement for CD-SEM to improve measurement uncertainty of not only the basic short-term repeatability, but also of the long-term stability and tool-to-tool matching. A conventional method called “Common Site Method” has been used to evaluate the uncertainty of CD-SEM measurement. In this method, target patterns on an identical sample and identical measurement point, which is the common site, is measured repeatedly. Common Site Method has possible instability factors as follows; 1) Carry-over due to contamination and/or charging caused by repeated measurement on the same points 2) Dimensional variation caused by the use of non-identical patterns between the groups These issues cannot be solved by averaging the results from many measurement points. In this paper we introduce a new method: “Fresh Site Method” to check the long-term stability and tool-to-tool matching with high precision. In this method, a target on arbitrary point extracted randomly from a large area of dense pattern is measured on multiple dies. Precision of the measurement is improved by increasing the number of dies for the measurement because influence of the CD non-uniformity among the dies is reduced by the averaging effect of the measurement points. In addition, “Macro-Area Measurement” method^[1][2] can reduce both the measurement uncertainty, caused by sample variation, and measurement time. As a result, the precision of CD-SEM monitoring using Fresh Site Method with Macro-Area Measurement produce sufficient results for the evaluation of CD-SEM measurement uncertainty, realizing a reproducibility performance below 0.1nm.

Current process tool performances are getting significantly enhanced by the adoption of advanced process correction application such as DoseMapper for CD or high order overlay correction for overlay. These process control capabilities need appropriate sampling to be efficient. Usually for in field metrology sampling we used to operate with metrology targets placed inside the scribe lines, however in this case the larger the chip the less scribe lines we have and the less relevant is the intrafield sampling. As ST is an IDM we have the opportunity to share with our design division this process control problematic. Since 45/40nm node we have started to put in place the so-called EMET (Embedded Metrology Target) strategy which consists in in-design metrology targets placement. Initially these targets were placed using tiling tools but it soon appeared to be not efficient and even impossible when we talk about targets involving complex metal stack. This papers talks about our current embedded metrology target strategy which has been adapted to enable appropriate target placement for CD and overlay for all critical layers from active to via/metal’s. Solutions needed to be put in place to (i) keep the circuit safe by using Design Rule clean metrology targets, (ii) be highly visible by the designers by placing targets at chip floor planning definition (iii) be upgradable by enabling target re-designs without impact on chip design version.

This paper describes the joint development and optimization of an advanced critical dimension (CD) control methodology at IBM’s 300 mm semiconductor facility. The work is initially based on 22 nm critical level gate CD control, but the methodology is designed to support both the lithography equipment (1.35 NA scanners) and processes for 22, 20, 18, and 14 nm node applications. Specifically, this paper describes the CD uniformity of processes with and without enhanced CD control applied. The control methodology is differentiated from prior approaches¹ by combining independent process tool compensations into an overall CD dose correction signature to be applied by the exposure tool. In addition, initial investigations of product specific focus characterization and correction are also described.

As feature size shrinkage in semiconductor device progress, process fluctuation, especially focus strongly affects device performance. Because focus control is an ongoing challenge in optical lithography, various studies have sought for improving focus monitoring and control. Focus errors are due to wafers, exposure tools, reticles, QCs, and so on. Few studies are performed to minimize the measurement errors of auto focus (AF) sensors of exposure tool, especially when processed wafers are exposed. With current focus measurement techniques, the phase shift grating (PSG) focus monitor 1) has been already proposed and its basic principle is that the intensity of the diffraction light of the mask pattern is made asymmetric by arranging a π/2 phase shift area on a reticle. The resist pattern exposed at the defocus position is shifted on the wafer and shifted pattern can be easily measured using an overlay inspection tool. However, it is difficult to measure shifted pattern for the pattern on the processed wafer because of interruptions caused by other patterns in the underlayer. In this paper, we therefore propose "SEM-PSG" technique, where the shift of the PSG resist mark is measured by employing critical dimension-scanning electron microscope (CD-SEM) to measure the focus error on the processed wafer. First, we evaluate the accuracy of SEM-PSG technique. Second, by applying the SEM-PSG technique and feeding the results back to the exposure, we evaluate the focus accuracy on processed wafers. By applying SEM-PSG feedback, the focus accuracy on the processed wafer was improved from 40 to 29 nm in 3σ.

Shrinking semiconductor device nodes are driving continuous overlay improvement. This, in turn, is driving broad adoption of high-order control, especially at today’s advanced nodes. There are two main categories of high-order control: wafer alignment, and process correction. This paper focuses on the inherent disadvantages of high-order process correction models due to data noise and the deterioration of model term stability. In our study, we observed that linear model terms became unstable after the implementation of high-order process corrections, and observed correlations between model parameters. We investigated correlations for both linear and high-order models, and found that all correlation combinations for the linear model had a Pearson correlation coefficient below 0.25, while 22% of the correlation combinations for third order polynomial parameters had a correlation coefficient greater than 0.5. A high correlation coefficient indicates that similar overlay signatures on the wafer can be modeled by different terms, and that there is instability of model terms in the presence of data noise. Advanced process control (APC) corrections are based on historical lot-to-lot model terms, and are applied to each new lot to be exposed. The instability of model terms adversely affects the precise prediction for a new lot. An alternative solution is to use cascading analysis, which calculates the model parameters sequentially using a series of models. The inherent disadvantage of cascading analysis is loss of model fidelity; however, the robust data filtering scheme used in cascading analysis ensures better overlay stability, as shown in the results of this study. This study shows that cascading analysis consistently yields a lower correlation within and across a batch of lots, but with improved overlay control. Several methods of cascading analysis were investigated in terms of the sequence of linear and high-order modeling. This was done to determine the optimal method for implementing cascading analysis, and to determine the implications of cascading analysis in today’s high-volume mass production fabrication facility.

This paper will examine the future for critical dimension (CD) metrology. First, we will present the extensive list of applications for which CD metrology solutions are needed, showing commonalities and differences among the various applications. We will then report on the expected technical limits of the metrology solutions currently being investigated by SEMATECH and others in the industry to address the metrology challenges of future nodes, including conventional CD scanning electron microscopy (CD-SEM) and optical critical dimension (OCD) metrology and new potential solutions such as He-ion microscopy (HeIM, sometimes elsewhere referred to as HIM), CD atomic force microscopy (CD-AFM), CD small-angle x-ray scattering (CD-SAXS), high-voltage scanning electron microscopy (HV-SEM), and other types. A technical gap analysis matrix will then be demonstrated, showing the current state of understanding of the future of the CD metrology space.

This paper reports recent progress in using Atomic Force Microscopy as a defect review tool for patterned wafers. The key developments in the AFM technology are substantial scan speed improvements and the ability to reach feature bottom-CDs in a narrow trench. The latter is accomplished by controlling the tip-sample interaction via the short-range interaction force. Narrow trenches with vertical side wall angles comparable to current FinFET dimensions were imaged using the AFM, where imaging speeds for this sample reached about 0.2 frames per second, providing quantified topographic data for key features of the trenches. The sub-10 nm resolution data of high speed AFM demonstrates the technology as a viable solution for defect review.

In this work, we report the first demonstration of scatterometry Optical Critical Dimension (OCD) characterization on advanced Ge Multi-Gate Field-Effect Transistor (MuGFET) or FinFET formed on a Germanium-on-Insulator (GeOI) substrate. Two critical process steps in the Ge MuGFET process flow were investigated, i.e. after Ge Fin formation, and after TaN gate stack etching process. All key process variations in the test structures were successfully monitored by the floating or fitting parameters in the OCD models. In addition, excellent static repeatability, with 3σ lower than 0.12 nm, was also achieved. The measurement results from OCD were also compared with both Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM) measurements. Excellent correlation with both SEM and TEM was achieved by employing OCD characterization, confirming scatterometry OCD as a promising metrology technique for next generation multi-gate transistor with an advanced channel material.

Recently, there has been significant interest in so-called Hybrid or Holistic Metrology, the practice of combining measurements from multiple sources in order to improve the estimation of one or more critical parameters. There also has been significant research in capturing and modeling the hierarchical spatial variability of CDs at the die, wafer, and lot level. However, the information inherent in spatial variability models has not been used towards improving the accuracy/precision of CD estimates. In this paper, we review the current trends in Hybrid Metrology and Spatial Variability Modeling, and provide a simple example based on the work of Zhang et al.¹ that illustrates how we can incorporate spatial information for improved measurement estimates.

We report a strong direct correlation (above 0.9) between conventional transistor-level parametrics typically used in the industry to monitor and control intra-die variability (IDV) and a novel, non-contact performance-based metrology (PBM), technology that was integrated into an active die on a 32nm SOI advanced logic product platform. We demonstrate a PBM test structure measurement repeatability of less than 0.4%. In this work, we also demonstrate the compatibility of integrating the PBM technology into an advanced CMOS process flow with no added processing or steps, as well as its footprint scalability. The data suggests that the non-contact PBM technology meets all prerequisites for its deployment as a standard, within-product IDV monitor.