This PDF file contains the front matter associated with SPIE Proceedings Volume 8880, including the Title Page, Copyright information, Table of Contents, Invited Panel Discussion, and Conference Committee listing.

The current era of semiconductor research is heavily dependent on the incorporation of new materials into structures measured in nanometers. We require complexity at not only the functional level but complexity in how these functions work together to make better products. The mask set is the critical element in managing that complexity in a cost effective manner but mask making today is challenged to key up with demands. For the next decade, these trends are expected to continue and will suffice to improve the traditional metrics of performance-power and costs. There are many choices to be made but a rich future lies ahead of us.

Line edge roughness (LER) or line width roughness (LWR) is a fundamental challenge in the semiconductor industry. LWR on transistor gate length is a dominant parameter for determining the variability of threshold voltage, on-current and off-current, and LER on interconnect impacts breakdown voltages. Integrated circuit (IC) scaling enabled by lithography is the technology to increase device density and improve performance. However, scaling below 32nn technology node induces short-channel effect (SCE) because of the short distance between the transistor source and the drain. Final LER on the working layer results from several processes, and, thus, LER controls rely on lithography, resist properties, post-resist-development processing, pattern transfer methods, and photomask LER. Now, pattern generation is main source of LER, where short exposure wavelength and consecutive low photon numbers result in discrete photon flux and shot noise, causing high LER. Extreme ultraviolet lithography (EUVL) uses shorter wavelengths and a lower dose than the current 193 nm lithography, making LWR one of the three most critical challenges. Characterization of LER is also a challenge. The current rms method is broadly used; however, this approach is not enough and a better method has yet to be established.

EUV mask substrates, made of titania-doped fused silica, ideally require sub-Angstrom surface roughness, sub-30 nm flatness, and no bumps/pits larger than 1 nm in height/depth. To achieve the above specifications, substrates must undergo iterative global and local polishing processes. Magnetorheological finishing (MRF) is a local polishing technique which can accurately and deterministically correct substrate figure, but typically results in a higher surface roughness than the current requirements for EUV substrates. We describe a new super-fine MRF® polishing fluid whichis able to meet both flatness and roughness specifications for EUV mask blanks. This eases the burden on the subsequent global polishing process by decreasing the polishing time, and hence the defectivity and extent of figure distortion.

The 50keV ebeam exposure of EUV blanks leads to additional electron backscattering from the tantalum layer and the mirror portion of the blank substrate that cannot be adequately corrected by in-tool algorithms. Coupling this additional backscatter with process effects, such as develop and etch micro/macro loading, results in significant systematic Critical Dimension (CD) errors for through pitch and linearity patterns on EUV masks. In wafer production EUV masks are targeted as single layer exposure, which requires extremely stringent CD control. The systematic CD errors can easily exceed the CD requirements of a typical EUV mask, facilitating the need for a correction scheme or mask process correction (MPC). AMTC and GLOBALFOUNDRIES have started a program to evaluate MPC solutions and drive improvements. Working closely with companies that provide solutions for ebeam and process modelling along with the corresponding correction, we have completed several iterations of MPC evaluations. Specifically, we have tested different equipment, processes and process partitioning for model calibration including a verification of the results. We report on the results of these evaluations, which include simulation of available models, as well as verification data from mask prints. We conclude by summarizing the current capabilities of available MPC solutions and present the remaining gaps for model and correction accuracy as well as the remaining questions for fully implementing MPC into the process landscape.

As optical lithography continues to extend into low-k1 regime, resolution of mask patterns continue to diminish, and so do mask defect requirements due to increasing MEEF. Post-inspection, mask defects have traditionally been classified by operators manually based on visual review. This approach may have worked down to 65/55nm node layers. However, starting 45nm and smaller nodes, visually reviewing 50 to sometimes 100s of defects on masks with complex modelbased OPC, SRAF, and ILT geometries, is error-prone and takes up valuable inspection tool capacity. Both these shortcomings in manual defect review are overcome by adoption of the computational solution called Automated Defect Classification (ADC) wherein mask defects are accurately classified within seconds and consistent to guidelines used by production technicians and engineers.

This article presents results from an algorithm that can automatically quantify critical dimensions in images from Mask inspection tools with a very high level of accuracy. Using such an algorithm the inspection systems can be run with much tighter settings, resulting in more false defect detections that can then be filtered using the algorithm described here. Such a technique could potentially make the inspection system suitable for inspecting photo-masks beyond its practical limitation.

As optical lithography continues to extend into low-k1 regime, resolution of mask patterns continues to diminish. The adoption of RET techniques like aggressive OPC, sub-resolution assist features combined with the requirements to detect even smaller defects on masks due to increasing MEEF, poses considerable challenges for mask inspection operators and engineers. Therefore a comprehensive approach is required in handling defects post-inspections by correctly identifying and classifying the real killer defects impacting the printability on wafer, and ignoring nuisance defect and false defects caused by inspection systems. This paper focuses on the results from the evaluation of Automatic Defect Classification (ADC) product at the SMIC mask shop for the 40nm technology node. Traditionally, each defect is manually examined and classified by the inspection operator based on a set of predefined rules and human judgment. At SMIC mask shop due to the significant total number of detected defects, manual classification is not cost-effective due to increased inspection cycle time, resulting in constrained mask inspection capacity, since the review has to be performed while the mask stays on the inspection system. Luminescent Technologies Automated Defect Classification (ADC) product offers a complete and systematic approach for defect disposition and classification offline, resulting in improved utilization of the current mask inspection capability. Based on results from implementation of ADC in SMIC mask production flow, there was around 20% improvement in the inspection capacity compared to the traditional flow. This approach of computationally reviewing defects post mask-inspection ensures no yield loss by qualifying reticles without the errors associated with operator mis-classification or human error. The ADC engine retrieves the high resolution inspection images and uses a decision-tree flow to classify a given defect. Some identification mechanisms adopted by ADC to characterize defects include defect color in transmitted and reflected images, as well as background pattern criticality based on pattern topology. The final classification uses a matrix decision approach for achieving the final defect disposition. As a first step for qualifying ADC for high volume production, the defect classification results obtained with ADC are compared to the operator classification. Matching rates of greater than 90% were achieved when compared to operator defect classifications. Moreover, no critical defect has been missed. ADC performance was proven to be qualified for deployment in full volume mask manufacturing production flow.

IC fabs inspect critical masks on a regular basis to ensure high wafer yields. These requalification inspections are costly for many reasons including the capital equipment, system maintenance, and labor costs. In addition, masks typically remain in the “requal” phase for extended, non-productive periods of time. The overall “requal” cycle time in which reticles remain non-productive is challenging to control. Shipping schedules can slip when wafer lots are put on hold until the master critical layer reticle is returned to production. Unfortunately, substituting backup critical layer reticles can significantly reduce an otherwise tightly controlled process window adversely affecting wafer yields. One major requal cycle time component is the disposition process of mask inspections containing hundreds of defects. Not only is precious non-productive time extended by reviewing hundreds of potentially yield-limiting detections, each additional classification increases the risk of manual review techniques accidentally passing real yield limiting defects. Even assuming all defects of interest are flagged by operators, how can any person's judgment be confident regarding lithographic impact of such defects? The time reticles spend away from scanners combined with potential yield loss due to lithographic uncertainty presents significant cycle time loss and increased production costs. Fortunately, a software program has been developed which automates defect classification with simulated printability measurement greatly reducing requal cycle time and improving overall disposition accuracy. This product, called ADAS (Auto Defect Analysis System), has been tested in both engineering and high-volume production environments with very successful results. In this paper, data is presented supporting significant reduction for costly wafer print checks, improved inspection area productivity, and minimized risk of misclassified yield limiting defects.

To prevent catastrophic failures during wafer manufacturing, mask manufacturers employ sophisticated reticle inspection systems to examine every image on every reticle to identify defects. These advanced systems inspect at resolutions typically 3x higher at the reticle-plane than advanced wafer scanners; thus enabling them to detect the small defects necessary to ensure reticle quality. The most thorough inspection is done using a reticle-to-database comparison that ensures the reticle pattern matches the design pattern. For high defect sensitivity, the database must be carefully modeled to exactly match the reticle pattern. Further, sub-resolution OPC shapes are often at the limit of the mask manufacturing process, which adds subtle variations on such shapes across the reticle. These modeling errors and process variations can cause high numbers of unwanted detections, thereby limiting inspection system defect detection sensitivity.[1] OPC designs are expected to become more aggressive for future generations and may stress the performance of current reticle inspection systems. To systematically assess the capability of various inspection approaches and identify needed areas for improvement, a new “Nightmare” test reticle has been designed by IBM. The test reticle contains various sizes and shapes of sub-resolution features that might appear on reticle generations from today’s 22nm to future 7nm. It also contains programmed defects to assess defect detection capability of current and future generation inspection systems. This paper will discuss the design of the “Nightmare” test reticle, and the inspection results of the current generation reticle inspection methods with emphasis on both inspectability and defect sensitivity. The subresolution features will be ranked according to importance for advanced OPC design. The reticle will also be evaluated using wafer print simulation so lithographic impact of features and defects can be measured and compared against inspection approaches and results.

Computational lithography solutions rely upon accurate process models to faithfully represent the imaging system output for a defined set of process and design inputs. These models rely upon the accurate representation of multiple parameters associated with the scanner and the photomask. Many input variables for simulation are based upon designed or recipe-requested values or independent measurements. It is known, however, that certain measurement methodologies, while precise, can have significant inaccuracies. Additionally, there are known errors associated with the representation of certain system parameters. With shrinking total CD control budgets, appropriate accounting for all sources of error becomes more important, and the cumulative consequence of input errors to the computational lithography model can become significant. In this work, we examine via simulation, the impact of errors in the representation of photomask properties including CD bias, corner rounding, refractive index, thickness, and sidewall angle. The factors that are most critical to be accurately represented in the model are cataloged. CD bias values are based on state of the art mask manufacturing data and other variables changes are speculated, highlighting the need for improved metrology and communication between mask and OPC model experts. The simulations are done by ignoring the wafer photoresist model, and show the sensitivity of predictions to various model inputs associated with the mask. It is shown that the wafer simulations are very dependent upon the 1D/2D representation of the mask and for 3D, that the mask sidewall angle is a very sensitive factor influencing simulated wafer CD results.

As the technology node keeps shrinking down to sub-28 nm, mask topography (Mask3D) effect is one of the most influential factors to draw intensive research lately. To build a successful Mask3D compact model, the runtime efficiency, accuracy and the flexibility to handle various geometry patterns are the three most important criterion to fulfill. Different approaches have been tried to resolve the difficulties in the full-chip modeling, but so far none of the existing Mask3D modeling methods have succeeded in meeting all the three criterion at the same time. It is often seen that an existing Mask3D model to succeed in one or two criteria, but fails in the rest. In this paper, we propose our innovative full chip Mask3D modeling method to successfully handle the above criterion at the same time. To our best of knowledge, it is the first ever Mask3D modeling in literature that is be able to achieve this goal. In our modeling flow, we first analyze the Mask3D effect by using rigorous simulation as the reference and generate edge-based kernels to mimic the Mask3D effect near the feature boundaries. The flexibility of handling the kernel helps us enable the support for all-angle patterns and be extendable for edge coupling effect and off-axis illumination. Our experimental results show that with only less than 30% runtime overhead compared to the conventional Mask2D model, we are able to achieve less than 0.8 nm CD RMS on the flexible feature patterns. An ILT-based OPC and simulation result is provided to validate the capability of all-angle support of our proposed model.

Although extreme ultraviolet lithography (EUVL) remains a promising candidate for semiconductor device manufacturing of the 1x nm half pitch node and beyond, many technological burdens have to be overcome. The “field edge effect” in EUVL is one of them. The image border region of an EUV mask,also known as the “black border” (BB), reflects a few percent of the incident EUV light, resulting in a leakage of light into neighboring exposure fields, especially at the corner of the field where three adjacent exposures take place. This effect significantly impacts on CD uniformity (CDU) across the exposure field. To avoid this phenomenon, a light-shielding border is introduced by etching away the entire absorber and multi-layer (ML)at the image border region of the EUV mask. In this paper, we present a method of modeling the field edge effect (also called the BB effect) by using rigorous lithography simulation with a calibrated resist model. An additional “flare level” at the field edge is introduced on top of the exposure tool flare map to account for the BB effect. The parameters in this model include the reflectivity and the width of the BB, which are mainly determining the leakage of EUV light and its influence range, respectively. Another parameter is the transition width which represents the half shadow effect of the reticle masking blades. By setting the corresponding parameters, the simulation results match well the experimental results obtained at the imec’s NXE:3100 EUV exposure tool. Moreover, these results indicate that the out-of-band (OoB) radiation also contributes to the CDU. Using simulation we can also determine the OoB effect rigorouslyusing the methodology of an “effective mask blank”. The study in this paper demonstrates that the impact of BB and OoB effects on CDU can be well predicted by simulations.

With the minimum feature size keeps shrinking, there are increasing difficulties to print these small features using one exposure (LE) or double exposures (LELE). To resolve the inherent physical limitations for current lithography techniques, triple patterning lithography (LELELE) has been widely recognized as one the most promising options for 14/10nm technology node. For triple patterning lithography (TPL), the designers are more interested in finding a decomposition with none of the three masks overwhelms the other. This color balancing issue is of crucial importance to ensure that consistent and reliable printing qualities can be achieved. In our previous work,18 a simple color balancing scheme is proposed to handle designed without stitches, which is not capable of handling complex designs with stitches. In this paper, we further extend the previous approach to be able to simultaneously optimizing the number of stitches and balancing the color usage in the three masks. This new approach is very efficient and robust, and guarantees to find a color balancing decomposition while achieving the optimal number of stitches. For the largest benchmark with over 10 million features, experimental results show that the new approach achieves almost perfect color balancing with reasonable runtime.

The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry’s transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

A comprehensive survey was sent to merchant and captive mask shops to gather information about the mask industry as an objective assessment of its overall condition. 2013 marks the 12th consecutive year for this process. Historical topics including general mask profile, mask processing, data and write time, yield and yield loss, delivery times, maintenance, and returns were included and new topics were added. Within each category are multiple questions that result in a detailed profile of both the business and technical status of the mask industry. While each year’s survey includes minor updates based on feedback from past years and the need to collect additional data on key topics, the bulk of the survey and reporting structure have remained relatively constant. A series of improvements is being phased in beginning in 2013 to add value to a wider audience, while at the same time retaining the historical content required for trend analyses of the traditional metrics. Additions in 2013 include topics such as top challenges, future concerns, and additional details in key aspects of mask masking, such as the number of masks per mask set per ground rule, minimum mask resolution shipped, and yield by ground rule. These expansions beyond the historical topics are aimed at identifying common issues, gaps, and needs. They will also provide a better understanding of real-life mask requirements and capabilities for comparison to the International Technology Roadmap for Semiconductors (ITRS).

As optical lithography continues to extend into sub-0.35 k1 regime, mask defect inspection and subsequent review has become tremendously challenging, and indeed the largest component to mask manufacturing cost. The routine use of various resolution enhancement techniques (RET) have resulted in complex mask patterns, which together with the need to detect even smaller defects due to higher MEEFs, now requires an inspection engineer to use combination of inspection modes. This is achieved in 193nm Aera^TM mask inspection systems wherein masks are not only inspected at their scanner equivalent aerial exposure conditions, but also at higher Numerical Aperture resolution, and special reflected-light, and single-die contamination modes, providing better coverage over all available patterns, and defect types. Once the required defects are detected by the inspection system, comprehensively reviewing and dispositioning each defect then becomes the Achilles heel of the overall mask inspection process. Traditionally, defects have been reviewed manually by an operator, which makes the process error-prone especially given the low-contrast in the convoluted aerial images. Such manual review also limits the quality and quantity of classifications in terms of the different types of characterization and number of defects that can practically be reviewed by a person. In some ways, such manual classification limits the capability of the inspection tool itself from being setup to detect smaller defects since it often results in many more defects that need to be then manually reviewed. Paper 8681-109 at SPIE Advanced Lithography 2013 discussed an innovative approach to actinic mask defect review using computational technology, and focused on Die-to-Die transmitted aerial and high-resolution inspections. In this approach, every defect is characterized in two different ways, viz., quantitatively in terms of its print impact on wafer, and qualitatively in terms of its nature and origin in the mask manufacturing process. The latter characterization qualifies real defect signatures, such as pin-dots or pin-holes, extrusions or intrusions, assist-feature or dummy-fill defects, writeerrors or un-repairable defects, chrome-on-shifter or missing chrome-from-shifter defects, particles, etc., and also false defect signatures, such as those due to inspection tool registration or image alignment, interlace artifacts, CCD camera artifacts, optical shimmer, focus errors, etc. Such qualitative characterization of defects has enabled better inspection tool SPC and process defect control in the mask shop. In this paper, the same computational approach to defect review has been extended to contamination style defect inspections, including Die-to-Die reflected, and non Die-to-Die or single-die inspections. In addition to the computational methods used for transmitted aerial images, defects detected in die-to-die reflected light mode are analyzed based on special defect and background coloring in reflected-light, and other characteristics to determine the exact type and severity. For those detected in the non Die-to-Die mode, only defect images are available from the inspection tool. Without a reference, i.e., defect-free image, it is often difficult to determine the true nature or impact of the defect in question. Using a combination of inspection-tool modeling and image inversion techniques, Luminescent’s LAIPH^TM system generates an accurate reference image, and then proceeds with automated defect characterization as if the images were simply from a die-to-die inspection. The disposition of contamination style defects this way, filters out >90% of false and nuisance defects that otherwise would have been manually reviewed or measured on AIMS^TM. Such computational defect review, unifying defect disposition across all available inspection modes, has been imperative to ensuring no yield losses due to errors in operator defect classification on one hand, and on the other, has enhanced defect characterization and detection capability of the inspection platform itself notwithstanding the number of defects detected in the process.

The fast pace of MOSFET scaling is accelerating the introduction of smaller technology nodes to extend CMOS beyond 20nm as required by Moore’s law. To meet these stringent requirements, the industry is seeing an increase in the number of critical layers per reticle set as it move to lower technology nodes especially in a high volume manufacturing operation. These requirements are resulting in reticles with higher feature densities, smaller feature sizes and highly complex Optical Proximity Correction (OPC), built with using new absorber and pellicle materials. These rapid changes are leaving a gap in maintaining these reticles in a fab environment, for not only haze control but also the functionality of the reticle. The industry standard of using wet techniques (which uses aggressive chemicals, like SPM, and SC1) to repel reticles can result in damage to the sub‐resolution assist features (SRAF’s), create changes to CD uniformity and have potential for creating defects that require other means of removal or repair. Also, these wet cleaning methods in the fab environment can create source for haze growth. Haze can be controlled by: 1) Chemical free (dry) reticle cleaning, 2) In‐line reticle inspection in fab, and 3) Manage the environment where reticles are stored. In this paper we will discuss a dry technique (chemical free) to remove pellicle adhesive residue from advanced optical reticles. Samsung Austin Semiconductors (SAS), jointly worked with Eco‐Snow System (a division of RAVE N.P., Inc.) to evaluate the use of Dry Reactive Gas (DRG) technique to remove pellicle adhesive residue on reticles. This technique can significantly reduce the impact to the critical geometry in active array of the reticle, resulting in preserving the reticle performance level seen at wafer level. The paper will discuss results on the viability of this technique used on advanced reticles.

193nm binary photomasks are still used in the semiconductor industry for the lithography of some critical layers for the nodes 90nm and 65nm, with high volumes and over long periods. However, these 193nm binary photomasks can be impacted by a phenomenon of chrome oxidation leading to critical dimensions uniformity (CDU) degradation with a pronounced radial signature. If not detected early enough, this CDU degradation may cause defectivity issues and lower yield on wafers. Fortunately, a standard cleaning and repellicle service at the mask shop has been demonstrated as efficient to remove the grown materials and get the photomask CD back on target.Some detection methods have been already described in literature, such as wafer CD intrafield monitoring (ACLV), giving reliable results but also consuming additional SEM time with less precision than direct photomask measurement. In this paper, we propose another approach, by monitoring the CDU directly on the photomask, concurrently with defect inspection for regular requalification to production for wafer fabs. For this study, we focused on a Metal layer in a 90nm technology node. Wafers have been exposed with production conditions and then measured by SEM-CD. Afterwards, this photomask has been measured with a SEM-CD in mask shop and also inspected on a KLA-Tencor X5.2 inspection system, with pixels 125 and 90nm, to evaluate the Intensity based Critical Dimension Uniformity (iCDU) option. iCDU was firstly developed to provide feed-forward CDU maps for scanner intrafield corrections, from arrayed dense structures on memory photomasks. Due to layout complexity and differing feature types, CDU monitoring on logic photomasks used to pose unique challenges.The selection of suitable feature types for CDU monitoring on logic photomasks is no longer an issue, since the transmitted intensity map gives all the needed information, as shown in this paper. In this study, the photomask was heavily degraded after more than 18,000 300mm wafers exposed and the cleaning brought it back almost to its original state after manufacture. Wafer CD, photomask CD and iCDU results can be compared, before and after a standard mask shop cleaning. Measurement points have be chosen in logic areas and SRAM areas, so that their respective behaviours can be studied separately. Transmitted maps before and after cleaning were analysed in terms of CD shift and CDU degradation. The delta map shows a nice correlation with photomask CD shift. iCDU demonstrated the capability to detect a reliable CD range degradation of 5nm on photomask by a comparison between a reference inspection and the current inspection. Die to die inspection mode provides also valuable data, highlighting the degraded chrome sidewalls, more in the photomask centre than on the edges. Ultimately, these results would enable to trigger the preventive cleanings rather than on predefined thresholds. The expected gains for wafer fabs are cost savings (adapted cleanings frequency), increased photomask availability for production, longer photomask lifetime, no additional SEM time neither for photomask nor on wafer.

EUV scatterometry is a potential high-throughput measurement method for the characterization of EUV photomask structures. We present a comparison of angle resolved extreme ultraviolet (EUV) scatterometry and critical dimension atomic force microscope (CD-AFM) as a reference metrology for measurements of geometrical parameters like line width (CD), height and sidewall angle of EUV photomask structures. The structures investigated are dense and semidense bright and dark lines with different nominal CDs between 140 nm and 540 nm. The results show excellent linearity of the critical dimension measured with both methods within a range of only 1.8 nm and an offset of the absolute values below 3 nm. A maximum likelihood estimation (MLE) method is used to reconstruct the shape parameters and to estimate their uncertainties from the measured scattering efficiencies. The newly developed CD-AFM at PTB allows versatile measurements of parameters such as height, CD, sidewall angle, line edge/width roughness, corner rounding, and pitch. It applies flared tips to probe steep and even undercut sidewalls and employs a new vector approaching probing (VAP) strategy which enables very low tip wear and high measurement flexibility. Its traceability is ensured by a set of calibrated step-height and reference CD standards.

At the 14 nm logic node, significant lithographic changes relative to previous technologies are needed to resolve smaller features with increased fragmentation in mask design and increased use of sub-resolution assist features. Extending the application of 193 immersion lithography for further generations requires not only continued reduction of traditional sources of variation but investigation into and quantification of the impact of completely new ones, such as mask twodimensional (2D) variability. To improve the overall lithography model accuracy, two-dimensional (2D) data from the mask is required to complete a mask model with an optimal wafer response. This paper characterizes and assesses the importance of 2D mask effects on thin opaque MoSi on glass (OMOG) masks. Methodologies for characterizing corner rounding in terms of corner rounding radius and contact area are presented. Optical mask 2D measurements and wafer print results are summarized.

Evaluation of lithography process or stepper involves very large quantity of CD measurements and measurement time. In this paper, we report on an application of Scatterometry based metrology for evaluation of EUV photomask lithography. Measurements were made on mask level with Ellipsometric scatterometer for develop-check CD (DCCD) and final check CD (FCCD). Calculation of scatterometer profile information was performed with in-situ library-based rigorous coupled wave analysis (RCWA) method. We characterized the CD uniformity (CDU) and metal film thickness uniformity. OCD results show that high precision CD measurement EUV absorber and resist is possible with this method. A series of simulations were also performed to investigate the feasibility of Ellipsometric scatterometry for various pitches/line CD sizes, down to 11nm half-pitch at 1x magnification. The data showed that Scatterometry provides a nondestructive and faster mean of characterizing mask CD performance for various EUV process generations.

Four EUV film stacks are prepared and evaluated from multiple points of view: mask fabrication, blank inspection, nonactinic inspection, actinic inspection and wafer print. Mask linearity measurements show very good results for all of four blanks. Blank inspection results reveal similar inspectability. Blank roughness and reflectivity at 193nm wavelength were also measured. Some types of defects were evaluated with both non-actinic inspection tools and simulations. It was found that the thinner low reflectivity (LR) stack shows higher defect sensitivity than the thicker ones for pattern defects at 193nm inspection wavelengths. Phase defect evaluations indicate that thinner total film stacks (LR plus absorber) have an advantage for phase defect detection. Defect printability was evaluated through focus by imaging on an EUV microscope and defect printability was shown to be equivalent among the four stacks. Then the appropriate film stacks are discussed from the wafer point of view. Finally the appropriate stack was chosen based on evaluations from all the various points of view.

The SEMATECH High Numerical Aperture Actinic Reticle Review Project (SHARP) is a newly commissioned, synchrotron-based extreme ultraviolet (EUV) microscope dedicated to photomask research. SHARP offers several major advances including objective lenses with 4xNA values from 0.25 to 0.625, flexible, lossless coherence control through a Fourier-synthesis illuminator, a rotating azimuthal plane of incidence up to ±25°, illumination central ray angles from 6 to 10°, and a continuously tunable, EUV illumination wavelength. SHARP is now being used to study programmed and native mask defects, defect repairs, mask architecture, optical proximity correction, and the influence of mask substrate roughness on imaging. SHARP has the ability to emulate a variety of current and future lithography tool numerical apertures, and illumination properties. Here, we present various performance studies and examples where SHARP’s unique capabilities are used in EUV mask research.

The concept and the current status of a newly developed PEM pattern inspection system are presented. An image-processing technique with learning functions to enhance the system’s detection capability is investigated. Highly accelerated electrons employed here in electron-optics function as an enabler to improve the image resolution and transmittance in the system, and to acquire an image contrast of 0.5 in a half pitch (hp) 64 nm lines and space pattern. This process also results in the formation of an electron image with more than 3000 electrons per pixel on a sensor. The image-processing system was also developed for die-to-die inspection. The alignment error is minimized to a negligibly small size by a continuous 2D pattern matching. An ensemble of signal characteristics enables the identification of any defect signal in a noisy electron image. The developed detection system met the requirements for hp16 nm generation.

Resist materials rely on solubility differences between the exposed and unexposed areas to create the desired image. Most negative-tone resists achieve the solubility difference by crosslinking the exposed area causing it to be insoluble in developer. The negative tone resist studied here is a high sensitivity negativetone resist that relies on polarity switching, similar to a positive-tone mechanism, but where the exposed area is insoluble in aqueous developer resulting in a negative-tone image. During mask evaluation for 14nm optical technology applications of the studied non-cross linking (polarity switching) resist, 1 - 5 μm size blob-like defects were found in large numbers under certain exposure conditions. This paper will describe the process and methodologies used to investigate these blob defects.

As optical lithography is extended to the 14nm and 10nm technology nodes, sidewall angle (SWA) control of photomask features becomes increasingly important. The experiments to be reported here study SWA for advanced attenuated phase-shift photomasks. SWA is evaluated from three perspectives. First, the effects of mask etch process parameters will be studied. Second, the effects of local mask environment, such as etch loading and line width, will be tested. Finally, a variety of SWA measurement methods will be compared.

For advanced binary and PSM mask etch, final profile control is critically important for achieving desired mask specifications. As an aid to attain profile control, an etch profile simulation method has been developed. The method starts with an initial photoresist profile and incorporates etch rate and directionality information to predict the final etch profile. In this paper, simulated results are compared to measured etch profiles for PSM substrates. The results highlight the importance and implications of incoming resist profile and etch selectivity on final profile.

Native defects in mask blanks is one of the key issues in extreme ultraviolet lithography. If defect-free mask blanks is the only solution, the resulting cost will be very high due to the low yield of such blanks. In this paper, we present a method for fabricating defect-free-like EUV masks by implementing several novel techniques such as global pattern shift, fine metrology-orientation and precise e-beam second-alignment from blank preparation to e-beam exposure. The mitigation success rate versus mask pattern density is simulated and verified by lithographic results using mitigated masks. Our methodology provides a way to achieve defect-free-like EUV mask blanks.

Migration of the Cr/Cr_xO_y film in binary photomasks during use in 193nm photolithography has been observed for some time in the semiconductor industry. This phenomenon leads to a shift in the reticle critical dimensions (CDs) that worsen with increased exposure eventually resulting in wafer yield loss. This paper studies the impact of varying annealing conditions on the Cr_xO_y species on the surface of the mask. Further, we examined the effect of a surface condition with maximized Cr₂O₃ content on the 193nm-induced chrome migration phenomenon. Scanning Electron Microscopy (SEM), Transmission Electron Microscopy (TEM), and X-Ray Photoelectron Spectroscopy (XPS) were used to characterize the composition of the Cr/Cr_xO_y film. A 193nm accelerated exposure test bench was used to induce film migration in samples of varying surface chemistry.

In the absence of a pellicle, an EUVL reticle is expected to withstand up to 100 cleaning cycles. EUVL reticles constitute a complex multi-layer structure with extremely sensitive materials which are prone to damage during cleaning. The 2.5 nm thin Ru capping layer has been reported to be most sensitive to repeated cleaning, especially when exposed to aggressive dry etch or strip chemicals [1]. Such a Ru film exhibits multiple modes of failure under wet cleaning processes. In this study we investigated the Ru peeling effect. IR-induced thermo-stress in the multilayer and photochemical-induced radical attack on the surface are investigated as the two most dominant contributors to Ru damage in cleaning. Results of this investigation are presented and corrective actions are proposed.

At advanced nodes, CMOS logic is being designed in a highly regular design style because of the resolution limitations of optical lithography equipment. Logic and memory layouts using 1D Gridded Design Rules (GDR) have been demonstrated to nodes beyond 12nm.[1-4] Smaller nodes will require the same regular layout style but with multiple patterning for critical layers. One of the significant advantages of 1D GDR is the ease of splitting layouts into lines and cuts. A lines and cuts approach has been used to achieve good pattern fidelity and process margin to below 12nm.[4] Line scaling with excellent line-edge roughness (LER) has been demonstrated with self-aligned spacer processing.[5] This change in design style has important implications for mask making: • The complexity of the masks will be greatly reduced from what would be required for 2D designs with very complex OPC or inverse lithography corrections. • The number of masks will initially increase, as for conventional multiple patterning. But in the case of 1D design, there are future options for mask count reduction. • The line masks will remain simple, with little or no OPC, at pitches (1x) above 80nm. This provides an excellent opportunity for continual improvement of line CD and LER. The line pattern will be processed through a self-aligned pitch division sequence to divide pitch by 2 or by 4. • The cut masks can be done with “simple OPC” as demonstrated to beyond 12nm.[6] Multiple simple cut masks may be required at advanced nodes. “Coloring” has been demonstrated to below 12nm for two colors and to 8nm for three colors. • Cut/hole masks will eventually be replaced by e-beam direct write using complementary e-beam lithography (CEBL).[7-11] This transition is gated by the availability of multiple column e-beam systems with throughput adequate for high- volume manufacturing. A brief description of 1D and 2D design styles will be presented, followed by examples of 1D layouts. Mask complexity for 1D layouts patterned directly will be compared to mask complexity for lines and cuts at nodes larger than 20nm. No such comparison is possible below 20nm since single-patterning does not work below ~80nm pitch using optical exposure tools. Also discussed will be recently published wafer results for line patterns with pitch division by-2 and by-4 at sub-12nm nodes, plus examples of post-etch results for 1D patterns done with cut masks and compared to cuts exposed by a single-column e-beam direct write system.

historically kept it out of mainstream fabs. Thanks to continuing EBDW advances combined with the industry’s move to unidirectional (1D) gridded layout style, EBDW promises to cost-efficiently complement 193nm ArF immersion (193i) optical lithography in high volume manufacturing (HVM). Patterning conventional 2D design layouts with 193i is a major roadblock in device scaling: the resolution limitations of optical lithography equipment have led to higher mask cost and increased lithography complexity. To overcome the challenge, IC designers have used 1D layouts with “lines and cuts” in critical layers.1 Leading logic and memory chipmakers have been producing advanced designs with lines-and-cuts in HVM for several technology nodes in recent years. However, cut masks in multiple optical patterning are getting extremely costly. Borodovsky proposes Complementary Lithography in which another lithography technology is used to pattern line-cuts in critical layers to complement optical lithography.2 Complementary E-Beam Lithography (CEBL) is a candidate to pattern the Cuts of optically printed Lines. The concept of CEBL is gaining acceptance. However, challenges in throughput, scaling, and data preparation rate are threatening to deny CEBL’s role in solving industry’s lithography problem. This paper will examine the following issues: The challenges of massively parallel pixel writing The solutions of multiple mini-column design/architecture in: Boosting CEBL throughput Resolving issues of CD control, CDU, LER, data rate, higher resolution, and 450mm wafers The role of CEBL in next-generation solution of semiconductor lithography

Electron beam lithography is a promising technology for next generation lithography. Compared to optical lithography, it has better pattern fidelity and larger process window. However, the proximity effect caused by the electron forward scattering and backscattering in the resist and the underlying substrate materials has a severe influence on the pattern fidelity when the required critical dimensions (CD) are comparable to the electron beam blur size. Therefore, an accurate electron scattering model and a proper proximity correction play a vital role in electron beam lithography. In this paper, we describe the model accuracy of electron scattering in terms of multiple Gaussian kernels with an in-house proximity error correction to reduce proximity error with much better accuracy and more self-consistency than the double Gaussian kernel on the 100-keV electron energies. The impact of various Gaussian kernels used in the proximity correction on the lineation of typical patterns is also addressed.

This paper gives a review and summary of the key messages from the 2013 PMJ panel discussion topic: “Future mask patterning technologies in the next decade: searching for the best mix solution." The results of the special survey conducted for the panel are reviewed along with a brief summary of each panelist’s point of view.

As improving device integration for the next generation, high performance and cost down are also required accordingly in semiconductor business. Recently, significant efforts have been given on putting EUV technology into fabrication in order to improve device integration. At the same time, 450mm wafer manufacturing environment has been considered seriously in many ways in order to boost up the productivity. Accordingly, 9-inch mask has been discussed in mask fabrication business recently to support 450mm wafer manufacturing environment successfully. Although introducing 9-inch mask can be crucial for mask industry, multi-beam technology is also expected as another influential turning point to overcome currently the most critical issue in mask industry, electron beam writing time. No matter whether 9-inch mask or multi-beam technology will be employed or not, mask quality and productivity will be the key factors to survive from the device competition. In this paper, the level of facility automation in mask industry is diagnosed and analyzed and the automation guideline is suggested for the next generation.

Directed self-assembly (DSA) technology has already demonstrated its capability for isolated and grouped contact/via pattern for 1D gridded design. If we reverse the resist tune, this technique can also be used to implement the cut printing. However, for this purpose, we need to redistribe the cuts by extending the real wires to form the desired cut distribution for template mask making. Based on this assumption, we propose an algorithm to redistribute the original cuts such that they form groups of non-conflict DSA templates. Experimental results demonstrate that our method can effectively redistribute the cuts and improve the layout manufacturability.

The progressive transition from Excimer to EUV lithography is driving a need for flatter and smoother photomasks. It is proving difficult to meet this next generation specification with the conventional chemical mechanical polishing technology commonly used for finishing photomasks. This paper reports on the application of sub-aperture CNC precessed bonnet polishing technology to the corrective finishing of photomask substrates for EUV lithography. Fullfactorial analysis was used to identify process parameters capable of delivering 0.5 nm rms surface roughness whilst achieving removal rates above 0.1 mm³/min. Experimental results show that masks pre-polished to 300~600 nm P-V flatness by CMP can then be improved down to 50~100 nm P-V flatness using the automated technology described in this paper. A series of edge polishing experiments also hints at the possibility of increasing the quality area beyond the 5 mm defined in the official EUV photomask specification.

Improvements in the variation of critical dimensions (CD) and placement accuracy in electron beam lithography (EBL) are of high importance in the modern maskmaking industry where acceptable variations are on the one nanometer range over the mask area. In EBL, electrons backscatter from the resist and substrate, reach the bottom of objective lens and come back to the resist, causing undesirable exposure and charging far away from the point of exposure. This fogging affects both CD variation and placement accuracy. The Monte Carlo software CHARIOT was upgraded to be capable of simulating this fogging effect. The results of simulations are presented for variety of conditions. The results were used for the correction of charging placement error. Fogging is one of the contributing factors to the charging placement error; the DISPLACE software tool predicts the displacement map for any layout, system setup and exposure strategy, which allows for the correction of placement error in maskmaking.

As dimension of device shrinks to 1X nm node, an extreme control of critical dimension uniformity (CDU) of masks becomes one of key techniques for mask and wafer fabrication. For memory devices, a large number of optical techniques have been studied and applied to mask production so far. The advantages of these methods are to eliminate the sampling dependency due to their high throughput, to minimize the local CD errors due to their large field of view (FOV) and to improve the correlation with wafer infield uniformity if they have scanner-like optics. For logic devices, however, CD-SEM has been a single solution to characterize CD performance of logic masks for a long time and simple monitoring patterns, instead of the cell patterns, have been measured to monitor the CD quality of masks. Therefore a global CDU of the mask tends to show its ambiguity because of the limited number of measurement sites and large local CD errors. An application of optical metrology for logic mask is a challenging task because patterns are more complex and random in shape and because there is no guarantee of finding patterns for CDU everywhere on the mask. CDU map still consists of the results from the indirect measurements and the traditional definition of uniformity, a statistical deviation of a typical pattern, seems to be unsuitable for logic CDU. A new definition of CDU is required in order to maximize the coverage area on a mask. In this study, we have focused of the possibility of measuring cell patterns and of using an inspection tool with data base handling capability, KLA Teron617, to find the areas and positions where the repeating patterns exist and the patterns which satisfy a certain set of condition and we have devised a new definition of CDU, which can handle multiple target CDs. Then we have checked the feasibility and validity of our new methodology through evaluation its fundamental performance such as accuracy, repeatability, and correlation with other CD metrology tools with a set of logic masks.

AFM-based roughness measurement reveals the topography of EUV masks, but is only sensitive to the top surface [1]. Scatterometry provides a more accurate approach to characterize the effective phase roughness of the multilayer, and it becomes important to determine the valid metrology for roughness characterization. In this work, the power spectral density calculated from scatterometry is compared to that from AFM for measurements before and after coating of substrates with a range of roughness levels. Results show noticeable discrepancies between AFM- and scatterometrymeasured roughness, and indicates that when the physical surface roughness increases with deposition the EUV penetration into the multilayer tends to mitigate this effect. In this paper, we describe an EUV scatterometry-based measurement method for the determination of phase roughness with the goal of minimizing the amount of physical scattering data to be collected and rendering the method compatible with potential future standalone EUV reflectometer tools.

Bright-field photomasks are used to print small contact holes via ArF immersion multiple patterning lithography. There are some technical difficulties when small floating dots are to be measured by SEM tools because of a false imaging shadow. However, a new scan technology of Multi Vision Metrology SEM^TM E3630 presents a solution for this issue. The combination of new scan technology and the other MVM-SEM® functions can provide further extended applications with more accurate measurement results.

We directly extracted the phase-shift values of an EUV mask by measuring the reflectance of the mask. The mask had gradient absorber thickness along vertical direction. We measured the reflectance of the open multilayer areas and the absorber areas by using an EUV reflectometer at various absorber thicknesses. We also measured the diffracted 0th order light intensities of grating patterns having several sizes of lines or holes. The phase-shift values were derived from these data assuming a flat mask interference model of the diffracted lights. This model was corrected by including the scattering amplitude from the pattern edges. We recalculated the phase-shift values which was free from the mask topological effect. The extracted phase-shift value was close to 180 degrees at 67 nm and 71 nm absorber thicknesses. The phase measurement error around 180 degree phase shift was 5 degrees (3σ).

Two proof-of-concept electron multi-beam mask writer tools (MBMW POC) have been realized,which are utilizing262,144 programmable beams of 20nm beam size and 50keV beam energy to pattern 6" mask blanks. Tool characterization details and test results are outlined. Especially,LMSIPRO4 measurements (after development inspection) of short term and long term stability of the 82μm x 82μm beam array field are discussed.Scale stability of the beam array field of 0.1nm per day is demonstrated.

VSB mask writers, which create patterns using a combination of rectangles and 45 degree triangles, are ill-suited to non- Manhattan geometries. This issue is particularly acute for layouts which contain a large fraction of curvilinear “offangle” patterns such as photonic or DRAM designs. Unable to faithfully reproduce the “off-angle” structures, traditional VSB mask writers approximate the desired design using abutted rectangular shots or small shapes to smooth out line edge roughness. Fidelity to the original pattern comes at a cost of increased shot count and reduced throughput. Aselta has developed a novel fracture algorithm to dramatically reduce the shot count of such designs. Using a traditional VSB pattern generator, the new algorithm provides significant shot count reduction. When combined with a modified JBX-3200MV VSB, the shot count is reduced while maintaining the same level of fidelity. The data preparation software tool has also the capability of trading off a more accurate level of fidelity with an even more reduced shot count. The paper will first describe the basic principles of the fracturing algorithm and e-beam writer hardware configuration then demonstrate the advantage of the method on a variety of patterns.

To reduce down time associated with routine cathode replacement we developed a turret-type electron gun for our electron beam mask writer, EBM-8000. This enables us to exchange cathodes without venting the gun to atmosphere, thereby reducing the downtime for cathode replacement by 80% compared to conventional single-cathode guns. Two key elements were considered in developing the turret-type electron gun: reducing fluctuation in beam current, and eliminating discharge sources. Reducing fluctuation in beam current is one of the most important elements because it has an impact to critical CD accuracy. In EBM-8000, the current fluctuation must be 0.1% (3s) or less to attain the CD accuracy specification. We will explain how the beam stability is realized. Special treatment to eliminate discharge sources is necessary to realize long-term stability of the electron gun. We devised a conditioning sequence which repeatedly increases and decreases the voltage applied to the barrel in N2 atmosphere. This conditioning sequence allowed us to dramatically decrease the probability of discharges, allowing us to achieve long-term stability operation.

Making a multilayer defect-free extreme ultraviolet (EUV) blank is not possible today, and is unlikely to happen in the next few years. The method proposed by Luminescent is to compensate effects of multilayer defects on images by modifying the absorber patterns. Progress in MDC is the subject of this paper. The multilayer growth model was calibrated using real data - the top layer profile captured by AFM and cross section captured by TEM for programmed defects. Multilayer defect profiles on repair sites were recovered by applying inverse methods with the calibrated model to AFM surface scans. The recovered defect profiles were fed into the MDC engine to calculate modified absorber patterns that would compensate for the defects. Further, new methods to compensate for phase errors by depositing materials or peeling multilayers in addition to absorber modifications have been developed. Different options of multilayer peeling for compensating phase error are also evaluated through simulation. A case study was performed to find out what is the maximum pit and bump defects that can be compensated by all options available. It shows absorber pattern modification plus material deposition is the most effective option for pit defect, while absorber pattern modification plus layer-by-layer multilayer peeling is the most effective option for bump defect. Either of these methods can fix defects up to four times larger than those that can be fixed by only modifying absorber patterns near them.

Sub-wavelength photolithography heavily depends on OPC (optical proximity correction), where the pattern fidelity and CD Uniformity can never be achieved without a good OPC. The OPC runtime-resource factor has been exponentially increasing every node. It is currently approaching a dangerous level in terms of runtime and cost as the 20nm node is approaching production. A reasonable portion of the OPC computation is spent in small iterative mask perturbations trying to reach a state that prints closer to the OPC target, followed by the final few iterations aiming to accurately achieve printability on target with an almost zero EPE (edge placement error). In our work, we propose replacing the first few iterations of OPC with a single fast multi-model iteration that can perturb the OPC mask into a shape that is very close to its final state. This approach is proven to reduce the OPC runtime by an average of 28% without degrading the final mask quality.

Ionic implantation photolithography step considered to be non critical started to be influenced by unwanted overexposure by wafer topography with technology node downscaling evolution [1], [2]. Starting from 2xnm technology nodes, implant patterns modulated on wafer by classical implant proximity effects are also influenced by wafer topography which can cause drastic pattern degradation [2], [3]. This phenomenon is expected to be attenuated by the use of anti-reflecting coating but it increases process complexity and involves cost and cycle time penalty. As a consequence, computational lithography solutions are currently under development in order to correct wafer topographical effects on mask [3]. For ionic implantation source Drain (SD) on Silicon bulk substrate, wafer topography effects are the consequence of active silicon substrate, poly patterns, STI stack, and transitions between patterned wafer stack. In this paper, wafer topography aware OPC modeling flow taking into account stack effects for bulk technology is presented. Quality check of this full chip stack aware OPC model is shown through comparison of mask computational verification and known systematic defectivity on wafer. Also, the integration of topographical OPC model into OPC flow for chip scale mask correction is presented with quality and run time penalty analysis.

Dummy fill plays a crucial role on both controlling topography uniformity and ensuring device performance by manipulating homogenous pattern density. There are several types of fill to achieve this purpose on advanced technologies. The conventional way is to place them out of optical ambit range from main features as reference for Optical Proximity Correction (OPC) procedure, but it degrades the FILL performance due to leaving considerable empty space between FILL and main features. The aggressive way is to place FILL as close as main features to perfectly achieve uniform pattern density. However, in this way, it’s challenge to produce defect-free FILL in ORC (Optical Review Check) without applying model-based OPC on FILL which boost the OPC cycle time significantly. In this paper, we propose a novel approach by in-stage Repair OPC technique to not only accurately print aggressive placement FILL on the wafer accurately but also reduce the impact of run time cost on full chip OPC processing.

Ozonated water, as an alternative to a Sulfuric – Peroxide Mixture (SPM), was introduced to the resist strip and cleaning processes to prevent surface haze formation through the elimination of sulfuric acid from these processes. [1] [2] [3] [4] [5] However, it also was found to cause significant change of optical characteristics and CD-linewidth shift on ArF6% attenuation phaseshift masks (AttPSM). Although the use of 172nm Excimer UV light irradiation treatment before the cleancouldimprove the above-mentioned shifts, after several clean cycle, this phase/CD preservation effect would be dramatically degraded.[6] [7] [8] In this paper, a novel approach of phase preservationto usedry treatments based on reactive plasma Asher as part of acid-free resist strip or cleaning process is introduced. [9][10] We have investigated on the surface material integrity and CD stability of MoSi based shifters and compared with above-mentioned approach of 172nm UV light irradiation treatment, and tried to illustrate and explain the principle. Not only Asher process but also UV irradiation, is supposed to be kind of oxygen activation process to accelerate oxidization on MoSi based shifter of ArF AttPSM masks, and created passivation layer would stand out for wet cleaning; furthermore, plasma Asher process is in prior to UV irradiation. As shown in Cross-section profiles on the masks without and with Asher process, although the deference is very limited, it may be proved that a thin passivation layer was created on the surface and side of MoSi based shifter after Asher process.

When compared to conventional chrome absorber masks, electron beam patterning of EUV masks requires additional corrections to account for intermediate range electron backscattering from the mirror and tantalum based absorber layers. The performance of this Mask Proximity Correction software should not be specified based solely on traditional mask linearity measures. We propose a new mask linearity specification based on Time Dependent Dielectric Breakdown requirements for metal layers.

A thin silicon oxy-nitride hard mask on the PSM blank is needed for the feature patterning with the size smaller than 70 nm. It is a good material for hard mask. However, the electrical property of silicon oxy-nitride with the thickness smaller than 10 nm causes the chromium surface damage during the mask processes. From the measurement of the surface damage, we figure out that the chromium surface damage is originated from the charging and the dielectric breakdown phenomena. In our present work, two types of silicon oxy-nitride film with the thicknesses of 5 nm and 12 nm are tested for verifying optimal mask fabrication processes. We find that the occurrence of ESD damage is related to the thickness of silicon oxy-nitride hard mask and mask fabrication process conditions. The optimal fabrication process condition for silicon oxy-nitride thin film hard mask, in which break-down never occurs, is discussed.

As semiconductor go to smaller node, the critical dimension (CD) of process become more and more small. For lithography, RET (Resolution Enhancement Technology) applications can be used for wafer printing of smaller CD/pitch on 28nm node and beyond. SMO (Source Mask Optimization), DPT (Double Patterning Technology) and SADP (Self-Align Double Patterning) can provide lower k1 value for lithography. In another way, image placement error and overlay control also become more and more important for smaller chip size (advanced node). Mask registration (image placement error) and mask overlay are important factors to affect wafer overlay control/performance especially for DPT or SADP. In traditional method, the designed registration marks (cross type, square type) with larger CD were put into scribe-line of mask frame for registration and overlay measurement. However, these patterns are far way from real patterns. It does not show the registration of real pattern directly and is not a convincing method. In this study, the in-die (in-chip) registration measurement is introduced. We extract the dummy patterns that are close to main pattern from post-OPC (Optical Proximity Correction) gds by our desired rule and choose the patterns that distribute over whole mask uniformly. The convergence test shows 100 points measurement has a reliable result.