PROCEEDINGS VOLUME 9053
SPIE ADVANCED LITHOGRAPHY | 23-27 FEBRUARY 2014
Design-Process-Technology Co-optimization for Manufacturability VIII
Proceedings Volume 9053 is from: Logo
SPIE ADVANCED LITHOGRAPHY
23-27 February 2014
San Jose, California, United States
Front Matter
Proc. SPIE 9053, Front Matter: Volume 9053, 905301 (22 April 2014); doi: 10.1117/12.2064480
Patterns in DTCO
Proc. SPIE 9053, Lithography-induced limits to scaling of design quality, 905302 (28 March 2014); doi: 10.1117/12.2047391
Proc. SPIE 9053, A pattern-driven design regularization methodology, 905303 (28 March 2014); doi: 10.1117/12.2047741
Proc. SPIE 9053, Systematic physical verification with topological patterns, 905304 (28 March 2014); doi: 10.1117/12.2046709
Proc. SPIE 9053, Synthesis of lithography test patterns through topology-oriented pattern extraction and classification, 905305 (28 March 2014); doi: 10.1117/12.2046142
Proc. SPIE 9053, Systematic data mining using a pattern database to accelerate yield ramp, 905306 (28 March 2014); doi: 10.1117/12.2047307
Proc. SPIE 9053, Layout pattern-driven design rule evaluation, 905307 (28 March 2014); doi: 10.1117/12.2046140
Multipatterning
Proc. SPIE 9053, Bridging the gap from mask to physical design for multiple patterning lithography, 905308 (28 March 2014); doi: 10.1117/12.2048626
Proc. SPIE 9053, Demonstrating production quality multiple exposure patterning aware routing for the 10NM node, 905309 (28 March 2014); doi: 10.1117/12.2045958
Proc. SPIE 9053, A fast triple patterning solution with fix guidance, 90530A (28 March 2014); doi: 10.1117/12.2046487
Proc. SPIE 9053, Benchmarking process integration and layout decomposition of directed self-assembly and self-aligned multiple patterning techniques, 90530B (28 March 2014); doi: 10.1117/12.2046085
Proc. SPIE 9053, Self-aligned quadruple patterning-aware routing, 90530C (28 March 2014); doi: 10.1117/12.2046241
Hotspots
Proc. SPIE 9053, Accurate lithography hotspot detection based on PCA-SVM classifier with hierarchical data clustering, 90530E (28 March 2014); doi: 10.1117/12.2045888
Proc. SPIE 9053, Model based multilayers fix for litho hotspots beyond 20nm node, 90530F (28 March 2014); doi: 10.1117/12.2045744
Proc. SPIE 9053, Configurable hot spot fixing system, 90530G (28 March 2014); doi: 10.1117/12.2046272
Proc. SPIE 9053, "Smart" source, mask, and target co-optimization to improve design related lithographically weak spots, 90530H (28 March 2014); doi: 10.1117/12.2047077
Design Optimization I
Proc. SPIE 9053, Layout induced variability and manufacturability checks in FinFETs process, 90530I (28 March 2014); doi: 10.1117/12.2046284
Proc. SPIE 9053, Layout optimization of DRAM cells using rigorous simulation model for NTD, 90530J (28 March 2014); doi: 10.1117/12.2046541
Pattern-Aware Techniques: Joint Session with Conferences 9052 and 9053
Proc. SPIE 9053, Lithography yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations, 90530M (28 March 2014); doi: 10.1117/12.2046208
Design Optimization II
Proc. SPIE 9053, Technology-design-manufacturing co-optimization for advanced mobile SoCs, 90530N (28 March 2014); doi: 10.1117/12.2047370
Proc. SPIE 9053, Optimizing standard cell design for quality, 90530O (28 March 2014); doi: 10.1117/12.2045660
Proc. SPIE 9053, Analysis and optimization of process-induced electromigration on signal interconnects in 16nm FinFET SoC (system-on-chip), 90530P (28 March 2014); doi: 10.1117/12.2046207
Proc. SPIE 9053, Design technology co-optimization for a robust 10nm Metal1 solution for logic design and SRAM, 90530Q (28 March 2014); doi: 10.1117/12.2048079
DSA Design for Manufacturability: Joint Session with Conferences 9049, 9052, and 9053
Proc. SPIE 9053, Physical verification and manufacturing of contact/via layers using grapho-epitaxy DSA processes, 90530R (28 March 2014); doi: 10.1117/12.2045328
Design Optimization III
Proc. SPIE 9053, ECO fill: automated fill modification to support late-stage design changes, 90530S (28 March 2014); doi: 10.1117/12.2047650
Proc. SPIE 9053, Yield-aware decomposition for LELE double patterning, 90530T (28 March 2014); doi: 10.1117/12.2046180
Proc. SPIE 9053, A generalized model to predict fin-width roughness induced FinFET device variability using the boundary perturbation method, 90530U (28 March 2014); doi: 10.1117/12.2046221
Proc. SPIE 9053, Localization concept of re-decomposition area to fix hotspots for LELE process , 90530V (28 March 2014); doi: 10.1117/12.2046263
Poster Session
Proc. SPIE 9053, Decomposition-aware layout optimization for 20/14nm standard cells, 90530W (28 March 2014); doi: 10.1117/12.2046147
Proc. SPIE 9053, Resist profile aware source mask optimization, 90530X (28 March 2014); doi: 10.1117/12.2046252
Proc. SPIE 9053, Robust and automated solution for correcting hotspots locally using cost-function based OPC solver, 90530Z (28 March 2014); doi: 10.1117/12.2046662
Proc. SPIE 9053, A layout decomposition algorithm for self-aligned multiple patterning, 905310 (28 March 2014); doi: 10.1117/12.2046390
Proc. SPIE 9053, Work smarter not harder: How to get more results with less modeling, 905311 (28 March 2014); doi: 10.1117/12.2046086
Proc. SPIE 9053, Scanner correction capabilities aware CMP lithography hotspot analysis, 905312 (28 March 2014); doi: 10.1117/12.2053035
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