This PDF file contains the front matter associated with SPIE Proceedings Volume 9426, including the Title Page, Copyright information, Table of Contents, Authors, Introduction (if any), and Conference Committee listing.

This presentation addresses the challenges to pattern single-digit nanometer nodes. Next generation lithography such as Extreme UV, Multiple E-Beam Direct Write, may or may not help to meet the challenges. Optical lithography may still be needed for all layers, in combination with NGL for relevant layers, or not at all. The consideration will be based on necessary requirements such as overlay accuracy, resolution, and defects. However, even if all these requirements are met, only a satisfactory cost can dictate the application in high volume manufacturing. Some considerations on costs will also be presented.

This talk will examine the evolutionary path of optical lithography without EUV. We explore the previous history to understand the various solutions that have emerged. This will give insight into future possibilities. We will examine the possible limits and fundamental problems moving into the sub-10nm node regime. Finally, the cost implications and future technologies are explored.

In this paper we extend our work into the impact of Mask Topography induced effects in current state of the art lithography by looking at the phase in the diffracted orders. By analyzing and describing the phase in a similar and systematic way as done for projection lenses, we could identify already known effects as best focus differences and pattern asymmetry, but also a new significant effect was found: contrast loss. We used the phase range in the diffracted orders as a metric to be used during lithography set-up. We were able to link the performance of different mask absorber types and parameters with the phase range in the diffracted orders.

In 7mn node (N7), the logic design requires the critical poly pitch (CPP) of 42-45nm and metal 1 (M1) pitch of 28- 32nm. Such high pattern density pushes the 193 immersion lithography solution toward its limit and also brings extremely complex patterning scenarios. The N7 M1 layer may require a self-aligned quadruple patterning (SAQP) with triple litho-etch (LE³) block process. Therefore, the whole patterning process flow requires multiple exposure+etch+deposition processes and each step introduces a particular impact on the pattern profiles and the topography. In this study, we have successfully integrated a simulation tool that enables emulation of the whole patterning flow with realistic process-dependent 3D profile and topology. We use this tool to study the patterning process variations of N7 M1 layer including the overlay control, the critical dimension uniformity (CDU) budget and the lithographic process window (PW). The resulting 3D pattern structure can be used to optimize the process flow, verify design rules, extract parasitics, and most importantly, simulate the electric field and identify hot spots for dielectric reliability. As an example application, we will report extractions of maximum electric field at M1 tipto- tip which is one of the most critical patterning locations and we will demonstrate the potential of this approach for investigating the impact of process variations on dielectric reliability. We will also present simulations of an alternative M1 patterning flow, with a single exposure block using extreme ultraviolet lithography (EUVL) and analyze its advantages compared to the LE₃ block approach.

Double-patterning ArF immersion lithography continues to advance the patterning resolution and overlay requirements and has enabled the continuation of semiconductor bit-scaling. Over the years Lithography Engineers continue to focus on CD control, overlay and process capability to meet current node requirements for yield and device performance. Reducing or eliminating variability in any process will have significant impact, but the sources of variability in any lithography process are many. The goal from the light source manufacturer is to further enable capability and reduce variation through a number of parameters.

Recent improvements in bandwidth control have been realized in the XLR platform with Cymer’s DynaPulse^TM control technology. This reduction in bandwidth variation could translate in the further reduction of CD variation in device structures. The Authors will discuss the impact that these improvements in bandwidth control have on advanced lithography applications. This can translate to improved CD control and higher wafer yields. A simulation study investigates the impact of bandwidth on contrast sensitive device layers such as contacts and 1x metal layers. Furthermore, the Authors will discuss the impact on process window through pitch and the overlapping process window through pitch that has been investigated. These improvements will be further quantified by the analysis of statistical bandwidth variation and the impact on CD.

In this paper we present the limitations of 3rd order distortion corrections based on standard overlay metrology and propose a new method to quantify and correct the cold-lens aberration fingerprint. As a result of continuous shrinking features of the integrated circuit, the overlay budget requirements have become very demanding. Historically, most overlay enhancements were achieved by hardware improvements. However there also is a benefit in the computational approach, and so we looked for solutions for overlay improvements in process variation with computational applications.

Lithography process window (PW) and CD uniformity (CDU) requirements are being challenged with scaling across all device types. Aggressive PW and yield specifications put tight requirements on scanner performance, especially on focus budgets resulting in complicated systems for focus control. In this study, an imec N10 Logic-type test vehicle was used to investigate the E95 bandwidth impact on six different Metal 1 Logic features. The imaging metrics that track the impact of light source E95 bandwidth on performance of hot spots are: process window (PW), line width roughness (LWR), and local critical dimension uniformity (LCDU).

In the first section of this study, the impact of increasing E95 bandwidth was investigated to observe the lithographic process control response of the specified logic features. In the second section, a preliminary assessment of the impact of lower E95 bandwidth was performed. The impact of lower E95 bandwidth on local intensity variability was monitored through the CDU of line end features and the LWR power spectral density (PSD) of line/space patterns. The investigation found that the imec N10 test vehicle (with OPC optimized for standard E95 bandwidth of300fm) features exposed at 200fm showed pattern specific responses, suggesting areas of potential interest for further investigation.

This report presents a model to predict, analyze, and monitor pattern edge placements errors occurring during integrated circuit manufacture. The edge placement errors are driven by overlay and imaging capabilities of scanners and pattering tools. The model can be used to analyze the impact of various imaging strategies on pattern placement statistics of layers composing ICs. Such analysis is essential to both, IC designers and lithography engineers, striving to successfully fabricate complex designs at economical manufacture yields. The report discusses key contributors to the image edge placement errors and presents examples of edge placement predictions based on scanner records. The edge placement error examples presented in this report are based on scanner overlay and CD uniformity performance for the current generation of integrated circuit designs.

Traditional approaches to improving photolithographic resolution rely on using shorter and shorter wavelengths of electromagnetic radiation. This approach faces ever greater challenges each time the operating wavelength is decreased. Recently, alternative approaches to nanoscale photolithography have been introduced that employ photoresists that are sensitive to multiple colors of visible light. One or more colors of light activate the photoresist, and one or more colors of light can subsequently deactivate it. By controlling the spatial patterns of the colors, it is possible to create features with sizes that are far below the diffraction limit. This approach has been demonstrated for laboratory-based fabrication using multiphoton-absorption-based fabrication, but with improvements in materials it shows great promise for semiconductor lithography as well. A number of approaches to two-color photolithography have been demonstrated. A next generation of schemes that involve a third color of light has the potential to improve the performance of multicolor lithography substantially. The basic premises of both two-color and three-color lithography are discussed, and experimental examples of each type of approach are presented.

In this paper we report on advances in DUV dry photolithography both for etching and implantation of silicon photonic devices. We explain why silicon patterning is a critical building block in silicon photonics and what are the challenges related to that process. Furthermore, it also occurs that some silicon photonic devices need implantation lithographic conditions which are also specific to the technology. For that purpose, we developed a dedicated DUV 193nm implantation lithography to address that need.

Diffractive mask-aligner lithography is capable to print structures that have a sub-500-nanometer resolution by using non-contact mode. This requires the use of specially designed phase-masks and dedicated illumination conditions in the Mask-Aligner to obtain the optimal exposure conditions, a spectral filter and a polarizer needs to be placed in the beam path. We introduce here mask designs that includes a polarizer on the top side of a photo-mask and a diffractive element on the bottom one. This enables printing of high resolution structures of arbitrary orientation by using a classical mask-aligner in proximity exposure mode.

Digital Micromirror Device (DMD)-based grayscale lithography is a promising tool for three dimensional (3D) microstructuring of thick-film photoresist since it is a maskless process, provides possibility for the free-form of 3D microstructures, and therefore rapid and cost-effective microfabrication. However, process parameter determination lacks efficient optimization tool, and thus conventional look-up table (indicating the relationship between development depth and exposure dose value under a fixed development time) approach with manual try-and-error adjustment is still gold standard. In this paper, we firstly present a complete “input target-output parameters” single exposure optimization method for 3D microstructuring utilizing DMD-based grayscale lithography. This numerical optimization based on lithography simulation and sensitivity analysis can automatically optimize a combination of three process parameters for target microstructure; exposure dose pattern, a focal position, and development time. Through a series of experiments using a 20 μm thick positive photoresist, validity of the proposed optimization approach has been successfully verified. Secondly, with the purpose of further advancing accuracy and improve the uniformity of precision for the target area, a multiple exposure optimization method is proposed. The simulated results proved that the multiple exposure optimization method is a promising strategy to further improve precision for thicker photoresist structure.

The mask plays a significant role as an active optical element in lithography, for both EUV and immersion lithography. Mask-induced and feature dependent shifts of the best focus position and other aberration-like effects were reported both for deep ultraviolet (DUV) immersion and for EUV lithography. We employ rigorous computation of light diffraction from lithographic masks in combination with aerial image simulation to study the root causes of these effects and their dependencies from mask and optical system parameters. Special emphasis is put on the comparison of transmission masks for DUV lithography and reflective masks for EUV lithography, respectively.

The proximity printing industry is in real need of high resolution results and it can be done using Phase Shift Mask (PSM) or by applying Optical Proximity Correction (OPC). In our research we are trying to find out details of how light fields behind the structures of photo masks develop in order to determine the best conditions and designs for proximity printing. We focus here on parameters that are used in real situation with gaps up to 50 μm and structure sizes down to 2 μm. The light field evolution behind the structures is studied and delivers insight in to precisions and tolerances that need to be respected. It is the first time that an experimental analysis of light propagation through mask is presented in detail, which includes information on intensity and phase. The instrument we use is known as High Resolution Interference Microscopy (HRIM). HRIM is a Mach-Zehnder interferometer which is capable of recording three dimensional distributions of intensity and phase with diffraction limited resolution. Our characterization technique allows plotting the evolution of the desired light field and therefore printable structure till the desired proximity gap. In this paper we discuss in detail the evolution of intensity and phase fields of elbow or corner structure at different position behind a phase mask and interpret the main parameters. Of particular interest are tolerances against proximity gap variation and the resolution in printed structures.

Printing contact-like cut mask form the line end of very dense pitches is imposing a significant challenge to lithography. Various lithography options including optical multi-patterning and EUV have been considered for sub-20nm half pitch metal line cut process. Different lithography solutions of cut mask will impose different design restrictions and thus lead to different scalability of chip. In this paper, we will study routing limitations of sub-20nm half pitch metal lines cut with various optical and EUV lithography options. Key metal routing rules for each cut mask option will be derived based on study of forbidden cut mask configurations. The associated logic area impact will be derived based on real digital design.

We present a novel optimisation algorithm for inverse lithography, based on optimization of the mask derivative, a domain inherently sparse, and for rectilinear polygons, invertible. The method is first developed assuming a point light source, and then extended to general incoherent sources. What results is a fast algorithm, producing manufacturable masks (the search space is constrained to rectilinear polygons), and flexible (specific constraints such as minimal line widths can be imposed). One inherent trick is to treat polygons as continuous entities, thus making aerial image calculation extremely fast and accurate. Requirements for mask manufacturability can be integrated in the optimization without too much added complexity. We also explain how to extend the scheme for phase-changing mask optimization.

We present results generated using a new gauge-based Resolution Enhancement Technique (RET) Selection flow during the technology set up phase of a 3x-node NAND Flash product. As a testcase, we consider a challenging critical level for this ash product. The RET solutions include inverse lithography technology (ILT) optimized masks with sub-resolution assist features (SRAF) and companion illumination sources developed using a new pixel based Source Mask Optimization (SMO) tool that uses measurement gauges as a primary input. The flow includes verification objectives which allow tolerancing of particular measurement gauges based on lithographic criteria. Relative importance for particular gauges may also be set, to aid in down-selection from several candidate sources. The end result is a sensitive, objective score of RET performance. Using these custom-defined importance metrics, decisions on the final RET style can be made in an objective way.

Source mask optimization (SMO) was considered to be one of the key resolution enhancement techniques for node technology below 20 nm prior to the availability of extreme-ultraviolet tools. SMO has been shown to enlarge the process margins for the critical layer in SRAM and memory cells. In this study, a new illumination shape optimization approach was developed on the basis of the ant colony optimization (ACO) principle. The use of this heuristic pixel-based ACO method in the SMO process provides an advantage over the extant SMO method because of the gradient of the cost function associated with the rapid and stable searching capability of the proposed method. This study was conducted to provide lithographic engineers with references for the quick determination of the optimal illumination shape for complex mask patterns. The test pattern used in this study was a contact layer for SRAM design, with a critical dimension and a minimum pitch of 55 and 110 nm, respectively. The optimized freeform source shape obtained using the ACO method was numerically verified by performing an aerial image investigation, and the result showed that the optimized freeform source shape generated an aerial image profile different from the nominal image profile and with an overall error rate of 9.64%. Furthermore, the overall average critical shape difference was determined to be 1.41, which was lower than that for the other off-axis illumination exposure. The process window results showed an improvement in exposure latitude (EL) and depth of focus (DOF) for the ACO-based freeform source shape compared with those of the Quasar source shape. The maximum EL of the ACO-based freeform source shape reached 7.4% and the DOF was 56 nm at an EL of 5%.

The Optical Proximity Correction (OPC) model, a key to process yield in the mask synthesis flow, is getting more and more complicated and challenging at advanced technology nodes (1X nm). To achieve accurate critical dimension (CD) prediction and model robustness on varied designed patterns, a rigorously tuned compact model (RTCM) [1] that takes the photoresist chemical effects into considerations is strongly desired. A lithography process consists of three main stages: Exposure, Post-Exposure Bake (PEB), and Photoresist Development. Each stage is characterized by its fundamental physics or chemistry that governs the process of illumination induced photo-acid generation, thermally activated chemical reaction-diffusion, and developer dependent photoresist dissolution, respectively. The final resist profile is determined by the process details of all these stages directly or indirectly. For an ideal resist that the development contrast approaches infinity, resist development is aptly represented by a threshold model applied to the PEB latent image (acid or inhibitor concentration). So the quality of OPC modeling is largely determined by the fidelity of PEB latent image [2,3]. However, for some types of resist and developer used in Negative Tone Development (NTD), the development contrast shows a long tail without a sharp transition. For such low-contrast resist, the developed resist profile is no longer described well by the equilevel surface of PEB latent image. Going beyond the threshold approximation, we start from the fundamental equations of resist development physics and analyze the time evolution of development front that determines the resist profile. In this paper, a new compact model is derived to catch the main physics in resist Development, which is also simple and computationally efficient to suit for OPC applications. Comparison with S-LITHO rigorous solutions and real-wafer experiments with 1D and 2D test patterns have showed that the new compact model, with fewer free parameters, provides better CD prediction than the existing empirical lumped parameter models for low-contrast resists. The new physical compact model offers a more accurate and extendable solution for OPC modeling at the 10nm node and onward.

Mask topography contributes diffraction-induced phase near edges, affecting the through-focus intensity variation and hence the process window at the wafer. We analyze the impact of edge diffraction on projection printing directly with experiments on an aerial image measurement system (AIMS). We show here that topographic effects change with illumination angle and can be quantified using through-focus intensity measurements. Off- axis incidence influences not just defocus image behavior (as for normal incidence), but also the at-focus intensity at wafer. Moreover, with oblique illumination, mask diffraction varies for left-facing and right-facing sidewalls, the nature of the asymmetry being polarization dependent. The image degradation due the polarization parallel to the sidewall (TE) is seen to be stronger, owing to the interplay of mask topography and pupil filtering in the imaging system. This translates to a CD variation of 2% between the two polarizations, even at focus. A simple thin-mask boundary layer model that treats each sidewall independently is shown to be able to approximate mask topography induced diffraction for both polarizations with 5-10nm wide boundary layers.

The physical process of mask manufacturing produces absorber geometry with significantly less than 90 degree fidelity at corners. The non-Manhattan mask geometry is an essential contributor to the aerial image and resulting patterning performance through focus. Current state of the art models for corner rounding employ “chopping” a 90 degree mask corner, replacing the corner with a small 45 degree edge. In this paper, a methodology is presented to approximate the impact of 3D EMF effects introduced by corners with rounded edges. The approach is integrated into a full chip 3D mask simulation methodology based on the Domain Decomposition Method (DDM) with edge to edge crosstalk correction.

As the critical dimension keeps shrinking, mask topography effect (Mask3D) becomes considerable to impact the lithography modeling accuracy and the quality of full-chip OPC. Among many challenges in Mask3D modeling, it is critical and particularly demanding to treat off-axis illumination (OAI) properly. In this paper, we present a novel Mask3D model that is completely test pattern- and optics- independent. Such model property enables greatly improved performance in terms of accuracy and consistency on various pattern types (1D/2D) and through a wide range of focus conditions, while no runtime overhead is incurred. The novel model and formulation will be able to save significant modeling time and greatly improve the model reliability, predictability and ease of use. Experimental results validate the claims and demonstrate the superiority to the current state-of-the-art Mask3D modeling method. This is a new generation Mask3D modeling process.

One of the main concerns about EUV lithography is whether or not it can be extended to very high numerical aperture. Recently, a waveguide effect in high-NA EUV lithography was observed. This effect serves to overcome the problem of shadowing in EUV lithography and allows EUV lithography to be extended to the 4-nm node. In this paper, an exact eigenmode analysis is presented to explain the observed effect. This waveguide effect is then applied to simulate the printing of 4-nm lines and spaces with excellent aerial-image contrast and peak intensity. The feasibility of EUV lithography for printing logic circuits containing general 2D patterns with 4-nm feature size is also demonstrated.

We have been utilizing rigorous simulation software in order to predict the alignment mark signal quality and mark contrast variation induced by processes changes reliably. We have run simulations in order to understand which parameters influence alignment mark quality most and to determine the important parameters that can be manipulated in order to improve it. Simulation of alignment signals (also referred to as waveforms) has been done for resist marks and etched marks, coated and uncoated, as well as in presence of increasing topography complexity. To validate simulation analysis, mark signal collection for different processes (and/or variations of those) and products has been carried out; cross sections have also been generated.

Two aspects of NTD resists, deprotection-induced shrinkage, and retrograde sidewalls, are investigated through experimentation and simulation.

Simulation predicts that NTD resist profiles should often have retrograde sidewall angles due to the attenuation of light as it propagates down through the resist. Resist shrinkage induced from both the de-protection during PEB and from exposure to electrons during SEM can cause CD and sidewall changes. The interplay between the shrinkage and the retrograde sidewalls is discussed.

Deprotection-induced shrinkage is measured by AFM while SEM induced shrinkage is estimated from repeated SEM measurements. SEM images for various features are analyzed and compared to simulation.

A novel approach to Sub-Resolution Assist Feature (SRAF) generation suitable for full-chip production scale applications is discussed in this work. The method enables generation of free-form SRAF insertion guidelines similar to those obtained by solving the inverse lithography problem. The guidelines encompass layout areas where total net effect of an elementary SRAF placement is positive taking into account all neighboring target features. The essence of the method is the assumption that the total impact of placing an elementary SRAF close to several neighboring features can be calculated as a sum of impacts to individual target features, or a simple mathematical function could be used to perform this calculation. Reduction of the SRAF insertion problem to the linear addition of “usefulness” metric on a grid enables the method to be exceptionally computationally efficient. Tests on an aggressive 28nm 100x100 um design contact array clips have confirmed 3+ orders of magnitude faster free-form SRAF generation as compared to commercially available ILT engines.

Traditionally, an image parameter metric has been used to analyze the lithography and resist responses versus the test pattern coverage. This metric assumes a variable threshold resist model which is not necessarily the state-of-the art model type used in the latest technology nodes. Additionally, these methods don’t consider the statistical nature of the variations where the number of the selected patterns can greatly affect the uncertainty of the model prediction for another set of patterns. We propose a new method that combines the lithography response with uncertainty analysis to select test patterns for OPC model calibration. We also propose a new metric based on resist response to be considered in site selection for advanced resist models. We show that uncertainty aware site selection combined with this new metric gives similar or better model accuracy compared to baseline which requires engineering expertise and other site clustering tools, but with large amount of calibration site reduction. Examples from advanced nodes are given.

OPC models have become critical in the manufacturing of integrated circuits (ICs) by allowing correction of complex designs, as we approach the physical limits of scaling in IC chip design. The accuracy of these models depends upon the ability of the calibration set to sufficiently cover the design space, and be manageable enough to address metrology constraints. We show that the proposed method provides results of at least similar quality, in some cases superior quality compared to both the traditional method and sample plan sets of higher size. The main advantage of our method over the existing ones is that it generates a calibration set much faster, considering a large initial set and even more importantly, by automatically selecting its minimum optimal size.

Optical Proximity Correction (OPC) is one of the most important techniques in today's optical lithography based manufacturing process. Although the most widely used model-based OPC is expected to achieve highly accurate correction, it is also known to be extremely time-consuming. This paper proposes a regression model for OPC using a Hierarchical Bayes Model (HBM). The goal of the regression model is to reduce the number of iterations in model-based OPC. Our approach utilizes a Bayes inference technique to learn the optimal parameters from given data. All parameters are estimated by the Markov Chain Monte Carlo method. Experimental results show that utilizing HBM can achieve a better solution than other conventional models, e.g., linear regression based model, or non-linear regression based model. In addition, our regression results can be fed as the starting point of conventional model based OPC, through which we are able to overcome the runtime bottleneck.

Continued improvements in SEM contour extraction capabilities have enabled calibrating more accurate OPC models for advanced technology nodes using a hybrid approach, combining CDs for 1D structures and full contour measurements for more complex 2D patterns. Previous work has addressed various components of contour modeling including alignment, edge detection, CD to contour consistency, and image parameter space coverage. This study covers weighting strategies for CDs compared to contours. Additionally the total number of structures in a sample plan can be reduced by incorporating contours for model calibration due to the increased number of evaluation points they provide.

Repeated measurements of the same structure at separate locations are used to extract SEM contours across several instances. The average measurements from these locations can then be used for OPC model calibration. Using 14nm process data, it is shown that including more contours in hybrid OPC model calibration leads to improved model verification. Within an appropriate range, higher weight on the contour patterns leads to improved model verification on measurement sites unseen by the calibration set. Calibrating a model with fewer contour structures, but at higher weight shows improvement over standard CD only model calibration.

A resist cross-sectional profile becomes worse as feature sizes shrink. The bad resist profile could result in a hotspot after etching process (after-etch hotspot). Conventional simulation method is difficult to detect such hotspots accurately because it does not consider process variation. In this paper, we propose an accurate after-etch hotspot detection methodology with consideration of process variation based on optical intensity and defect rate. An experimental result shows our method can detect an after-etch hotspot accurately.

Optical Proximity Correction (OPC) is a compute-intensive process used to generate photolithography mask shapes at advanced VLSI nodes. Previously, we reported a modified two-step OPC flow which consists of a first pattern replacement step followed by a model based OPC correction step [1]. We build on this previous work and show how this hybrid flow not only improves full chip OPC runtime, but also significantly improves mask correction consistency and overall mask quality. This is demonstrated using a design from the 20nm node, which requires the use of model based SRAF followed by model based OPC to obtain the full mask solution.

To accord with new requirement of securing more overlay margin, not only the optical overlay measurement is faced with the technical limitations to represent cell pattern’s behavior, but also the larger measurement samples are inevitable for minimizing statistical errors and better estimation of circumstance in a lot. From these reasons, diffraction based overlay (DBO) and integrated metrology (IM) were mainly proposed as new approaches for overlay enhancement in this paper.

The use of extreme freeform illumination conditions and multi patterning processes used to generate sub 40nm images can result in significant intra-field overlay errors. When levels with differing illumination conditions are aligned to each other, these intra-field distortions can result in overlay errors which are uncorrectable using normal linear feedback corrections.

We use a double exposure method, previously described by Minghetti [1] et al. to isolate and measure intra-field overlay distortions caused by tool lens signatures and different illumination conditions. A full field test reticle is used to create a dual level expose pattern. The same pattern is exposed twice, but with two different illumination conditions. The first exposure is done with a standard reference illumination. The second exposure is the target illumination condition. The test reticle has overlay target pairs that are measurable when the 2nd exposure is offset in the Y direction by the designed amount. This allows for a high density, 13x13, intra-field overlay measurement to be collected and modeled to determine 2^nd and 3^rd order intra-field terms. Since the resulting illumination and scanner lens specific intra field corrections are independent of field size, the sub-recipes can be applied to any product exposure independent of field size, which use the same illumination conditions as the test exposures. When the method is applied to all exposure levels in a product build cycle, the overlay errors contributed by the reference illumination condition cancel out. The remaining errors are due exclusively to the impact of the illumination condition on that scanner lens.

Actual results correlated well with the model with more than 80% of the predicted overlay improvement being achieved.

For mass production of DRAM device, a stable and effective overlay control becomes more and more important as DRAM design rule shrinks. Existent technologies were already applied to overcome this situation. Nevertheless, we are still suffered from tight overlay margin and forced to move from lot-based to wafer-based overlay control. However, the wafer-based control method requires a huge amount of measurement resource.

In this paper, we present the insight for the wafer-based overlay correction with optimal measurement resource which is suitable for mass production. The experiment which is the wafer-based overlay correction by several statistical analyses carried out for 2X nm node DRAM. Among them, linear regression is a strong candidate for wafer-based overlay control, which improved up to 0.8 nm of maximum overlay.

Progressing towards the 10nm and 7nm imaging node, pattern-placement and layer-to-layer overlay requirements keep on scaling down and drives system improvements in immersion (ArFi) and dry (ArF/KrF) scanners. A series of module enhancements in the NXT platform have been introduced; among others, the scanner is equipped with exposure stages with better dynamics and thermal control. Grid accuracy improvements with respect to calibration, setup, stability, and layout dependency tighten MMO performance and enable mix and match scanner operation. The same platform improvements also benefit focus control. Improvements in detectability and reproducibility of low contrast alignment marks enhance the alignment solution window for 10nm logic processes and beyond. The system’s architecture allows dynamic use of high-order scanner optimization based on advanced actuators of projection lens and scanning stages. This enables a holistic optimization approach for the scanner, the mask, and the patterning process. Productivity scanner design modifications esp. stage speeds and optimization in metrology schemes provide lower layer costs for customers using immersion lithography as well as conventional dry technology. Imaging, overlay, focus, and productivity data is presented, that demonstrates 10nm and 7nm node litho-capability for both (immersion & dry) platforms.

In order to achieve stable operation in cutting-edge semiconductor manufacturing, Nikon has developed NSR-S630D with extremely accurate overlay while maintaining throughput in various conditions resembling a real production environment. In addition, NSR-S630D has been equipped with enhanced capabilities to maintain long-term overlay stability and user interface improvement all due to our newly developed application software platform. In this paper, we describe the most recent S630D performance in various conditions similar to real productions. In a production environment, superior overlay accuracy with high dose conditions and high throughput are often required; therefore, we have performed several experiments with high dose conditions to demonstrate NSR’s thermal aberration capabilities in order to achieve world class overlay performance. Furthermore, we will introduce our new software that enables long term overlay performance.

Semiconductor market demand for improved performance at lower cost continues to drive enhancements in excimer light source technologies. Multi-patterning lithography solutions to extend deep-UV (DUV) immersion have driven requirements such as higher throughput and higher efficiencies to maximize the utilization of leading-edge lithography equipment. Three key light source parameters have direct influence on patterning performance – energy, wavelength and bandwidth stability – and they have been the primary areas of continuous improvement. With 14nm node development, a number of studies have shown the direct influence of bandwidth stability on CD uniformity for certain patterns and geometries, leading to the desire for further improvements in this area. More recent studies also examined the impact of bandwidth on 10nm logic node patterning [1]. Alongside these drivers, increasing cost per patterning layer continues to demand further improvements in operating costs and efficiencies from the lithography tools, and the light source can offer further gains in these areas as well. This paper introduces several light source technologies that are embodied in a next-generation light source, the Cymer XLR® 700ix, which is an extension of the ring laser architecture introduced 8 years ago. These technologies enable a significant improvement in bandwidth stability as well as notable reductions in operating costs through more efficient gas management algorithms and lower facilities costs.

Along with device shrinkage, higher accuracy will continuously be required from photo-lithography tools in order to enhance on-product yield. In order to achieve higher yield, the advanced photo-lithography tools must be equipped with sophisticated tuning knobs on the tool and with software that is flexible enough to be applied per layer. This means photo-lithography tools must be capable of handling many types of sub-recipes and parameters simultaneously.

To enable managing such a large amount of data easily and to setup lithography tools smoothly, we have developed a total lithography system called Litho Turnkey Solution based on a new software application platform, which we call Plug and Play Manager (PPM). PPM has its own graphical user interface, which enables total management of various data. Here various data means recipes, sub-recipes, tuning-parameters, measurement results, and so on. Through PPM, parameter making by intelligent applications such as CDU/Overlay tuning tools can easily be implemented. In addition, PPM is also linked to metrology tools and the customer’s host computer, which enables data flow automation. Based on measurement data received from the metrology tools, PPM calculates correction parameters and sends them to the scanners automatically. This scheme can make calibration feedback loops possible. It should be noted that the abovementioned functions are running on the same platform through a user-friendly interface. This leads to smart scanner management and usability improvement.

In this paper, we will demonstrate the latest development status of Nikon’s total lithography solution based on PPM; describe details of each application; and provide supporting data for the accuracy and usability of the system. Keywords: exposure

The difficulty of EUV lithography system development has prolonged the industry’s dependence on ArF excimer lasers to realize further advancements in lithography process technologies. Smaller CD with reduced cost requires tighter specifications, and the potential extension to 450mm wafers introduces extremely difficult performance challenges on lasers. One of the most important features of the next generation lasers will be the ability to support green operations while further improving cost of ownership and performance. For example, electricity consumption costs and the dependence on rare gases, such as neon and helium, will become critical considerations for HVM process going forward. As a laser vendor, Gigaphoton continues to innovate and develop solutions that address these important issues. The latest model GT64A with its field-proven, twin-chamber platform has reduced environmental impact while upgrading performance and power. A variety of green technologies are employed on the GT64A. The first is the reduction of gas usage. Parameters, such as input power and gas pressure are closely monitored during operations and fed back to the injection/exhaust gas controller system. By applying a special algorithm, the laser gas consumption can be reduced by up to 50%. More than 96% of the gas used by the lasers is neon. Another rare gas that requires attention is Helium. Recently the unstable supply of helium became a serious worldwide issue. To cope with this situation, Gigaphoton is developing lasers that support completely helium-free operations.

In optical lithography, high-performance exposure tools are necessary to obtain not only fine patterns but also preciseness of the pattern width. Therefore, an accurate theoretical method is necessary to predict these values in practice. Conversely speaking, lithography experiments enables us to evaluate the validity of imaging theory. Thus some pioneer and valuable studies have been argued [1,2,3,4,5,6,7,8,9]. However there might be some ambiguity or no consensus for the treatment of diffraction by object in scalar imaging theory and a paradoxical phenomenon for the inclined entrance plane wave especially in vector imaging theory. Therefore we reconsider the imaging theory and compare the theoretical aerial image intensity with experimental pattern width.

As DUV multi-patterning requirements continue to become more stringent, it is critical that all sources of lithography patterning variability are characterized and monitored. Advanced process characterization studies have been enabled using Cymer’s novel technique to modulate Beam Divergence and Polarization, and Energy, Bandwidth, or Wavelength light source performance. These techniques have been instrumental in helping identify process sensitivities that enable proactive light source monitoring and excursion detection using SmartPulse^TM.

Demonstration of the benefits of these technologies is provided through results from recent experiments at imec. Changes in patterning performance are characterized using top down CD-SEM metrology, enabling excellent correlation between optical parameters and on wafer attributes for typical patterning geometries. In addition, new results show that changes in laser beam parameter performance can have measurable wafer patterning and/or illumination impacts. Chipmakers can benefit from the use of this capability to perform proactive, comprehensive characterization of current and next generation process nodes.

In high-NA and hyper-NA lithography systems, the polarization aberration of projection lens leads to imaging degradations. Typically, numerical simulations are used to explore the relationship. In this paper, analytical analysis for the impact of polarization aberration of projection lens on the aerial image of alternating phase-shift mask (Alt-PSM) is realized. The analytical expressions of image placement error (IPE) and best focus shift (BFS) caused by polarization aberration are derived from the intensity of aerial image. The derived expressions match simulation results extremely well, and can be used to understand more fully the detrimental impact of polarization aberration on lithographic imaging quality. The linear relationships between IPE and odd items of Pauli-Zernike polarization aberrations, as well as that between BFS and even items of Pauli-Zernike polarization aberrations are established, using linear polarization illumination. The accuracy of the linear relationships is assessed by the least square method.

As the scaling down of design rule for high-density memory device, the small depth of focus (DoF) budget may be deteriorated by focus leveling errors, which arises in unpredicted reflectivity from multilayer structures on the topographic wafer. The leveling sensors of ASML scanner use near infrared (NIR) range wavelength which can penetrate through most of films using in semiconductor fabrication such as photo-resist, bottom anti reflective coating (BARC) and dielectric materials. Consequently, the reflected light from underlying substructures would disturb leveling sensors from accurate leveling. The different pattern densities and layout characteristics between array and periphery of a memory chip are expected to result in different leveling signals. Furthermore, the process dependent variations between wafer central and edge areas are also considered to yield different leveling performances during wafer exposure.

In this study, lower blind contact immunity was observed for peripheral contacts comparing to the array contacts especially around wafer edge region. In order to overcome this problem, a series of investigations have been carried out. The wafer edge leveling optimization through circuit dependent focus edge clearance (CDFEC) option doesn’t get improvement. Air gauge improved process leveling (AGILE) function of ASML immersion scanner doesn’t show improved result either. The ILD uniformity improvement and step height treatments around wafer edge such as edge exclusion of film deposition and bevel etching are also ineffective to mitigate the blind contact problem of peripheral patterns. Altering the etch hard-mask stack is finally found to be an effective approach to alleviate the issue. For instance, through either containing high temperature deposition advanced patterning film (APF) in the hard-mask or inserting higher opaque film such as amorphous Si in between the hard-mask stack.

Aerial image calculation is the basis of the current lithography simulation. As the critical dimension (CD) of the integrated circuits continuously shrinks, the thick mask near-field calculation has increasing influence on the accuracy and efficiency of the entire aerial image calculation process. This paper develops a flexible librarybased approach to significantly improve the efficiency of the thick mask near-field calculation compared to the rigorous modeling method, while leading to much higher accuracy than the Kirchhoff approximation method. Specifically, a set of typical features on the fullchip are selected to serve as the training data, whose near-fields are pre-calculated and saved in the library. Given an arbitrary test mask, we first decompose it into convex corners, concave corners and edges, afterwards match each patch to the training layouts based on nonparametric kernel regression. Subsequently, we use the matched near-fields in the library to replace the mask patches, and rapidly synthesize the near-field for the entire test mask. Finally, a data-fitting method is proposed to improve the accuracy of the synthesized near-field based on least square estimate (LSE). We use a pair of two-dimensional mask patterns to test our method. Simulations show that the proposed method can significantly speed up the current FDTD method, and effectively improve the accuracy of the Kirchhoff approximation method.

The impact of mask three dimensions (M3D) effect on lithography processes is getting more pronounced from 32 nm nodes^1-2. In this paper, we report four research progresses on the M3Deffect. Firstly, the impacts of M3D effect on the best focus (BF) offset were studied with though pitch as test pattern. The M3D effect has negative impacts on the BF, generating the BF offset pattern by pattern. The BF offset strongly depends on MoSi film thickness (THK). However the impact of MoSi profile, or side wall angle (SWA) could be ignored. Secondly, M3D OPC is needed to mitigate the shift of dose and focus center. Thirdly, as long as enough shade, the thinner MoSi, the less BF shift, as electromagnetic field (EMF) effect makes space behave smaller, which leads to higher contrast but higher mask error enhancement factor(MEEF); So the trade-off between contrast and MEEF is needed. And MoSi THK 43.7 nm in production supposed to be the optimized value from this study. Finally, compared to attenuating phase shifting mask (att.PSM) mask, opaque MoSi on Glass (OMOG) mask is more robust in terms of MEEF, the normalized image logarithmic slope (NILS) etc., not obviously influenced by mask duty ratio.

The new ArF Immersion Laser, GT64A has been developed to support the next generation multiple-patterning process. It offers the industry’s highest output power of 120W with high stability and efficiency. 120W output power with auto-adjusting function enables to meet the requirements of various processes and makes higher-throughput possible even at 450mm-wafers. The increased wavelength stability and bandwidth stability can further improve overlay accuracy and CD error required for the next generation multiple-patterning lithography. Advanced gas control algorithm reduces the consumption of rare gases such as neon to a half. Helium-free operation is also under development to cope with the unstable supply of helium gases worldwide.

New advanced wavelength control and bandwidth control algorithm has been developed to meet tighter stability requirement for the next generation multiple-patterning lithography.

Forbidden pitches are the result of unwanted, non-linear effects that limit yield and not always well understood. Yet, as approximations, they are implicitly deployed through design rules. Many believe they result as a consequence of more complicated light sources. We develop an analytical model of aerial image quality as a function of light source. We show the effect is most pronounced for a point light source, the simplest of all. We develop a method to improve print image quality by illumination source optimization, and show promising first results. Additionally, it is shown how design rules capture forbidden pitches unsatisfactorily.

In recent years, with the availability of freeform sources, source optimization has emerged as one of the key techniques for achieving higher resolution without increasing the complexity of mask design. In this paper, an efficient source optimization approach using particle swarm optimization algorithm is proposed. The sources are represented by pixels and encoded into particles. The pattern fidelity is adopted as the fitness function to evaluate these particles. The source optimization approach is implemented by updating the velocities and positions of these particles. The approach is demonstrated by using two typical mask patterns, including a periodic array of contact holes and a vertical line/space design. The pattern errors are reduced by 66.1% and 39.3% respectively. Compared with the source optimization approach using genetic algorithm, the proposed approach leads to faster convergence while improving the image quality at the same time. The robustness of the proposed approach to initial sources is also verified.

Mask aligner lithography is very attractive for less-critical lithography layers and is widely used for LED, display, CMOS image sensor, micro-fluidics and MEMS manufacturing. Mask aligner lithography is also a preferred choice the semiconductor back-end for 3D-IC, TSV interconnects, advanced packaging (AdP) and wafer-level-packaging (WLP). Mask aligner lithography is a mature technique based on shadow printing and has not much changed since the 1980s. In shadow printing lithography a geometric pattern is transferred by free-space propagation from a photomask to a photosensitive layer on a wafer. The inherent simplicity of the pattern transfer offers ease of operation, low maintenance, moderate capital expenditure, high wafers-per-hour (WPH) throughput, and attractive cost-of-ownership (COO). Advanced mask aligner lithography (AMALITH) comprises different measures to improve shadow printing lithography beyond current limits. The key enabling technology for AMALITH is a novel light integrator systems, referred to as MO Exposure Optics® (MOEO). MOEO allows to fully control and shape the properties of the illumination light in a mask aligner. Full control is the base for accurate simulation and optimization of the shadow printing process (computational lithography). Now photolithography enhancement techniques like customized illumination, optical proximity correction (OPC), phase masks (AAPSM), half-tone lithography and Talbot lithography could be used in mask aligner lithography. We summarize the recent progress in advanced mask aligner lithography (AMALITH) and discuss possible measures to further improve shadow printing lithography.

As shrinkage of design features progresses, the difference in best focus positions among different patterns is becoming a fatal issue, especially when many patterns co-exist in a layer. The problem arises from three major factors: aberrations of projection optics, mask 3D topography effects, and resist thickness effects. Aberrations in projection optics have already been thoroughly investigated, but mask 3D topography effects and resist thickness effects are still under study. It is well known that mask 3D topography effects can be simulated by various Electro-magnetic Field (EMF) analysis methods. However, it is almost impossible to use them for full chip modeling because all of these methods are extremely computationally intensive. Consequently, they usually apply only to a limited range of mask patterns which are about tens of square micro meters in area. Resist thickness effects on best focus positions are rarely treated as a topic of lithography investigations. Resist 3D effects are treated mostly for resist profile prediction, which also requires an intensive EMF analysis when one needs to predict it accurately. In this paper, we present a simplified Virtual Aberration (VA) model to simulate both mask 3D induced effects and resist thickness effects. A conventional simulator, when applied with this simplified method, can factor in both mask 3D topography effects and resist thickness effects. Thus it can be used to model inter-pattern Best Focus Difference (BFD) issues with the least amount of rigorous EMF analysis.

With the introduction of negative tone develop (NTD) resists to production lithography nodes, multiple NTD resist modeling challenges have surpassed the accuracy limits of the existing modeling infrastructure developed for the positive polarity process. We report the evaluation of two NTD resist modeling algorithms. The new modeling terms represent, from the first principles, the NTD resist mechanisms of horizontal shrink and horizontal development bias. Horizontal shrink describes the impact of the physical process of out-gassing on remaining resist edge location. Horizontal development bias accounts for the differential in the peak and minimum development rate with exposure intensity observed in NTD formulations. We review specific patterning characteristics by feature type, modeling accuracy impact presented by these NTD mechanisms, and their description in our compact models (Compact Model 1, CM1). All the new terms complement the accuracy advantage observed with existing CM1 resist modeling infrastructure. The new terms were tested on various NTD layers. The results demonstrate consistent model accuracy improvement for both calibration and verification. Furthermore, typical NTD model fitting challenges, such as large SRAF-induced wafer CD jump, can be overcome by the new NTD terms. Finally, we propose a joint-tuning approach for the calibration of compact models for the NTD resist.

The optical proximity correction (OPC) model and post-OPC verification that takes the developed photoresist (PR) 3D profile into account is needed in the advanced 2Xnm node. The etch process hotspots caused by poor resist profile may not be fully identified during the lithography inspection but will only be observed after the subsequent etch process. A complete mask correction that targets to final etch CD requires not only a lithography R3D profile model but also a etch process compact model. The drawback of existing etch model is to treat the etch CD bias as a function of visibility and pattern density which do not contain the information of resist profile. One important factor to affect the etch CD is the PR lateral erosion during the etch process due to non-vertical PR side wall angle (SWA) and anisotropy of etch plasma source. A simple example is in transferring patterns from PR layer to thin hard mask (HM) layer, which is frequently used in the double pattern (DPT) process. The PR lateral erosion contributes an extra HM etch CD bias which is deviated from PR CD defined by lithography process. This CD bias is found to have a nontrivial dependency on the PR profile and cannot be described by the pattern density or visibility. In this report, we study the etch CD variation to resist SWA under various etch conditions. Physical effects during etch process such as plasma ion reflection and source anisotropy, which modify the local etch rate, are taken into considerations in simulation. The virtual data are generated by Synopsys TCAD tool Sentaurus Topography 3D using Monte Carlo engine. A simple geometry compact model is applied first to explain the behavior of virtual data, however, it works to some extent but lacks accuracy when plasma ion reflection comes into play. A modified version is proposed, for the first time, by including the effects of plasma ion reflection and source anisotropy. The new compact model fits the nonlinear etch CD bias very well for a wide range of resist SWAs from 65 to 90 degrees, which covers the resist profile diversities in most real situations. This result offers a potential application for both resist profile aware and etch process aware mask correction model in the mask synthesis flow.

Resist profile shapes become important for 22nm node and beyond as the process window shrinks. Degraded profile shapes for example may induce etching failures. Rigorous resist simulators can simulate a 3D resist profile accurately but they are not fast enough for correction or verification on a full chip. Compact resist models are fast but have traditionally modeled the resist in two dimensions. They provide no information on the resist loss and sidewall angle. However, they can be extended to predict resist profiles by proper setting of optical parameters and by accounting for vertical effects. Large resist shrinkages in NTD resists can also be included in the compact model. This article shows how a compact resist model in Calibre can be used to predict resist profiles and resist contours at arbitrary heights.

As feature size get smaller, it's crucial to gain depth of focus (DOF) common window in optical lithography. In addition to the DOF of individual patterns, the shift of the best focus between various patterns is significant reducing the common DOF. High-order spatial frequencies diffracted from sharp corners and small patterns on the mask induce additional phase terms and can shift the best focus significantly. We analyzed the correlation between the pattern shape after OPC correction and its corresponding DOF, and found that more complicated shapes lead to more focus shift. Wafer experiment and simulation confirm the predictions. This provides another index for future OPC application.

To ensure a high patterning quality, the etch effects have to be corrected within the OPC recipe in addition to the traditional lithographic effects. This requires the calibration of an accurate etch model and optimization of its implementation in the OPC flow. Using SEM contours is a promising approach to get numerous and highly reliable measurements especially for 2D structures for etch model calibration. A 28nm active layer was selected to calibrate and verify an etch model with 50 structures in total. We optimized the selection of the calibration structures as well as the model density. The implementation of the etch model to adjust the litho target layer allows a significant reduction of weak points. We also demonstrate that the etch model incorporated to the ORC recipe and run on large design can predict many hotspots.

The CMOS logic 22nm node was the last one done with single patterning. It used a highly regular layout style with Gridded Design Rules (GDR). Smaller nodes have required the same regular layout style but with multiple patterning for critical layers. A “line/cut” approach is being used to achieve good pattern fidelity and process margin.[1] As shown in Fig. 1, even with “line” patterns, pitch division will eventually be necessary.

For the “cut” pattern, Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective at the 20nm node and below.[2,3,4] Single patterning was found to be suitable down to 16nm, while double patterning extended optical lithography for cuts to the 10-12nm nodes. Design optimization avoided the need for triple patterning. Lines can be patterned with 193nm immersion with no complex OPC. The final line dimensions can be achieved by applying pitch division by two or four.[5]

In this study, we extend the scaling using simplified OPC to the 7nm node for critical FEOL and BEOL layers. The test block is a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops, scaled from previous experiments.

Simulation results show that for cuts at 7nm logic dimensions, the gate layer can be done with single patterning whose minimum pitch is 53nm, possibly some of the 1x metal layers can be done with double patterning whose minimum pitch is 53nm, and the contact layer will require triple patterning whose minimum pitch is 68nm. These pitches are less than the resolution limit of ArF NA=1.35 (72nm). However these patterns can be separated by a combination of innovative SMO for less than optical resolution limit and a process trick of hole-repair technique. An example of triple patterning coloring is shown in Fig 3. Fin and local interconnect are created by lines and trims. The number of trim patterns are 3 times (min. pitch=90nm) and twice (min. pitch=120nm), respectively. The small number of masks, large pitches, and simple patterns of trims come from the simple 1D layout design.

Experimental demonstration of these cut layers using design optimization, OPC-Lite, and conventional illuminators at the 7nm node dimensions will be presented. Lines were patterned with 193nm immersion with no complex OPC. The final line dimensions (22nm pitch) were achieved with pitch division 4.[5]

Traditionally, the optical proximity correction (OPC) is to deliver the solution to ensure the nominal after-development-inspection (ADI) contours on target. As the technology node keeps shrinking to 28nm and beyond, the OPC is expected to cover the lithography process window (PW), etch PW, and overlay margin as well. As a result, more and more advanced functions are included in OPC to achieve the awareness of multiple cost functions, such as the nominal EPE, PW effective EPE, the enclosure of above and underneath layers, and so on. These inclusions are at the cost of the run time and complexity of OPC solution. In this paper, we demonstrated a methodology by adopting design rule check (DRC) algorithm in repair flow to fix hot spots. In accordance to OPC verification check, the subsequent DRC movements were applied to those hot spots only. With a straightforward recipe tuning, a fast convergence of OPC can be achieved. The results exhibit the run time improvement without compromising the OPC performance. We further evaluated by real cases the effects of the DRC-based repair algorithm on the error convergence and final repair effects, by comparing to the standard OPC solution.

The optical proximity correction (OPC) designs a biased mask so as to ensure the after-development-inspection (ADI) contours could be on target. Meanwhile, the lithographic manufacture process is approaching the sub 28 nm technology node, imposing a tremendous challenge on OPC engineers. Even a well-tuned OPC recipe can render many off-target simulated contours for the most up-to-date chip designs; and these off-target contours indicate highly possible on wafer weak points. We have recently developed a high-performance repair flow that can automatically correct these OPC weak points based on the retargeting procedure. It is expected that one has to take both nominal and process window (PW) conditions into account to avoid potential on wafer weak points. For the contact holes, we require the nominal CD and PW CD be at least CD_nom and CD_pw, respectively. In some cases, it could be difficult to satisfy both nominal and PW CD constraints which may pose conflicts to each other. In this work, various strategies have been used to accommodate such conflicts; for instance, one can release the nominal constraint or replace the PW CD constrain by the PW area constrain. We perform a systematic study on the various specifications of these constraints, in order to select the most optimal setup for the nominal and PW constraints. These optimized specifications may allow us to perform a highly efficient repair on a contact layer.

As the technology node shrinks, ArF Immersion reaches the limitation of wafer patterning, furthermore weak point during the mask processing is generated easily. In order to make strong patterning result, the design house conducts lithography rule checking (LRC). Despite LRC processing, we found the weak point at the verification stage of optical proximity correction (OPC). It is called the hot spot point (HSP). In order to fix the HSP, many studies have been performed. One of the most general hot spot fixing (HSF) methods is that the modification bias which consists of “Line-Resizing” and “Space-Resizing”. In addition to the general rule biasing method, resolution enhancement techniques (RET) which includes the inverse lithography technology (ILT) and model based assist feature (MBAF) have been adapted to remove the hot spot and to maximize the process window. If HSP is found during OPC verification stage, various HSF methods can be applied. However, HSF process added on regular OPC procedure makes OPC turn-around time (TAT) increased.

In this paper, we introduce a new HSF method that is able to make OPC TAT shorter than the common HSF method. The new HSF method consists of two concepts. The first one is that OPC target point is controlled to fix HSP. Here, the target point should be moved to optimum position at where the edge placement error (EPE) can be 0 at critical points. Many parameters such as a model accuracy or an OPC recipe become the cause of larger EPE. The second one includes controlling of model offset error through target point adjustment. Figure 1 shows the case EPE is not 0. It means that the simulation contour was not targeted well after OPC process. On the other hand, Figure 2 shows the target point is moved -2.5nm by using target point control function. As a result, simulation contour is matched to the original layout. This function can be powerfully adapted to OPC procedure of memory and logic devices.

In optical proximity correction (OPC), the sub-resolution assist feature (SRAF) has been used to enhance the process window of main structures. However, the printing of SRAF on wafer is undesirable as this may adversely degrade the overall process yield if it is transferred into the final pattern. A reasonably accurate prediction model is needed during OPC to ensure that the SRAF placement and size have no risk of SRAF printing. Current common practice in OPC is either using the main OPC model or model threshold adjustment (MTA) solution to predict the SRAF printing. This paper studies the feasibility of SRAF printing prediction using logistic regression (LR). Logistic regression is a probabilistic classification model that gives discrete binary outputs after receiving sufficient input variables from SRAF printing conditions. In the application of SRAF printing prediction, the binary outputs can be treated as 1 for SRAFPrinting and 0 for No-SRAF-Printing. The experimental work was performed using a 20nm line/space process layer. The results demonstrate that the accuracy of SRAF printing prediction using LR approach outperforms MTA solution. Overall error rate of as low as calibration 2% and verification 5% was achieved by LR approach compared to calibration 6% and verification 15% for MTA solution. In addition, the performance of LR approach was found to be relatively independent and consistent across different resist image planes compared to MTA solution.

Precise and fast computation of aerial images are essential. Typical lithographic simulators employ a Köhler illumination system for which aerial imagery is obtained using a large number of Transmission Cross Coefficients (TCCs). These are generally computed by a slow numerical evaluation of a double integral. We review the general framework in which the 2D imagery is solved and then propose a fast and accurate method to obtain the TCCs. We acquire analytical solutions and thus avoid the complexity-accuracy trade-off encountered with numerical integration. Compared to other analytical integration methods, the one presented is faster, more general and more tractable.

Correlation of resist modeling of printed features with lithographic data is a necessary part of developing new lithographic processes. Recently, we have found a case in which the most advanced resist types sometimes show better behavior than expectations from optical simulation in terms of dose latitude, MEEF (mask error enhancement factor), and even CD variation through different pitches. This superior resist performance may allow greater margin for error in each component, such as mask, scanner, and metrology in very low-k1 lithography.

On the other hand, since the resist pattern CD for the most advanced resist is very much different from the prediction of optical simulation, it is a challenge to build OPC models using the exposure result with the resist. In order to solve this issue, we have tried to use several litho parameters to reduce the gap between optical simulation and resist CDs for OPC modeling. In this paper we discuss the effect of the parameters to reduce the gap between optical model and actual resist behavior with keeping superior performance as much as possible. The method we mention may be a key to use the most advanced resist in near future. As a result the life of ArF immersion lithography in the critical layer would be extended than we expect today.

Production lithography is undergoing a technology shift, and the requirements of beam delivery system (BDS) are increasing which also raises the precision requirements of the beam steering units (BSU) in BDS. In essence, the BSU is a two rotational degree of freedom platform. In this paper, a BSU based on 3-RPS flexure parallel mechanism is proposed. By analyzing the relationship between the unit’s dimensions and mechanics, a mathematical model is built. Then the BSU with a balance between lower stress of the flexure hinges and higher accuracy of the unit can be got by optimizing the dimensions with the mathematical model. Finally a simulation is conducted to verify the design.

The need for repeatable, reliable, and faster DUV ArF light source gas optimizations drove the development of Automated Gas Optimization (AGO). These automate the manual gas optimization procedure previously used to select the laser chamber gas pressures and in addition, bandwidth actuation settings, to deliver consistent performance and long gas lives, while maintaining stability and bounds on laser inputs. Manual gas optimization procedure requires at least two refills and an on-site visit by service personnel that can take over an hour to complete. This results in inconsistent light source performance, and sometimes unscheduled downtime. The key to AGO technology is the real-time estimation and monitoring of the laser’s gas and bandwidth states, and automatic adjustment of gas pressure and bandwidth actuators until the states reach their specified targets, thus creating a closed loop. AGO executes on every refill, typically complete in less than 5 minutes, and collect performance data to allow long-term trending. They include built-in safety features and flexibility to allow future upgrades of light source features or performance tuning. Deployed in many lasers in the field, AGO has proved to be a dependable automation, yielding repeatable, fast, and reliable optimizations and valuable long-term trending data used to assess chamber performance

As chipmakers continue to reduce feature sizes and shrink CDs on the wafer to meet customer needs, Cymer continues developing light sources that enable advanced lithography, and introducing innovations to improve productivity, wafer yield, and cost of ownership. In particular, the ETC controller provides improved spectral bandwidth and wavelength stability, which enables superior CD control and wafer yield for the chipmaker. This controller is a key technology in Cymer’s XLR 700ix and DynaPulse^TM products. Last year we reported that the XLR 600ix incorporates new controller technology called ETC for improvements in spectral bandwidth and wavelength stability. The Authors will present metrics demonstrating the performance and stability of systems that have been installed at chipmaker sites over the last year.

Chipmakers continued pressure to drive down costs while increasing utilization requires development in all areas. Cymer’s commitment to meeting customer’s needs includes developing solutions that enable higher productivity as well as lowering cost of lightsource operation. Improvements in system power efficiency and predictability were deployed to chipmakers’ in 2014 with release of our latest Master Oscillating gas chamber. In addition, Cymer has committed to reduced gas usage, completing development in methods to reduce Helium gas usage while maintaining superior bandwidth and wavelength stability. The latest developments in lowering cost of operations are paired with our advanced ETC controller in Cymer’s XLR 700ix product.

In semiconductor lithography, light sources play a significant role in the wafer production process as well as impacting the manufacturing cost per wafer. Chip manufacturers going forward will be challenged to develop new ways to become more cost effective than their competitors, and the software tools necessary to compete in this environment must be capable of effectively adapting to the unique needs of each manufacturer. Gigaphoton has developed a new highly customizable software system for managing light sources. It not only offers a simple and intuitive user interface that can be operated using a standard web browser on PCs, tablets, and smartphones, but also a platform for users and third parties to develop unique extensions and optimizations.

Semiconductor manufacturing industry has growing concerns over future environmental impacts as fabs expand and new generations of equipment become more powerful. Especially rare gases supply and price are one of prime concerns for operation of high volume manufacturing (HVM) fabs. Over the past year it has come to our attention that Helium and Neon gas supplies could be unstable and become a threat to HVM fabs. To address these concerns, Gigaphoton has implemented various green technologies under its EcoPhoton program. One of the initiatives is GigaTwin deep ultraviolet (DUV) lithography laser design which enables highly efficient and stable operation. Under this design laser systems run with 50% less electric energy and gas consumption compared to conventional laser designs. In 2014 we have developed two technologies to further reduce electric energy and gas efficiency. The electric energy reduction technology is called eGRYCOS (enhanced Gigaphoton Recycled Chamber Operation System), and it reduces electric energy by 15% without compromising any of laser performances. eGRYCOS system has a sophisticated gas flow design so that we can reduce cross-flow-fan rotation speed. The gas reduction technology is called eTGM (enhanced Total gas Manager) and it improves gas management system optimizing the gas injection and exhaust amount based on laser performances, resulting in 50% gas savings. The next steps in our roadmap technologies are indicated and we call for potential partners to work with us based on OPEN INNOVATION concept to successfully develop faster and better solutions in all possible areas where green innovation may exist.