Proceedings Volume 9427 is from: Logo
SPIE ADVANCED LITHOGRAPHY
22-26 February 2015
San Jose, California, United States
Front Matter: Volume 9427
Proc. SPIE 9427, Front Matter: Volume 9427, 942701 (22 April 2015); doi: 10.1117/12.2193828
Invited Session I
Proc. SPIE 9427, The daunting complexity of scaling to 7NM without EUV: pushing DTCO to the extreme, 942702 (18 March 2015); doi: 10.1117/12.2175509
Layout Patterns Applications
Proc. SPIE 9427, High coverage of litho hotspot detection by weak pattern scoring, 942703 (18 March 2015); doi: 10.1117/12.2087473
Proc. SPIE 9427, A pattern-based methodology for optimizing stitches in double-patterning technology, 942704 (18 March 2015); doi: 10.1117/12.2085955
Proc. SPIE 9427, Fast detection of manufacturing systematic design pattern failures causing device yield loss, 942705 (18 March 2015); doi: 10.1117/12.2085307
Proc. SPIE 9427, Topology and context-based pattern extraction using line-segment Voronoi diagram, 942706 (18 March 2015); doi: 10.1117/12.2085547
Multipatterning
Proc. SPIE 9427, A systematic framework for evaluating standard cell middle-of-line (MOL) robustness for multiple patterning, 942707 (18 March 2015); doi: 10.1117/12.2085918
Proc. SPIE 9427, Self-aligned quadruple patterning-compliant placement, 942708 (26 March 2015); doi: 10.1117/12.2085705
Proc. SPIE 9427, Impact of a SADP flow on the design and process for N10/N7 metal layers, 942709 (18 March 2015); doi: 10.1117/12.2085923
Proc. SPIE 9427, An efficient auto TPT stitch guidance generation for optimized standard cell design, 94270A (18 March 2015); doi: 10.1117/12.2085834
Proc. SPIE 9427, Yield-aware mask assignment using positive semi-definite relaxation in LELECUT triple patterning, 94270B (26 March 2015); doi: 10.1117/12.2085285
Invited Session II
Proc. SPIE 9427, DTCO at N7 and beyond: patterning and electrical compromises and opportunities, 94270C (18 March 2015); doi: 10.1117/12.2178997
Layout Optimization and Verification I
Proc. SPIE 9427, Layout optimization with assist features placement by model based rule tables for 2x node random contact, 94270D (18 March 2015); doi: 10.1117/12.2085460
Proc. SPIE 9427, Standard cell design in N7: EUV vs. immersion, 94270E (18 March 2015); doi: 10.1117/12.2085739
Proc. SPIE 9427, Layout dependent effects analysis on 28nm process, 94270F (18 March 2015); doi: 10.1117/12.2087443
Proc. SPIE 9427, Breaking through 1D layout limitations and regaining 2D design freedom Part I: 2D layout decomposition and stitching techniques for hybrid optical and self-aligned multiple patterning, 94270G (18 March 2015); doi: 10.1117/12.2085738
Design Interaction with Metrology: Joint Session with Conferences 9424 and 9427
Proc. SPIE 9427, Full chip two-layer CD and overlay process window analysis, 94270H (18 March 2015); doi: 10.1117/12.2086368
DFM (Design and Litho Optimization): Joint Session with Conferences 9426 and 9427
Proc. SPIE 9427, Quantitative evaluation of manufacturability and performance for ILT produced mask shapes using a single-objective function, 94270I (18 March 2015); doi: 10.1117/12.2087111
Proc. SPIE 9427, Akaike information criterion to select well-fit resist models, 94270J (18 March 2015); doi: 10.1117/12.2085770
Proc. SPIE 9427, Fast source optimization by clustering algorithm based on lithography properties, 94270K (18 March 2015); doi: 10.1117/12.2087007
Circuit Variability
Proc. SPIE 9427, Statistical modeling of SRAM yield performance and circuit variability, 94270M (18 March 2015); doi: 10.1117/12.2085844
Proc. SPIE 9427, Layout optimization and trade-off between 193i and EUV-based patterning for SRAM cells to improve performance and process variability at 7nm technology node, 94270O (18 March 2015); doi: 10.1117/12.2086100
DSA Design for Manufacturability: Joint Session with Conferences 9423, 9426, and 9427
Proc. SPIE 9427, Incorporating DSA in multipatterning semiconductor manufacturing technologies, 94270P (18 March 2015); doi: 10.1117/12.2084776
Layout and Optimization and Verification II
Proc. SPIE 9427, Design layout analysis and DFM optimization using topological patterns, 94270Q (26 March 2015); doi: 10.1117/12.2086904
Proc. SPIE 9427, Automation for pattern library creation and in-design optimization, 94270R (18 March 2015); doi: 10.1117/12.2087100
Proc. SPIE 9427, A new lithography hotspot detection framework based on AdaBoost classifier and simplified feature extraction, 94270S (18 March 2015); doi: 10.1117/12.2085790
Proc. SPIE 9427, A methodology to optimize design pattern context size for higher sensitivity to hotspot detection using pattern association tree (PAT), 94270T (18 March 2015); doi: 10.1117/12.2086954
Poster Session
Proc. SPIE 9427, 20nm CMP model calibration with optimized metrology data and CMP model applications, 94270U (18 March 2015); doi: 10.1117/12.2085728
Proc. SPIE 9427, Topography aware DFM rule based scoring for silicon yield modeling, 94270V (18 March 2015); doi: 10.1117/12.2085733
Proc. SPIE 9427, A compact model to predict pillar-edge-roughness effects on 3D vertical nanowire MOSFETs using the perturbation method, 94270W (18 March 2015); doi: 10.1117/12.2085919
Proc. SPIE 9427, Efficient etch bias compensation techniques for accurate on-wafer patterning, 94270X (18 March 2015); doi: 10.1117/12.2085956
Proc. SPIE 9427, An efficient lithographic hotspot severity analysis methodology using Calibre PATTERN MATCHING and DRC application, 94270Y (18 March 2015); doi: 10.1117/12.2086041
Proc. SPIE 9427, A holistic methodology to drive process window entitlement and its application to 20nm logic, 94270Z (18 March 2015); doi: 10.1117/12.2086101
Proc. SPIE 9427, Practical DTCO through design/patterning exploration, 942710 (18 March 2015); doi: 10.1117/12.2086355
Proc. SPIE 9427, Comparison of OPC job prioritization schemes to generate data for mask manufacturing, 942711 (18 March 2015); doi: 10.1117/12.2086927
Proc. SPIE 9427, VLSI physical design analyzer: A profiling and data mining tool, 942712 (18 March 2015); doi: 10.1117/12.2087078
Proc. SPIE 9427, The cell pattern correction through design-based metrology, 942713 (18 March 2015); doi: 10.1117/12.2085004
Proc. SPIE 9427, Breaking through 1D layout limitations and regaining 2D design freedom part II: stitching yield modeling and optimization, 942714 (18 March 2015); doi: 10.1117/12.2085898
Proc. SPIE 9427, Automatic DFM methodology for bit line pattern dummy, 942715 (18 March 2015); doi: 10.1117/12.2185545
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