This PDF file contains the front matter associated with SPIE Proceedings Volume 9780, including the Title Page, Copyright information, Table of Contents, Introduction (if any), and Conference Committee listing.

Historically, progress in lithography has been driven by steady advances in exposure tool and optical technology; shorter wavelength, higher numerical aperture (NA) and resolution enhancement techniques to drive the k₁ factor as close as possible to the physical limit. Over the past decade, however, the pace of progress has been gated more by patterning – what we do after the resist image is printed – than by higher resolution imaging. The emphasis on patterning rather than just printing has created new pressures in many parts of the overall process, beginning with the design itself. The breakdown of lithographic error budgets into CD and OL tolerances has given way to total edge placement error (EPE) budgets where CD, OL and edge roughness, as well as film and etch variations, must all be controlled to meet the required tolerances. Contact hole and cut mask placement have likewise been tightened to single digit EPE budgets. Collaborative research between technology specialists in multiple areas, such as metrology, etch, process control and simulation, will all be required to deliver these patterning solutions for some years to come. This paper will describe some of these challenges in more detail, and suggest directions for future research to keep optical lithography relevant even below the 10 nm node.

In the past 10 years, immersion lithography has been the most effective high volume manufacturing method for the critical layers of semiconductor devices. Thinking of the next 10 years, we can expect continuous improvement on existing 300 mm wafer scanners with better accuracy and throughput to enhance the total output value per input cost. This value productivity, however, can be upgraded also by larger innovations which might happen in optical lithography. In this paper, we will discuss the possibilities and the impossibilities of potential innovation ideas of optical lithography, which are 450 mm wafer, optical maskless, multicolor lithography, and metamaterial.

Since the 28nm node, the resolution of ArFi lithography tools has been limited by the fixed Numerical Aperture of the scanners (1.35) at approximately 40-45 nm half-pitch. As a consequence, the shrink cadence identified by Moore’s law requires more complex patterning flows such as multiple Litho-Etch (LE) steps as well as spacer techniques (Self-Aligned Double Patterning (SADP)). To ensure yield it is necessary to optimize the total Edge Placement Error, a combination of Overlay, Global CDU, LCDU, OPC and other process and equipment errors.

In this presentation I will discuss some of the ways that these contributors can be measured, modeled and corrected as part of a Holistic Lithography methodology. Multiple-patterning techniques can be combined with EUV lithography to continue Moore’s law down to final pattern dimensions of 5-6 nm half pitch.

In this paper, we discuss the lithographic qualification of high transmission (High T) mask for Via and contact hole applications in 10nm node and beyond. First, the simulated MEEF and depth of focus (DoF) data are compared between the 6% and High T attnPSM masks with the transmission of High T mask blank varying from 12% to 20%. The 12% High T blank shows significantly better MEEF and larger DoF than those of 6% attnPSM mask blank, which are consistent with our wafer data. However, the simulations show no obvious advantage in MEEF and DoF when the blank transmittance is larger than 12%. From our wafer data, it has been seen that the common process window from High T mask is 40nm bigger than that from the 6% attnPSM mask. In the elongated bar structure with smaller aspect ratio, 1.26, the 12% High T mask shows significantly less develop CD pull back in the major direction. Compared to the High T mask, the optimized new illumination condition for 6% attnPSM shows limited improvement in MEEF and the DoF through pitch. In addition, by using the High T mask blank, we have also investigated the SRAF printing, side lobe printing and the resist profile through cross sections, and no patterning risk has been found for manufacturing. As part of this work new 12% High T mask blank materials and processes were developed, and a brief overview of key mask technology development results have been shared. Overall, it is concluded that the High T mask, 12% transmission, provides the most robust and extendable lithographic solution for 10nm node and beyond.

With shrinking design rules, the overall patterning requirements are getting aggressively tighter. For the 7-nm node and below, allowable CD uniformity variations are entering the Angstrom region (ref [1]). Optimizing inter- and intra-field CD uniformity of the final pattern requires a holistic tuning of all process steps. In previous work, CD control with either litho cluster or etch tool corrections has been discussed. Today, we present a holistic CD control approach, combining the correction capability of the etch tool with the correction capability of the exposure tool. The study is done on 10-nm logic node wafers, processed with a test vehicle stack patterning sequence. We include wafer-to-wafer and lot-to-lot variation and apply optical scatterometry to characterize the fingerprints. Making use of all available correction capabilities (lithography and etch), we investigated single application of exposure tool corrections and of etch tool corrections as well as combinations of both to reach the lowest CD uniformity. Results of the final pattern uniformity based on single and combined corrections are shown. We conclude on the application of this holistic lithography and etch optimization to 7nm High-Volume manufacturing, paving the way to ultimate within-wafer CD uniformity control.

Patterning solutions based on ArF immersion lithography are the fundamental enablers of device scaling. In order to meet the challenges of industry technology roadmaps, tool makers in the DUV lithography area are continuously investigating all of the interactions between equipment parameters and patterning in order to identify potential margins of improvement. Cymer, a light source manufacturer, is fully involved and is playing a crucial role in these investigations. As demonstrated by recent studies^[1], a significant improvement to multiple patterning solutions can be achieved by leveraging light source capabilities. In particular, bandwidth is a key knob that can be leveraged to improve patterning. While previous publications^[1,2] assessed contrast loss induced by increased bandwidth, this work will expand the research in the opposite direction and will investigate how patterning can be affected by improved image contrast achieved through a reduction in bandwidth. The impact of lower bandwidth is assessed using experimental and simulation studies and provide persuasive results which suggest continued studies in this area.

As overlay margin is getting tighter, traditional overlay correction method is not enough to secure more overlay margin without extended correction potential on lithography tool. Timely, the lithography tool has a capability of wafer to wafer correction. From these well-timed industry’s preparations, the uncorrected overlay error from current sampling in a lot could be corrected for yield enhancement.

In this paper, overlay budget break was performed prior to experiments with the purpose of estimating amount of overlay improvement. And wafer to wafer correction was simulated to the specified layer of a 2x node DRAM device. As a result, not only maximum 94.4% of residual variation improvement is estimated, but also recognized that more samplings to cover all wafer’s behavior is inevitable. Integrated metrology with optimized sampling scheme was also introduced as a supportive method for more samplings.

In order to optimize yield in DRAM semiconductor manufacturing for 2x nodes and beyond, the (processing induced) overlay fingerprint towards the edge of the wafer needs to be reduced. Traditionally, this is achieved by acquiring denser overlay metrology at the edge of the wafer, to feed field-by-field corrections. Although field-by-field corrections can be effective in reducing localized overlay errors, the requirement for dense metrology to determine the corrections can become a limiting factor due to a significant increase of metrology time and cost. In this study, a more cost-effective solution has been found in extending the regular correction model with an edge-specific component. This new overlay correction model can be driven by an optimized, sparser sampling especially at the wafer edge area, and also allows for a reduction of noise propagation. Lithography correction potential has been maximized, with significantly less metrology needs. Evaluations have been performed, demonstrating the benefit of edge models in terms of on-product overlay performance, as well as cell based overlay performance based on metrology-to-cell matching improvements. Performance can be increased compared to POR modeling and sampling, which can contribute to (overlay based) yield improvement. Based on advanced modeling including edge components, metrology requirements have been optimized, enabling integrated metrology which drives down overall metrology fab footprint and lithography cycle time.

Overlay is one of the key factors which enables optical lithography extension to 1X node DRAM manufacturing. It is natural that accurate wafer alignment is a prerequisite for good device overlay. However, alignment failures or misalignments are commonly observed in a fab. There are many factors which could induce alignment problems. Low alignment signal contrast is one of the main issues. Alignment signal contrast can be degraded by opaque stack materials or by alignment mark degradation due to processes like CMP. This issue can be compounded by mark sub-segmentation from design rules in combination with double or quadruple spacer process. Alignment signal contrast can be improved by applying new material or process optimization, which sometimes lead to the addition of another process-step with higher costs. If we can amplify the signal components containing the position information and reduce other unwanted signal and background contributions then we can improve alignment performance without process change. In this paper we use ASML's new alignment sensor (as was introduced and released on the NXT:1980Di) and sample wafers with special stacks which can induce poor alignment signal to demonstrate alignment and overlay improvement.

Demand for ever increasing level of microelectronics integration continues unabated, driving the reduction of the integrated circuit critical dimensions, and escalating requirements for image overlay and pattern dimension control. The challenges to meet these demands are compounded by requirement that pattern edge placement errors be at single nanometer levels. Layout design together with the patterning tools performance play key roles in determining location of the pattern edges at different device layers. However, complexities of the layout design often lead to stringent tradeoffs for viable optical proximity correction and imaging strategy solutions. As a result, in addition to scanner overlay performance, pattern imaging plays a key role in the pattern edge placement. The imaging contributes to edge displacement by impacting the image dimensions and by shifting the images relative to their target locations. In this report we discuss various aspects of advanced image control at 10 nm integrated circuit design rules. We analyze the impact of pattern design and scanner performance on pattern edges. We present an example of complex, three step litho-etch patterning involving immersion scanners. We draw conclusion on edge placement control when complex images interact with wafer topography.

As technology node has been shrinking for bit growth, various technologies have been developed for high productivity. Nevertheless, lithography technology is close to its limit. In order to overcome these limits, EUV(Extreme Ultraviolet Lithography) and DSA(Directed Self-Assembly) are being developed, but there still exists problems for mass production. Currently, all lithography technology developments focus on solving the problems related to fine patterning and widening process window.

One of the technologies is NTD(Negative Tone Development) which uses inverse development compared to PTD(Positive Tone Development). The exposed area is eliminated by positive developer in PTD, whereas the exposed area is remained in NTD. It is well known that NTD has better characteristics compared to PTD in terms of DOF(Depth of Focus) margin, MEEF(Mask Error Enhancement Factor), and LER(Line End Roughness) for both small contact holes and isolated spaces [1]. Contact hole patterning is especially more difficult than space patterning because of the lower image contrast and smaller process window [2]. Thus, we have focused on the trend of both NTD and PTD contact hole patterns in various environments. We have analyzed optical performance of both NTD and PTD according to size and pitch by SMO(Source Mask Optimization) software. Moreover, the simulation result of NTD process was compared with the NTD wafer level performance and the process window variation of NTD was characterized through both results. This result will be a good guideline to avoid DoF loss when using NTD process for contact layers with various contact types.

In this paper, we studied the impact of different sources on various combinations of pattern sizes and pitches while estimating DOF trends aside from source and pattern types.

The printing of contact holes using positive tone development typically requires the interference of more than the 0th and 1st diffracted orders. In the 2d case and cQuad illumination in a positive tone process, if (0,0), (±1,0), and (0,±1) are exclusively present, the relevant contrast for imaging can in the best case not rise above 0.33, which is typically insufficient for a good process window. And this maximum value can only be achieved if the (0,0) and (±1,0) orders are matched to give a perfect sine wave of perfect contrast in y while the (0,0) and (0,±1) orders yield perfect contrast in x. In reality, the contrast is quite a bit lower. On the other hand, for negative tone development we are interested in the minima of the intensity–the dark locations in the image–and if we can manage to reduce the intensity in the minima we can achieve a high contrast image. Through a choice of RET and illumination, we manage to achieve a resolution for contact holes in 2d at k₁ values that can otherwise be achieved only for 1d imaging.

Earlier work has been done on double exposures that exposed in the same resist a horizontal grating with x-dipoles and subsequently a vertical grating with y dipoles, without intermediate process steps. This yielded a high contrast image in resist at k₁ <0.3.¹ We show that an equivalent result can be achieved in a single exposure with a single mask, at admittedly high dose. We investigate the process parameters and the related mask tolerances, and find a non-intuitive result for the mask pattern that yields an optimized image at given mask specifications. Finally, we investigate the extension of this technique to EUV through simulations and experiments.

With shrinking feature size, runtime has become a limitation of model-based OPC (MB-OPC). A few machine learning-guided OPC (ML-OPC) have been studied as candidates for next-generation OPC, but they all employ too many parameters (e.g. local densities), which set their own limitations. We propose to use basis functions of polar Fourier transform (PFT) as parameters of ML-OPC. Since PFT functions are orthogonal each other and well reflect light phenomena, the number of parameters can significantly be reduced without loss of OPC accuracy. Experiments demonstrate that our new ML-OPC achieves 80% reduction in OPC time and 35% reduction in the error of predicted mask bias when compared to conventional ML-OPC.

The use of optical proximity correction (OPC) demands increasingly accurate models of the photolithographic process. Model building and inference techniques in the data science community have seen great strides in the past two decades which make better use of available information. This paper aims to demonstrate the predictive power of Bayesian inference as a method for parameter selection in lithographic models by quantifying the uncertainty associated with model inputs and wafer data. Specifically, the method combines the model builder's prior information about each modelling assumption with the maximization of each observation's likelihood as a Student's t-distributed random variable. Through the use of a Markov chain Monte Carlo (MCMC) algorithm, a model's parameter space is explored to find the most credible parameter values. During parameter exploration, the parameters' posterior distributions are generated by applying Bayes' rule, using a likelihood function and the a priori knowledge supplied. The MCMC algorithm used, an affine invariant ensemble sampler (AIES), is implemented by initializing many walkers which semiindependently explore the space. The convergence of these walkers to global maxima of the likelihood volume determine the parameter values' highest density intervals (HDI) to reveal champion models. We show that this method of parameter selection provides insights into the data that traditional methods do not and outline continued experiments to vet the method.

Optimization of OPC recipes is not trivial due to multiple parameters that need tuning and their correlation. Usually, no standard methodologies exist for choosing the initial recipe settings, and in the keyword development phase, parameters are chosen either based on previous learning, vendor recommendations, or to resolve specific problems on particular special constructs. Such approaches fail to holistically quantify the effects of parameters on other or possible new designs, and to an extent are based on the keyword developer’s intuition. In addition, when a quick fix is needed for a new design, numerous customization statements are added to the recipe, which make it more complex.

The present work demonstrates the application of Genetic Algorithm (GA) technique for optimizing OPC recipes. GA is a search technique that mimics Darwinian natural selection and has applications in various science and engineering disciplines. In this case, GA search heuristic is applied to two problems: (a) an overall OPC recipe optimization with respect to selected parameters and, (b) application of GA to improve printing and via coverage at line end geometries. As will be demonstrated, the optimized recipe significantly reduced the number of ORC violations for case (a). For case (b) line end for various features showed significant printing and filling improvement.

Over the years, Lithography Engineers continue to focus on CD control, overlay and process capability to meet current node requirements for yield and device performance. Reducing or eliminating variability in any process will have significant impact, but the sources of variability in any lithography process are many. The goal from the light source manufacturer is to further enable capability and reduce variation through a number of parameters. ^{(1, 2, 3, 4)}

Recent improvements in bandwidth control have been realized in the XLR platform with Cymer’s DynaPulse^TM control technology. This reduction in bandwidth variation translates in the further reduction of CD variation in device structures ^5,6. The Authors will review the methodology for determining the impact that bandwidth variation has on CD dose, focus, pitch and bandwidth, which is required to build a dynamic model. This assists in understanding the impact that bandwidth variability has on the accuracy of the Source and Mask optimization and the overall OPC model, which is reviewed and demonstrated.

The introduction of DSA for lithography is still obstructed by a number of technical issues including the lack of a comprehensive computational platform. This work presents a direct source/mask/DSA optimization (SMDSAO) method, which incorporates standard lithographic metrics and figures of merit such as the maximization of process windows. The procedure is demonstrated for a contact doubling example, assuming grapho-epitaxy-DSA. To retain a feasible runtime, a geometry-based Interface Hamiltonian DSA model is employed. The feasibility of this approach is demonstrated through several results and their comparison with more rigorous DSA models.

Self-Aligned Via (SAV) process is commonly used in back end of line (BEOL) patterning. As the technology node advances, tightening CD and overlay specs require continuous improvement in model accuracy of the SAV process. Traditional single layer Variable Etch Bias (VEB) model is capable of describing the micro-loading and aperture effects associated with the reactive ion etch (RIE), but it does not include effects from under layers. For the SAV etch, a multi-layer VEB model is needed to account for the etch restriction from metal trenches. In this study, we characterize via post-etch dimensions through pitch and through metal trench widths, and show that VEB model prediction accuracy for SAV CDs after SAV formation can be significantly improved by applying a multi-layer scheme. Using a multi-layer VEB, it is demonstrated that the output via size changes with varying trench dimensions, which matches the silicon results. The model also reports via shape post-etch as a function of trench environment, where elliptical vias are correctly produced. The multi-layer VEB model can be applied both multi-layer correction and verification in full chip flow. This paper will also suggest that the multi-layer VEB model can be used in other FEOL layers with interlayer etch process effects, such as gate cut, to support the robustness of new model.

The Self-Aligned Quadruple Patterning (SAQP) process is one of the most suitable techniques for the patterning of under-20 nm half-pitch lines and spaces (L/S) patterns because it requires only one lithography step, resulting in a relatively low process cost. A serious problem when applying the SAQP process to real devices is the printability of defects in the photomask to the wafer because the effect of the mask defects may be enlarged when the defects are transferred to the spacer pattern. In this study, we evaluate the mask defect printability for both opaque and clear defects in the SAQP process in order to clarify the limit size of the defects on the photomask and to clarify whether the acceptable mask defect size given by ITRS was too small. The defect sizes of both the opaque and clear defects were relaxed as the wafer process progressed from lithography to SAQP. The acceptable mask defect size in the SAQP process found to be 70 nm, which is relaxed from that in ITRS2013.

Standard cell pin access has become one of the most challenging issues for the back-end physical design in sub-14nm technology nodes due to increased pin density, limited number of routing tracks, and complex DFM rules/constraints from multiple patterning lithography. The standard cell I/O pin access problem is very difficult also because the access points of each pin are limited and they interfere with each other. There have been several studies across various standard cell and physical design stages, including standard cell pin access optimization, placement mitigation and routing planning, to achieve overall pin access optimization. In this paper, we will introduce a holistic approach across different design stages to deal with the pin access issue while accommodating the complex DFM constraints in advanced lithography.

The lithographic performance of a photomask is sensitive to shape uncertainty caused by manufacturing and measurement errors. This work proposes incorporating the photomask shape uncertainty in computational lithography such as inverse lithography. The shape uncertainty of the photomask is quantitatively modeled as a random field in a level-set method framework. With this, the shape uncertainty can be characterized by several parameters, making it computationally tractable to be incorporated in inverse lithography technique (ILT). Simulations are conducted to show the effectiveness of using this method to represent various kinds of shape variations. It is also demonstrated that incorporating the shape variation in ILT can reduce the mask error enhancement factor (MEEF) values of the optimized patterns, and improve the robustness of imaging performance against mask shape fluctuation.

Modern optical applications have special demands on the lithographic fabrication technologies. This relates to the lateral shape of the structures as well as to their three dimensional surface profile. On the other hand optical nano-structures are often periodic which allows for the use of dedicated lithographic exposure principles. The paper briefly reviews actual developments in the field of optical nano-structure generation. Special emphasis will be given to two technologies: electron-beam lithography based on a flexible cell-projection method and the actual developments in diffractive mask aligner lithography. Both offer a cost effective fabrication alternative for high resolution structures or three-dimensional optical surface profiles.

We developed a novel LED projection based direct write grayscale lithography system for the generation of optical surface profiles such as micro-lenses, diffractive elements, diffusors, and micro freeforms. The image formation is realized by a LCoS micro-display which is illuminated by a 405 nm UV High Power LED. The image on the display can be demagnified from factors 5x to 100x with an exchangeable lens. By controlling exposure time and LED power, the presented technique enables a highly dynamic dosage control for the exposure of h-line sensitive photo resist. In addition, the LCoS micro-display allows for an intensity control within the micro-image which is particularly advantageous to eliminate surface profile errors from stitching and limited homogeneity from LED illumination. Together with an accurate calibration of the resist response this leads to a superior low surface error of realized profiles below <0.2% RMS. The micro-display is mounted on a 3-axis (XYθ) stage for precise alignment. The substrate is brought into position with an air bearing stage which addresses an area of 500 × 500 mm² with a positioning accuracy of <100 nm. As the exposure setup performs controlled motion in the z-direction the system to maintain the focal distance and lithographic patterning on non-planar surfaces to some extent. The exposure concept allows a high structure depth of more than 100 μm and a spatial resolution below 1 μm as well as the possibility of very steep sidewalls with angles larger than >80°. Another benefit of the approach is a patterning speed up to 100 cm²/h, which allows fabricating large-scale optics and microstructures in an acceptable time. We present the setup and show examples of micro-structures to demonstrate the performance of the system, namely a refractive freeform array, where the RMS surface deviation does not exceed 0.2% of the total structure depth of 75 μm. Furthermore, we show that this exposure tool is suitable to generate diffractive optical elements as well as freeform optics and arrays with a high aspect ratio and structure depth showing a superior optical performance. Lastly we demonstrate a multi-level diffraction grating on a curved substrate.

This paper introduces Firefly, an optical lithography origination system that has been developed to produce holographic masters of high quality. This mask-less lithography system has a resolution of 418 nm half-pitch, and generates holographic masters with the optical characteristics required for security applications of level 1 (visual verification), level 2 (pocket reader verification) and level 3 (forensic verification). The holographic master constitutes the main core of the manufacturing process of security holographic labels used for the authentication of products and documents worldwide. Additionally, the Firefly is equipped with a software tool that allows for the hologram design from graphic formats stored in bitmaps. The software is capable of generating and configuring basic optical effects such as animation and color, as well as effects of high complexity such as Fresnel lenses, engraves and encrypted images, among others. The Firefly technology gathers together optical lithography, digital image processing and the most advanced control systems, making possible a competitive equipment that challenges the best technologies in the industry of holographic generation around the world. In this paper, a general description of the origination system is provided as well as some examples of its capabilities.

Shaping of light behind masks using different techniques is the milestone of the printing industry. The aerial image distribution or the intensity distribution at the printing distances defines the resolution of the structure after printing. Contrast and phase are the two parameters that play a major role in shaping of light to get the desired intensity pattern. Here, in contrast to many other contributions that focus on intensity, we discuss the phase evolution for different structures. The amplitude or intensity characteristics of the structures in a binary mask at different proximity gaps have been analyzed extensively for many industrial applications. But the phase evolution from the binary mask having OPC structures is not considered so far. The mask we consider here is the normal amplitude binary mask but having high resolution Optical Proximity Correction (OPC) structures for corners. The corner structures represent a two dimensional problem which is difficult to handle with simple rules of phase masks design and therefore of particular interest. The evolution of light from small amplitude structures might lead to high contrast by creating sharp phase changes or phase singularities which are points of zero intensity. We show the phase modulation at different proximity gaps and can visualize the shaping of light according to the phase changes. The analysis is done with an instrument called High Resolution Interference Microscopy (HRIM), a Mach-Zehnder interferometer that gives access to three-dimensional phase and amplitude images. The current paper emphasizes on the phase measurement of different optical proximity correction structures, and especially on corners of a binary mask.

Prime silicon wafers are ideal substrates for lithographic patterning, with tight flatness specifications for focus control. Process engineers are painfully aware that in-process product wafers can substantially depart from this ideal substrate. Wafer processing can induce non-flatness leading to focus problems, or distort the wafer leading to overlay issues. Thus processes from outside the lithography sector can impact yield by ruining lithographic pattern quality. Double-sided optical interferometric metrology is the standard method to assess the flatness of blank silicon wafers. In the last several years, a similar Patterned Wafer Geometry (PWG) metrology tool is able to measure in-process patterned wafers. The apparent surface seen by an interferometer may be different than the true surface due to transparent thin films, a discrepancy that we call "false topography". Modeling results will demonstrate the use of a thin opaque film to reduce the problem. PWG metrology offers compelling advantages for the practical investigation of process-induced focus and overlay problems. The paper will include several examples of process learning from PWG metrology.

Adjustment and control of the illumination pupil asymmetry is relevant for wafer alignment and overlay of lithography tools. Pupil asymmetries can cause a tilt in aerial image (Aerial Image Tilt, or AIT). This AIT, combined with a focus offset, leads to a horizontal image shift. Pupil asymmetries can be related to a shift of the entire illumination pupil (geometrical telecentricity) caused by illuminator misalign. Another type of pupil asymmetry is energetic imbalance (quantified by pupil Center of Gravity, COG). The scanner can show pupil variation across the exposure slit.

In general the COG at the edge of the slit is often worse than in the center part of the slit. Recently, ASML has released the NXT:1980Di that is equipped with an enhanced illuminator to improve pupil COG variation across the slit. In this paper we explore the performance of this scanner system and show that the AIT variation across the slit is also reduced significantly.

High throughput with high resolution imaging has been key to the development of leading-edge microlithography. However, management of thermal aberrations due to lens heating during exposure has become critical for simultaneous achievement of high throughput and high resolution. Thermal aberrations cause CD drift and overlay error, and these errors lead directly to edge placement errors (EPE). Management and control of high order thermal aberrations is a critical requirement. In this paper, we will show practical performance of the lens heating with dipole and other typical illumination conditions for finer patterning. We confirm that our new control system can reduce the high-order aberrations and enable critical-dimension uniformity CDU during the exposure.

Multiple patterning ArF immersion lithography has been expected as the promising technology to satisfy tighter leading edge device requirements. One of the most important features of the next generation lasers will be the ability to support green operations while further improving cost of ownership and performance. Especially, the dependence on rare gases, such as Neon and Helium, is becoming a critical issue for high volume manufacturing process.

The new ArF excimer laser, GT64A has been developed to cope with the reduction of operational costs, the prevention against rare resource shortage and the improvement of device yield in multiple-patterning lithography. GT64A has advantages in efficiency and stability based on the field-proven injection-lock twin-chamber platform (GigaTwin platform). By the combination of GigaTwin platform and the advanced gas control algorithm, the consumption of rare gases such as Neon is reduced to a half. And newly designed Line Narrowing Module can realize completely Helium free operation. For the device yield improvement, spectral bandwidth stability is important to increase image contrast and contribute to the further reduction of CD variation. The new spectral bandwidth control algorithm and high response actuator has been developed to compensate the offset due to thermal change during the interval such as the period of wafer exchange operation. And REDeeM Cloud™, new monitoring system for managing light source performance and operations, is on-board and provides detailed light source information such as wavelength, energy, E95, etc.

Immersion scanners remain the critical lithography workhorses in semiconductor device manufacturing. When progressing towards the 7nm device node for logic and D18 device node for DRAM production, pattern-placement and layer-to-layer overlay requirements keep progressively scaling down and consequently require system improvements in immersion scanners. The on-product-overlay requirements are approaching levels of only a few nanometers, imposing stringent requirements on the scanner tool design in terms of reproducibility, accuracy and stability.

In this paper we report on the performance of the NXT:1980Di immersion scanner. The NXT:1980Di builds upon the NXT:1970Ci, that is widely used for 16nm, 14nm and 10nm high-volume manufacturing. We will discuss the NXT:1980Di system- and sub-system/module enhancements that drive the scanner overlay, focus and productivity performance. Overlay, imaging, focus, productivity and defectivity data will be presented for multiple tools.

To further reduce the on-product overlay system performance, alignment sensor contrast improvements as well as active reticle temperature conditioning are implemented on the NXT:1980Di. Reticle temperature conditioning will reduce reticle heating overlay and the higher contrast alignment sensor will improve alignment robustness for processed alignment targets.

Due to an increased usage of multiple patterning techniques, an increased number of immersion exposures is required. NXT:1980Di scanner design modifications raised productivity levels from 250wph to 275wph. This productivity enhancement provides lower cost of ownership (CoO) for customers using immersion technology.

The semiconductor technology roadmap suggests that multiple patterning techniques will be used at the 7nm node. The final lithography accuracy is determined by what is known as the "on-product" performance, which includes projection lens heating, illumination condition variations, product wafer related errors, and long term stability. It is evident that on product performance improvement is imperative now, and will become even more crucial in coming years. Nikon has developed the next-generation lithography system focusing on optimizing the main factors impacting on product performance. In this paper, we will introduce the details of the next-generation Nikon scanner and provide supporting performance data.

As feature size shrinks, better critical dimension uniformity (CDU) is highly demanded in aspects of device characteristics. Intra field CDU is one of main contributor in total CD variation budget. Especially systematic CD distribution in shot, bank and MAT boundary should be strongly considered to minimize repeated error to guarantee high yield even though it is not prominent in overall CDU value.

In this paper, we investigated the several factors to affect systematic CD distribution error on intra field. First of all, localized mask CD variation caused by electron-beam scattering over local region, development loading and etch loading effect directly printed in wafer. Appropriate mask fabrication suppress CD variation at boundary region. Secondly, chemical flare effect is expected to make CD gradient at boundary region. Photo acid concentration change by sub-resolution assist feature (SRAF) can reduce the CD gradient. We demonstrated SRAF size dependency in positive tone develop (PTD) and negative tone develop (NTD) case. Thirdly, out-of-field stray light (OOFSL) due to adjacent exposed field causes CD gradient at field boundary. Exposure dose reduction is expected as a solution in this case. Even though we perfectly control CDU at boundary region after mask patterning, other process issues such as etch and CMP loading effect also make worse the CD distribution at boundary region.

Through the consideration of above factors, we optimized systematic CD distribution error at boundary region before etch. Furthermore we compared several techniques to compensate post-etch systematic CD distribution.

Diffractive mask-aligner lithography allows printing sub-micrometer resolution structures by using non-contact mode. For such a purpose, binary diffraction gratings are used as masks and are designed to transmit solely the ±1st diffraction orders. The high resolution interferogram is realized by the overlapping and the interference of the propagating beams. By applying the techniques known as Self-Aligned Double Patterning (SADP), it´s possible to decrease the period of the fabricated grating (350 nm) by a factor of two, and thus reaching the 90nm structure width. As application, metallic gratings have been fabricated operating as wire grid polarizer (WGP).

In this paper we present a method to optimize the lithography process for the fabrication of interdigitated electrode arrays (IDA) for a lift-off free electrochemical biosensor. The biosensor is based on amperometric method to allow a signal amplification by redox cycling. We already demonstrated a method to fabricate IDAs with nano gaps with conventional mask aligner lithography and two subsequent deposition processes. By decreasing the distance down to the nanometer range the linewidth variation is becoming the most critical factor and can result in a short circuit of the electrodes. Therefore, the light propagation and the resist pattern of the mask aligner lithography process are simulated to optimize the lithography process. To optimize the outer finger structure assistant features (AsFe) were introduced. The AsFe allow an optimization of the intensity distribution at the electrode fingers. Hence, the periodicity is expanded and the outer structure of the IDA is practically a part of the periodic array. The better CD uniformity can be obtained by adding three assistant features which generate an equal intensity distributions for the complete finger pattern. Considering a mask optimization of the outer structures would also be feasible. However, due to the strong impact of the gap between mask and wafer at contact lithography it is not practicable. The better choice is to create the same intensity distribution for all finger structures. With the introduction of the assistant features large areas with electrode gap sizes in the sub 100 nm region are demonstrated.

In proximity lithography, interference and diffraction effects arise when printing small features because of the proximity gap. Different techniques are used in order to control and take advantage of these effects. In this paper, the focus is set on the MO Exposure Optics developed to shape the angular spectrum of the exposure light. The MO Exposure Optics contains several elements including microlens arrays that have certain symmetry and sampling. The MO Exposure Optics allows to set the angle of illumination and can be used to define spatial coherence. We study here in detail the influence of different illumination settings on optical proximity correction (OPC) structures. We apply this concept for the first time to a LED illumination. The propagation of light after an optical proximity correction structure is measured by recording aerial images over a distance of up to 60 μm behind the mask with a high resolution microscope setup.¹ As an example structure, we investigate here an optical proximity correction structure that is intended to make the edge of a line sharper. Using illumination filter plates that limit the angle of illumination and increase the coherence lead to pronounced interference effects in aerial images as expected. But special settings of the illumination allow to achieve comparable results with much larger illumination angles and higher throughput. We will show examples and analyze the results

Laser interference lithography (LIL) is a great way to produce micro and nano scale periodic structures. The principle of LIL is that two or more coherent laser beams overlap with each other and form a standing wave in the space which can be recorded by the photoresist. However, due to the principle of LIL, exposure result is very sensitive to the light source, especially in large area exposure. Regular defects occurs in large area exposure result when the laser source has multiple longitudinal mode or mode hopping. Therefore, this paper design and build up an advanced achromatic interference lithography system to solve this problem. Due to the principle of achromatic interference lithography, the exposure result is no longer relative to the wavelength of the laser source, and the pitch of the periodic structures is half of the grating pitch. As a result, achromatic interference lithography is able to eliminate the regular defects caused by the unstable laser source. But traditional achromatic interference lithography system is not very efficient due to transmission lost and only first order light is used. This paper build up an advanced achromatic interference lithography system with two reflective blazed gratings. Because of the principle of the reflective blazed grating, we can improve the efficiency of our achromatic interference lithography system. In this paper, 20 mm² of large area periodic structures with 420nm pitch and 130 nm linewidth have been successfully fabricated without any defects.

As patterns shrink to the resolution limits of up-to-date ArF immersion lithography technology, negative tone development (NTD) process has been an increasingly adopted technique to get superior imaging quality through employing bright-field (BF) masks to print the critical dark-field (DF) metal and contact layers. However, from the fundamental materials and process interaction perspectives, several key differences inherently exist between NTD process and the traditional positive tone development (PTD) system, especially the horizontal/vertical resist shrinkage and developer depletion effects, hence the traditional resist parameters developed for the typical PTD process have no longer fit well in NTD process modeling. In order to cope with the inherent differences between PTD and NTD processes accordingly get improvement on NTD modeling accuracy, several NTD models with different combinations of complementary terms were built to account for the NTD-specific resist shrinkage, developer depletion and diffusion, and wafer CD jump induced by sub threshold assistance feature (SRAF) effects. Each new complementary NTD term has its definite aim to deal with the NTD-specific phenomena. In this study, the modeling accuracy is compared among different models for the specific patterning characteristics on various feature types. Multiple complementary NTD terms were finally proposed to address all the NTD-specific behaviors simultaneously and further optimize the NTD modeling accuracy. The new algorithm of multiple complementary NTD term tested on our critical dark-field layers demonstrates consistent model accuracy improvement for both calibration and verification.

Source Mask Optimization (SMO) has played an important role in technology setup and ground rule definition since the 2x nm technology node. While improvements in SMO algorithms have produced higher quality and more consistent results, the accuracy of the overall solution is critically linked to how faithfully the entire patterning system is modeled, from mask down to substrate. Fortunately, modeling technology has continued to advance to provide greater accuracy in modeling 3D mask effects, 3D resist behavior, and resist phenomena. Specifically, the Domain Decomposition Method (DDM) approximates the 3D mask response as a superposition of edge-responses.¹ The DDM can be applied to a sectorized illumination source based on Hybrid-Hopkins Abbe approximation,² which provides an accurate and fast solution for the modeling of 3D mask effects and has been widely used in OPC modeling. The implementation of DDM in the SMO flow, however, is more challenging because the shape and intensity of the source, unlike the case in OPC modeling, is evolving along the optimization path. As a result, it gets more complicated. It is accepted that inadequate pupil sectorization results in reduced accuracy in any application, however in SMO the required uniformity and density of pupil sampling is higher than typical OPC and modeling cases. In this paper, we describe a novel method to implement DDM in the SMO flow. The source sectorization is defined by following the universal pixel sizes used in SMO. Fast algorithms are developed to enable computation of edge signals from each fine pixel of the source. In this case, each pixel has accurate information to describe its contribution to imaging and the overall objective function. A more continuous angular spectrum from 3D mask scattering is thus captured, leading to accurate modeling of 3D mask effects throughout source optimization. This method is applied on a 2x nm middle-of-line layer test case. The impact of the 3D mask model accuracy on the source profile and corresponding lithographic performance is studied in detail. Furthermore, the impact of using a compact resist model in SMO is also investigated by using the same test case.

In this paper, we present the approach and results of layer-aware source mask target optimization. In this approach, the design target is co-optimized during source mask optimization (SMO) by considering inter-layer constraints. We tested the method on a 2x nm node metal layer by using both standard and customized cost functions for source optimization. Variable targets were defined for two process window limiting critical pattern cells, with contact-to-metal and metal-tovia coverage rules taken into consideration. The results indicate that layer-aware source mask target optimization gives consistent process window improvement over conventional SMO. The optimized targets prove to be a good balance between lithography process window and post-etch inter-layer coverage margin.

Process window OPC (PWOPC) is widely used in advanced technology nodes as one of the most important resolution enhancement techniques (RET).¹ PWOPC needs to consider not only edge placement error (EPE) from nominal condition simulations, but also constraints based on process variation simulations, such as pinch and bridge related requirements based on process variation band (PVBAND). Those constraints can be challenging to meet as feature size continues to shrink in advanced nodes.

In this paper a novel matrix retargeting based PWOPC was developed to find optimal OPC solutions by solving constraints-based matrix and applying minimal retargeting as needed.² Experiment results showed enhanced process window and reasonable performance.

Controlling critical dimension (CD) of implant blocking layers during photolithography has been challenging due to reflection caused by wafer topography. Unexpected reflection which comes from wafer topography makes severe CD variation on mask patterns of implant layer. Using bottom antireflective coatings(BARCs) can reduce the topography effect, but it could also damage wafer surface during BARCs dry etching. Developable BARCs(D-BARCs) could be alternative solution for wafer topography effect. However there are some issues that should be considered in D-BARCs process such as sensitive temperature control and managing defects. There are also papers introducing model based topography aware OPC as a solution for wafer topography effect implant layer. But building topography aware OPC model is very complex and it takes too much time to build.

In this paper, we will introduce experimental results of wafer topography effect using various test patterns and propose a simple method that could effectively reduce wafer topography effect.

Triple patterning (TP) lithography becomes a feasible technology for manufacturing as the feature size further scale down to sub 14/10 nm. In TP, a layout is decomposed into three masks followed with exposures and etches/freezing processes respectively. Previous works mostly focus on layout decomposition with minimal conflicts and stitches simultaneously. However, since any existence of native conflict will result in layout re-design/modification and reperforming the time-consuming decomposition, the effective method that can be aware of native conflicts (NCs) in layout is desirable. In this paper, a bin-based library matching method is proposed for NCs detection and layout decomposition. First, a layout is divided into bins and the corresponding conflict graph in each bin is constructed. Then, we match the conflict graph in a prebuilt colored library, and as a result the NCs can be located and highlighted quickly.

Light source technological performance is key to enabling chipmaker yield and production success. Just as important is ensuring that performance is consistent over time to help maintain as high an uptime as possible on litho-cells (scanner and track combination). While it is common to see average tool uptime of over 99% based on service intervention time, we will show that there are opportunities to improve equipment availability through a multifaceted approach that can deliver favorable results and significantly improve on the actual production efficiency of equipment.

The majority of chipmakers are putting light source data generated by tools such as Cymer OnLine (COL), OnPulse Plus, and SmartPulse to good use. These data sets, combined with in-depth knowledge of the equipment, makes it possible to draw powerful conclusions that help increase both chip manufacturing consistency as well as equipment productivity. This discussion will focus on the latter, equipment availability, and how data analysis can help increase equipment availability for Cymer customers.

There are several types of opportunities for increasing equipment availability, but in general we can focus on two primary categories: 1) scheduled downtime and 2) unscheduled downtime. For equipment that is under control of a larger entity, as the laser is to the scanner, there are additional categories related to either communication errors or better synchronization of events that can maximize overall litho-cell efficiency. In this article we will focus on general availability without highlighting the specific cause of litho-cell (laser, scanner and track). The goal is to increase equipment available time with a primary focus is on opportunities to minimize errors and variabilities.

In response to significant neon supply constraints, Cymer has responded with a multi-part plan to support its customers. Cymer’s primary objective is to ensure that reliable system performance is maintained while minimizing gas consumption. Gas algorithms were optimized to ensure stable performance across all operating conditions.

The Cymer neon support plan contains four elements: 1. Gas reduction program to reduce neon by >50% while maintaining existing performance levels and availability; 2. short-term containment solutions for immediate relief. 3. qualification of additional gas suppliers; and 4. long-term recycling/reclaim opportunity. The Cymer neon reduction program has shown excellent results as demonstrated through the comparison on standard gas use versus the new >50% reduced neon performance for ArF immersion light sources. Testing included stressful conditions such as repetition rate, duty cycle and energy target changes. No performance degradation has been observed over typical gas lives.

Multiple patterning ArF immersion lithography has been expected as the promising technology to satisfy tighter leading edge device requirements. A new ArF excimer laser, GT64A has been developed to cope with the prevention against rare resource shortage and the reduction of operational costs. GT64A provides the sophisticated technologies which realize the narrow spectral bandwidth with helium free operation. A helium gas purge has usually been employed due to the low refractive index variation with temperature rises within a line narrowing module(LNM). Helium is a non-renewable resource and the world’s reserves have been running out. Nitrogen gas with an affordable price has been used as an alternative purge gas of helium on the restrictive condition of low thermal loads. However, the refractive index variation of nitrogen gas is approximately ten times more sensitive to temperature rises than that of helium, and broadens a spectral bandwidth in the high duty cycle operations. The new LNM design enables heat effect in laser shooting at optical elements and mechanical components in the vicinity of an optical path to be lower. This reduces thermal wavefront deformation of a laser beam without helium gas purge within LNM, and narrows a spectrum bandwidth without helium purge. Gigaphoton proved that the new LNM enabled E95 bandwidth without control to improve a lot with nitrogen purge.

There are growing concerns over future environmental impact and earth resource shortage throughout the world and in many industries. Our semiconductor industry is not excluded. "Green" has become an important topic as production volume become larger and more powerful.

Especially, the rare gases are widely used in semiconductor manufacturing because of its inertness and extreme chemical stability. One major component of an Excimer laser system is Neon. It is used as a buffer gas for Argon (Ar) and Krypton (Kr) gases used in deep ultraviolet (DUV) lithography laser systems. Since Neon gas accounting for more than 96% of the laser gas mixture, a fairly large amount of neon gas is consumed to run these DUV lasers. However, due to country's instability both in politics and economics in Ukraine, the main producer of neon gas today, supply reduction has become an issue and is causing increasing concern. This concern is not only based on price increases, but has escalated to the point of supply shortages in 2015. This poses a critical situation for the semiconductor industry, which represents the leading consumer of neon gas in the world. Helium is another noble gas used for Excimer laser operation. It is used as a purge gas for optical component modules to prevent from being damaged by active gases and impurities. Helium has been used in various industries, including for medical equipment, linear motor cars, and semiconductors, and is indispensable for modern life. But consumption of helium in manufacturing has been increased dramatically, and its unstable supply and price rise has been a serious issue today. In this article, recent global supply issue of rare resources, especially Neon gas and Helium gas, and its solution technology to support semiconductor industry will be discussed.

The Semiconductor Industry is making continuous progress in shrinking feature size developing technologies and process to achieve < 10 nm feature size. The required Overlay specification for successful production is in the range one nanometer or even smaller. Consequently, materials designed into metrology systems of exposure or inspection tools need to fulfill ever tighter specification on the coefficient of thermal expansion (CTE). The glass ceramic ZERODUR® is a well-established material in critical components of microlithography wafer stepper and offered with an extremely low coefficient of thermal expansion, the tightest tolerance available on market. SCHOTT is continuously improving manufacturing processes and it’s method to measure and characterize the CTE behavior of ZERODUR®. This paper is focusing on the "Advanced Dilatometer" for determination of the CTE developed at SCHOTT in the recent years and introduced into production in Q1 2015. The achievement for improving the absolute CTE measurement accuracy and the reproducibility are described in detail. Those achievements are compared to the CTE measurement accuracy reported by the Physikalische Technische Bundesanstalt (PTB), the National Metrology Institute of Germany. The CTE homogeneity is of highest importance to achieve nanometer precision on larger scales. Additionally, the paper presents data on the short scale CTE homogeneity and its improvement in the last two years. The data presented in this paper will explain the capability of ZERODUR® to enable the extreme precision required for future generation of lithography equipment and processes.

This paper, originally published on 15 March 2016, was retracted from the SPIE Digital Library on 14 December 2021 upon verification that it was a duplicate publication of the following paper:

A. Zhevlakov, E. Gavrilov, S. Kascheev, V. Kujanpaa, and T. Savinainen, “Optical attachment for transformation of output beam of excimer laser,” Proc. SPIE 7822, Laser Optics 2010, 78220C (22 March 2011); https://doi.org/10.1117/12.885210

The diagnosis and control of the polarization aberrations is one of the main concerns in a hyper numerical aperture (NA) lithography system. Waveplates are basic and indispensable optical components in the polarimetric diagnosis tools for the immersion lithography system. The retardance of a birefringent waveplate is highly sensitive to the incident angle of the light, which makes the conventional waveplate not suitable to be applied in the polarimetric diagnosis for the immersion lithography system with a hyper NA. In this paper, we propose a method for the optimal design of a wideview- angle waveplate by combining two positive waveplates made from magnesium fluoride (MgF₂) and two negative waveplates made from sapphire using the simulated annealing algorithm. Theoretical derivations and numerical simulations are performed and the results demonstrate that the maximum variation in the retardance of the optimally designed wide-view-angle waveplate is less than ± 0.35° for a wide-view-angle range of ± 20°.

The aberration inspection of Shack-Hartmann of lithographic lens has reached the nanometer inspection accuracy. Collimator as the key element of the system, the accurate positioning of itself is one important factor for the inspection accuracy. Based on the wavefront reconstruction with Zernike polynomials, in this paper, an optical alignment method for positioning adjustments of the collimator is presented. A sensitivity matrix is obtained from the equation that describes the correlation between Zernike coefficients and the multi-degree-of-freedom misalignment, and the positioning adjustments of collimator are acquired thereof. For the aberration inspection with Shack-Hartmann method, an engineering model of 193nm NA 0.75 projection lens is established in commercial simulating software (ZEMAX). For 0.5nm RMS aberration inspection accuracy, the positioning accuracy of collimator is analyzed and plotted with independent single freedom degree and mutual correlation with combined three freedom degrees. These analysis indicate the proposed method is a viable tool for aligning confocal position of collimator.

The application of accurate and predictive physical resist simulation is seen as one important use model for fast and efficient exploration of new patterning technology options, especially if fully qualified OPC models are not yet available at an early pre-production stage. The methodology of using a top-down CD-SEM metrology to extract the 3D resist profile information, such as the critical dimension (CD) at various resist heights, has to be associated with a series of presumptions which may introduce such small, but systematic CD errors. Ideally, the metrology effects should be carefully minimized during measurement process, or if possible be taken into account through proper metrology modeling. In this paper we discuss the application of a fast SEM signal emulation describing the SEM image formation. The algorithm is applied to simulated resist 3D profiles and produces emulated SEM image results for 1D and 2D patterns. It allows estimating resist simulation quality by comparing CDs which were extracted from the emulated and from the measured SEM images.

Moreover, SEM emulation is applied for resist model calibration to capture subtle error signatures through dose and defocus. Finally, it should be noted that our SEM emulation methodology is based on the approximation of physical phenomena which are taking place in real SEM image formation. This approximation allows achieving better speed performance compared to a fully physical model.

The 2x nm logic foundry node has many challenges since critical levels are pushed close to the limits of low k₁ ArF water immersion lithography. For these levels, improvements in lithographic performance can translate to decreased rework and increased yield. Source Mask Optimization (SMO) is one such route to realize these image fidelity improvements. During SMO, critical layout constructs are intensively optimized in both the mask and source domain, resulting in a solution for maximum lithographic entitlement. From the hardware side, advances in source technology have enabled free-form illumination. The approach allows highly customized illumination, enabling the practical application of SMO sources. The customized illumination sources can be adjusted for maximum versatility. In this paper, we present a study on a critical layer of an advanced foundry logic node using the latest ILT based SMO software, paired with state-of-the-art scanner hardware and intelligent illuminator. Performance of the layer's existing POR source is compared with the ideal SMO result and the installed source as realized on the intelligent illuminator of an NSR-S630D scanner. Both simulation and on-silicon measurements are used to confirm that the performance of the studied layer meets established specifications.

As leading edge lithography moves to advanced nodes, CDU requirements have relatively increased with technologies 14nm/20nm and beyond. In this paper, we want to introduce the methodology to offer an itemized CDU budget such as Intra-field, Inter-field, wafer to wafer as well as scanner contributors vs. non-scanner contributors (including detailed analysis of reticle contributors like CD, absorber thickness and SWA variation) through Top-Down CDU and Bottom-Up CDU budget breakdown and deliver sources of CD variation with measureable value so that we can estimate CDU gain from them. The test vehicle being used in this experiment is designed based on 14nm D/R basis. Measurement structures are densely located in the slit/scan direction on the reticle for the data collection plan. Hence, we can expand on this methodology to build up the tool reference fingerprint when we release new tool fleet. The final goal will be to establish a methodology for CDU budget breakdown that can be used to draw a conclusion on the root causes of the observed CDU, propose its improvement strategy and estimate the gain.

The inverse polarizing effect of Sub-Wavelength Metallic Gratings (SWMGs) is employed to improve the lithography performance by controlling the polarization. The SWMGs are intentionally created on the top surface of mask. Its polarization selectivity is deliberately designed according to the bottom mask patterns. A series of simulations and optimizations on SWMG structures were done in order to achieve better image quality. We demonstrate that the contrast of aerial image can be improved by designing the inverse polarizer on mask (iPOM) for some specific layout patterns. We also reveal that the double diffraction inevitably occurring in-between the iPOM and layout pattern may damage the image quality in most situations. This leads to narrow usage of iPOM. An alternative to overcome the double diffraction is proposed by optimizing the refractive index and thickness of layout absorber to make the polarization selection feasible without iPOM.

The line edge roughness (LER) and line width roughness (LWR) transfer in a self-aligned quadruple patterning (SAQP) process is shown for the first time. Three LER characterization methods, including conventional standard deviation method, power spectral density (PSD) method and frequency domain 3-sigma method, are used in the analysis. The wiggling is also quantitatively characterized for each SAQP step with a wiggling factor. This work will benefit both process optimization and process monitoring.

In this paper, we demonstrate a dual-wavelength diffractive beam splitter to be used in parallel laser processing. The novel optical element, which is formed in a transparent material, generates two beam arrays at different wavelengths and allows their overlap at the process points on a workpiece. Since the splitter has a stochastically designed, complex, and deep surface profile, there is limited freedom in selecting a fabrication method. We designed the splitter using a simulated annealing algorithm and fabricated it in a photoresist through maskless exposure by using a digital micromirror device. We characterized the designed splitter, thereby corroborating the proposed beam-splitting concept.

Today's design for photonics devices on silicon relies on non-Manhattan features such as curves and a wide variety of angles with minimum feature size below 100nm. Industrial manufacturing of such devices requires optimized process window with 193nm lithography. Therefore, Resolution Enhancement Techniques (RET) that are commonly used for CMOS manufacturing are required.

However, most RET algorithms are based on Manhattan fragmentation (0°, 45° and 90°) which can generate large CD dispersion on masks for photonic designs. Industrial implementation of RET solutions to photonic designs is challenging as most currently available OPC tools are CMOS-oriented. Discrepancy from design to final results induced by RET techniques can lead to lower photonic device performance.

We propose a novel sizing algorithm allowing adjustment of design edge fragments while preserving the topology of the original structures. The results of the algorithm implementation in the rule based sizing, SRAF placement and model based correction will be discussed in this paper. Corrections based on this novel algorithm were applied and characterized on real photonics devices. The obtained results demonstrate the validity of the proposed correction method integrated in Inscale software of Aselta Nanographics.

An efficient pixel-based mask optimization method via particle swarm optimization (PSO) algorithm for inverse lithography is proposed. Because of the simplicity of principles, the ease of implementation and the efficiency of convergence, PSO has been widely used in many fields. In this study, PSO is used to solve the inverse problem of mask optimization. The pixel-based mask patterns are transformed into frequency space using discrete cosine transformation and the frequency components are encoded into particles. The pattern fidelity is adopted as the fitness function to evaluate these particles. The mask optimization method is implemented by updating the velocities and positions of these particles. Simulation results show that the image fidelity has been efficiently improved after using the proposed method.