PROCEEDINGS VOLUME 9781
SPIE ADVANCED LITHOGRAPHY | 21-25 FEBRUARY 2016
Design-Process-Technology Co-optimization for Manufacturability X
Proceedings Volume 9781 is from: Logo
SPIE ADVANCED LITHOGRAPHY
21-25 February 2016
San Jose, California, United States
Front Volume: 9781
Proc. SPIE 9781, Front Matter: Volume 9781, 978101 (28 June 2016); doi: 10.1117/12.2239765
Layout Optimization and Design Restrictions
Proc. SPIE 9781, Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs, 978102 (16 March 2016); doi: 10.1117/12.2218361
Proc. SPIE 9781, Structural design, layout analysis and routing strategy for constructing IC standard cells using emerging 3D vertical MOSFETs, 978103 (16 March 2016); doi: 10.1117/12.2219267
Proc. SPIE 9781, Directed self-assembly aware restricted design rule and its impact on design ability, 978104 (16 March 2016); doi: 10.1117/12.2219216
Proc. SPIE 9781, Integrated routing and fill for self-aligned double patterning (SADP) using grid-based design, 978105 (16 March 2016); doi: 10.1117/12.2219142
Proc. SPIE 9781, Integrated layout based Monte-Carlo simulation for design arc optimization, 978106 (16 March 2016); doi: 10.1117/12.2218636
Proc. SPIE 9781, Impact of EUV patterning scenario on different design styles and their ground rules for 7nm/5nm node BEOL layers, 978107 (16 March 2016); doi: 10.1117/12.2220019
Layout Analytics
Proc. SPIE 9781, Methodology for analyzing and quantifying design style changes and complexity using topological patterns, 978108 (16 March 2016); doi: 10.1117/12.2220021
Proc. SPIE 9781, Methodology to extract, data mine and score geometric constructs from physical design layouts for analysis and applications in semiconductor manufacturing, 978109 (16 March 2016); doi: 10.1117/12.2220145
Proc. SPIE 9781, Using pattern enumeration to accelerate process development and ramp yield, 97810A (16 March 2016); doi: 10.1117/12.2219129
Proc. SPIE 9781, Optimization of self-aligned double patterning (SADP)-compliant layout designs using pattern matching for 10nm technology nodes and beyond, 97810B (16 March 2016); doi: 10.1117/12.2219358
Design and Litho Optimization: Joint Session with Conferences 9780 and 9781
Proc. SPIE 9781, Hybrid hotspot detection using regression model and lithography simulation, 97810C (22 March 2016); doi: 10.1117/12.2219318
Circuit Modeling
Proc. SPIE 9781, Variability-aware compact modeling and statistical circuit validation on SRAM test array, 97810D (16 March 2016); doi: 10.1117/12.2219428
Proc. SPIE 9781, Impacts of process variability of alternating-material self-aligned multiple patterning on SRAM circuit performance, 97810E (16 March 2016); doi: 10.1117/12.2218992
Proc. SPIE 9781, Modeling interconnect corners under double patterning misalignment, 97810F (16 March 2016); doi: 10.1117/12.2219150
Proc. SPIE 9781, Model-based CMP aware RC extraction of interconnects in 16nm designs, 97810G (16 March 2016); doi: 10.1117/12.2219118
Hotspot Detection and Removal
Proc. SPIE 9781, Automatic layout feature extraction for lithography hotspot detection based on deep neural network, 97810H (16 March 2016); doi: 10.1117/12.2217746
Proc. SPIE 9781, Pattern-based DTCO flow for early estimation of lithographic difficulty using optical image processing, 97810I (16 March 2016); doi: 10.1117/12.2219506
Proc. SPIE 9781, A random approach of test macro generation for early detection of hotspots, 97810J (16 March 2016); doi: 10.1117/12.2218806
Proc. SPIE 9781, Hotspot detection and removal flow using multi-level silicon-calibrated CMP models, 97810K (16 March 2016); doi: 10.1117/12.2219545
Proc. SPIE 9781, Migrating from older to newer technology nodes and discovering the process weak-points, 97810L (16 March 2016); doi: 10.1117/12.2219561
Multiple Patterning and Directed Self-Assembly
Proc. SPIE 9781, Triple/quadruple patterning layout decomposition via novel linear programming and iterative rounding, 97810M (16 March 2016); doi: 10.1117/12.2218628
Proc. SPIE 9781, Design strategy for integrating DSA via patterning in sub-7 nm interconnects, 97810N (16 March 2016); doi: 10.1117/12.2222041
Proc. SPIE 9781, Enablement of DSA for VIA layer with a metal SIT process flow, 97810O (16 March 2016); doi: 10.1117/12.2218808
Proc. SPIE 9781, Layout decomposition and synthesis for a modular technology to solve the edge-placement challenges by combining selective etching, direct stitching, and alternating-material self-aligned multiple patterning processes, 97810P (16 March 2016); doi: 10.1117/12.2219082
Proc. SPIE 9781, Metal stack optimization for low-power and high-density for N7-N5, 97810Q (28 March 2016); doi: 10.1117/12.2238928
Design Interaction with Metrology: Joint Session with Conferences 9778 and 9781
Proc. SPIE 9781, The new analysis method of PWQ in the DRAM pattern, 97810R (16 March 2016); doi: 10.1117/12.2218414
Process and Yield Modeling
Proc. SPIE 9781, Verification and application of multi-source focus quantification, 97810S (16 March 2016); doi: 10.1117/12.2219143
Proc. SPIE 9781, A comparative study on the yield performance of via landing and direct stitching processes for 2D pattern connection, 97810T (16 March 2016); doi: 10.1117/12.2219336
Proc. SPIE 9781, Estimate design sensitivity to process variation for the 14nm node, 97810U (16 March 2016); doi: 10.1117/12.2219067
Interactive Poster Session
Proc. SPIE 9781, Interlayer design verification methodology using contour image, 97810V (16 March 2016); doi: 10.1117/12.2218477
Proc. SPIE 9781, Design space exploration for early identification of yield limiting patterns, 97810W (16 March 2016); doi: 10.1117/12.2218540
Proc. SPIE 9781, Design technology co-optimization for 14/10nm metal1 double patterning layer, 97810X (16 March 2016); doi: 10.1117/12.2218711
Proc. SPIE 9781, An integrated design-to-manufacturing flow for SADP, 97810Y (16 March 2016); doi: 10.1117/12.2218828
Proc. SPIE 9781, Using pattern analysis methods to do fast detection of manufacturing pattern failures, 97810Z (16 March 2016); doi: 10.1117/12.2219000
Proc. SPIE 9781, Electron-beam lithography with character projection exposure for throughput enhancement with line-edge quality optimization, 978110 (16 March 2016); doi: 10.1117/12.2219021
Proc. SPIE 9781, Rapid recipe formulation for plasma etching of new materials, 978111 (16 March 2016); doi: 10.1117/12.2219171
Proc. SPIE 9781, Expanding the printable design space for lithography processes utilizing a cut mask, 978112 (23 March 2016); doi: 10.1117/12.2219201
Proc. SPIE 9781, Characterization of shallow trench isolation CMP process and its application, 978113 (16 March 2016); doi: 10.1117/12.2219912
Proc. SPIE 9781, Advanced DFM application for automated bit-line pattern dummy, 978114 (16 March 2016); doi: 10.1117/12.2220276
Proc. SPIE 9781, Wafer hotspot prevention using etch aware OPC correction, 978115 (16 March 2016); doi: 10.1117/12.2220778
Proc. SPIE 9781, Building block style recipes for productivity improvement in OPC, RET and ILT flows, 978116 (16 March 2016); doi: 10.1117/12.2222591
Proc. SPIE 9781, Hybrid pattern matching based SRAF placement, 978117 (16 March 2016); doi: 10.1117/12.2225830
Proc. SPIE 9781, LELE CD bias offset monitor through OVL measurement, 978118 (16 March 2016); doi: 10.1117/12.2219509
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