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8 December 1978 A Proposed Design For A Real-Time Signal Processor
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A proposed architecture for real-time signal processing is discussed. The architecture consists of 2n microcomputers connected through a switching network that makes the entire array into what we call the "indirect binary n-cube array." By a microcomputer we mean a microprocessor together with memory, some of which can be read-only or write-occasionally. The microcomputers are operated in lockstep under broadcast macroinstructions from a central controller which can also be a microcomputer. The macroinstructions are locally interpreted in a programmable way as a sequence of microinstructions. The central controller also manages the switching array, as well as handling I/O to and from the array. It is shown that this design can make full use of the 2n-fold parallelism for most signal processing algorithms including, for example, the radix-2 FFT in one or two dimensions, windowing, doppler filtering, and the like. Furthermore, the design is such that the array, and hence the available degree of parallelism, can be halved or doubled without requiring redesign; it can therefore be adapted to changing requirements.
© (1978) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Marshall Pease "A Proposed Design For A Real-Time Signal Processor", Proc. SPIE 0154, Real-Time Signal Processing I, (8 December 1978);

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