SIGNAL PROCESSING WITH BIT-SERIAL WORD-PARALLEL ARCHITECTURES

Noble R. Powell; John M. Irwin

doi:10.1117/12.938243

8 December 1978 SIGNAL PROCESSING WITH BIT-SERIAL WORD-PARALLEL ARCHITECTURES

Noble R. Powell, John M. Irwin

Proceedings Volume 0154, Real-Time Signal Processing I; (1978) https://doi.org/10.1117/12.938243
Event: 22nd Annual Technical Symposium, 1978, San Diego, United States

Abstract

The incremental cost per unit of performance of a variety of flexible system functions has been sharply reduced through the application of a high degree of functional parallelism with serialized arithmetic. (Functional parallelism as used here is the parallel use of an array of high density, low cost, lower performance devices to obtain a high performance function.) System functions, such as fast Fourier transformers, digital filters, graphics function generators, and matrix computational arrays have all been reduced to a form which is highly channelized in this manner. Such computationally intensive digital signal processors employing novel computational means are shown to promise a reduction in size, weight, and power by an order of magnitude over conventional techniques. Several examples of modular functional processors are presented for which the algorithmic formulation, architectural configuration, and prototype implementation are described.

Citation Download Citation

Noble R. Powell and John M. Irwin "SIGNAL PROCESSING WITH BIT-SERIAL WORD-PARALLEL ARCHITECTURES", Proc. SPIE 0154, Real-Time Signal Processing I, (8 December 1978); https://doi.org/10.1117/12.938243

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