30 July 1982 Problem Adaptation To Systolic Arrays
Author Affiliations +
The systolic array architecture is known to make highly efficient use of hardware in evaluating certain matrix products provided that the matrices are banded strongly. However, this high efficiency can be degraded significantly if the matrices to be processed do not possess the narrow bandwidth feature, but assume a more general structure. This paper introduces and evaluates two techniques which in some instances can enhance systolic array efficiency. The approach effectively reduces to adapting problem structure so that it more naturally fits the systolic array architecture. Potential benefits from this approach are quantified and presented in graphical form.
© (1982) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
R. W. Priester, R. W. Priester, H. J. Whitehouse, H. J. Whitehouse, K. Bromley, K. Bromley, J. B. Clary, J. B. Clary, } "Problem Adaptation To Systolic Arrays", Proc. SPIE 0298, Real-Time Signal Processing IV, (30 July 1982); doi: 10.1117/12.932509; https://doi.org/10.1117/12.932509


A Review Of Signal Processing With Systolic Arrays
Proceedings of SPIE (November 27 1983)
Implementation Of An SVD Processor Using Redundant CORDIC
Proceedings of SPIE (February 22 1988)
Fault Tolerance Techniques For Systolic Arrays
Proceedings of SPIE (November 24 1987)
Implementation Of Cellular Arrays
Proceedings of SPIE (July 29 1982)
Algorithmic Engineering-An Emerging Discipline
Proceedings of SPIE (November 13 1989)

Back to Top