The systolic array architecture is known to make highly efficient use of hardware in evaluating certain matrix products provided that the matrices are banded strongly. However, this high efficiency can be degraded significantly if the matrices to be processed do not possess the narrow bandwidth feature, but assume a more general structure. This paper introduces and evaluates two techniques which in some instances can enhance systolic array efficiency. The approach effectively reduces to adapting problem structure so that it more naturally fits the systolic array architecture. Potential benefits from this approach are quantified and presented in graphical form.