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14 January 1982 Modular Multiprocessor Picture Computer Architecture For Distributed Picture Information Systems
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Abstract
Even in its most primitive mode of operation - acquisition, filing, and retrieval - picture information systems will need high-speed picture processors. The tens of megabits of each picture have to be transferred, buffered, and coded in a user-friendly time of only a few seconds. The required throughput rate will be about 10 Mpel/s, which is far beyond the capability of conventional computer hardware. In order to avoid a proliferation of special purpose hardware designs, we have developed a picture processor concept, which is based on a modular architecture. A register of full (or multiple) picture size is connected via a high-speed bus structure to one or several processing elements. Each processing element manages its own data stream in order to synchronize data transfer and processing. Processing elements may be hardwired (fast but specialized), or programmable on different levels. Several modes of multiprocessing are possible (SIMD, pipeline, etc.). Any local sub-system of a distributed picture information system may be assembled from a number of standardized modules. Local sub-systems may easily be optimized with respect to the most frequently used operations, but will still be flexible to allow any extension towards more sophisticated processing.
© (1982) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Th . Wendler, D. Bohring, D. Meyer-Ebrecht, J. Schmidt, and H. Svensson "Modular Multiprocessor Picture Computer Architecture For Distributed Picture Information Systems", Proc. SPIE 0318, 1st Intl Conf and Workshop on Picture Archiving and Communication Systems, (14 January 1982); https://doi.org/10.1117/12.967634
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