The acrylate family of resists have been the most popular choice of positive resists for advanced lithography. Over the last decade, polymethylmethacrylate (PMMA) and derivatives of the general formula continue to show improved performance

Poly(methly a-chloracrylate) (PMCA) is one of the vinyl polymers which is highly sensitive to high energy radiation. The G, value (defined as number of chain scission events per 100 ev of energy absorbed) of PMCA is 6.0 which is significantly higher than 1.6 of PMMA - the current standard e-beam resist. Used as a positive electron resist, the sensitivity of PMCA is considerably better than PMMA but less than one would expect from its high Gs' Such behavior can be attributed to: (a) the occurrence of non-negligible concurrent crosslinking in PMCA and (b) the poor solubility of PMCA. In the past, we have reported the synthesis, characterization and e-beam exposure results for the copolymers of MCA and several methacrylates, including methyl methacrylate (MMA), cyclohexyl methacrylate and n-hexyl methacrylate. In the present paper, the results of our recent studies for the copolymers of MCA and n-butyl methacrylate (BMA), of MCA and methacrylic acid (MAA) and the new results for the copolymers of MCA and MMA are presented. The optimization of copolymer composition and molecular weight, and the selection of developers based on solubility parameter concept are discussed in the paper. It has been found that both MCA/BMA and MCA/MMA copolymer resists possess submicron resolution and are significantly more sensitive than PMMA.

We have found that a family of ionic polymers, various oolyvinylnyridinium salts, can act as good electron beam resists. Exoosure of these polymers to a 20 XV electron beam resulted in sensitivities ranging up to 5 μcoulomb/cm². A number of materials definately exhibited submicron caoabilities. Furthermore, the highly aromatic nature of the nolymer provided the outstanding plasma etch resistance. In order to elucidate the chemical structural variables which influence the resist Performance, a series of polymers has been synthesized by varying molecular weights, molecular weight distributions, counterions, alkyl groups, degrees of Quaternization, etc. We subsequently studied the resist behavior of these materials. Several postulated mechanisms will be discussed to explain the resist action.

The plasma resist image stabilization technique (PRIST) can effectively stabilize the developed resist image in the production of integrated circuits6 This fluorocarbon plasma treatment allows the resist to be baked in excess of 210 C without measurable change in dimensions. The typical PRIST treatment is exercised in a CF4 plasma at a low RF power (25 W) for a short time (30 sec). This low power and short time combination could cause problems at times, especially when the PRIST is exercised in an inductively coupled barrel reactor. These problems are attributed to the plasma instability due to the system design. Most plasma systems are not designed for such low power and short time operation. We can minimize these problems and improve the process reliability by operating the reactor at a power level for which the system was designed. This paper reports the results of the PRIST experiments using a mixture of CF₄ diluted in nitrogen, argon, or helium. The results indicate that one can reduce the concentration of CF4 to less than 1% and still obtain excellent resist pattern after the post-baking. This reduction in CF₄ concentration permits increasing both RF power and treatment duration without increasing the nitride etch rate. In addition to improving the process reliability, this increase in time and power allows one to select a series of power and time combinations to achieve the desired results.

A hybrid lithographic process, utilizing both e-beam and conventional optical exposure techniques within the same device level, has been developed using a commercially available positive photoresist. Following E-beam exposure of the < 3.0 micron geometries and optical exposure of the larger sized patterns, both sets of images are developed in a single development. Using this process, working CMOS devices have been fabricated with polysilicon gate lengths of 0.75 and 0.50 micron. The effect of E-beam dosage upon the submicron gate critical dimensions has been determined as well as other processing characteristics.

Multilevel resist systems based on Ge-Se films make possible the use of optical projection printers for printing 0.5-1.0μm features. The four multilevel resist systems considered employ either a photosensitive or a photopassive polymer layer for planarization. In bilevel schemes the surface of the Ge-Se film is reacted in a Ag(CN)i- containing solution to form a A_g2Se imaging layer. No reacted Ge-Se is used as a sacrificial layer in trilevel schemes. Ge-Se films are resistant to attack by oxygen plasma and therefore make good masks for pattern transfer by dry (reactive ion) etching, to a thick underlying photopassive polymer layer. Because of their high absorbance (a 10⁵cm-1) in the ultraviolet and violet, Ge-Se patterns can also be used as exposure masks for transferring images to a thick underlying photosensitive polymer layer. The latter is "flood" exposed through the Ge-Se mask and wet developed. Both dry and wet processes provide steep wall-profile patterns in the polymer layer. The dry process provides superior feature size control while the wet process offers reduced processing cost. The exceptional lithographic performance exhibited by Ge-Se resist systems is attributed to a unique edge-sharpening effect; diffraction is compensated for by lateral silver diffusion in the Ag2Se layer. Patterns having 0.6μm lines and spaces are obtained over lcmXlcm fields with a defocus tolerance of 2.5μm using a standard Zeiss 10:1 reduction lens (N.A.=0.28, λ=436nm). Results indicate that optical lithography can practically print features in the size regime previously reserved for a-beam or x-ray based lithographic technologies.

Quartz has an extremely low thermal expansion and is fully transparent down to wavelengths below 200 nm. These properties allow users of quartz substrate masks to push optical lithography to its limits.

Multi-level resist technology is rapidly emerging as a technique capable of significantly improving processes needed to achieve desired yields on VLSI products. For the multi-level resist technology to be successful, production-rated Deep Ultraviolet (DUV) exposure systems will be required.

Wafer imaging technology has changed significantly in the past few years, responding to the demands of LSI and VLSI circuitry. The powerful driving force of economics indicates that the LSI trend will continue with reduced line widths and greater complexity to achieve a higher level of functions in reduced area. Even with signigicant cost increases due to advanced equipment and zero defect mask or wafer fabrication, increased integration is cost effective and progression toward sub-micron design rules is expected to continue. 1 The major question is how sub-micron technology will be implemented into the production environment.

The use of multilevel resist processing techniques for fine line resolution applications has been reported. These techniques commonly require coating the wafer surface with two or more materials (photopolymer, polymer, and/or an inorganic) prior to alignment and imaging of the desired circuit pattern. By a combination of one or more such materials, the relatively rugged surface topography of the the wafer can be planarized to provide an optimally flat surface upon which a thin photoresist can then be applied. This thin resist then allows imaging of very fine linewidths. Subsequent processing (re-exposure, chemical and/or dry etching) of the multilevel materials and the wafer material transfers the desired fine line image to the wafer. This paper treats the practice of three multilevel resist processing methods in a wafer fabrication manufacturing environment. Specifically, the three multilevel resist processing techniques investigated are a dual level process, and two triple level processes using inorganic materials. The issues of material flow, line balance, required equipment, equipment capability and process control are treated in contrast to the common practice of single level resist processing. The resultant implications for work space layouts, net throughput, incurred manufacturing costs and operational complexity are addressed. Finally, the use of multilevel resist processing methods for critical device layers are examined in context of these factors.

This paper examines the impact of submicron MOS integrated circuit technology on submicron lithography, and contrasts the lithography picture today with that for submicron features. A considerably larger number of factors must be dealt with rigorously because they either do not scale with decreasing dimensions or they do not lend themselves easily to more rigid control so that it has become disproportionately difficult to reduce their effect. In addition to the lithography issues, other serious device technology limitations arise at submicron dimensions. These have to do with device isolation, gate insulation, parasitic resistance and capacitance, interconnectivity, particle-induced upset, and hot electron effects. These issues must also be successfully resolved if submicron dimensions are to be successfully exploited in submicron integrated circuits.

The two most serious problems in electron beam lithography are proximity effects and slow throughput. The former arises from the penetration of the electrons which, at conventional electron energies, can greatly exceed the size of the exposure element. Thus much of the exposing electron's energy is wasted. The use of electrons whose energy is much lower results in a much more compact area of exposure and should result in improved linewidth control and in more efficient use of the exposing power.

Electron Beam techniques, which have been applied for VLSI testing, are also useful for contactless testing of packaging modules. A test system has been developed to detect electrical opens and shorts in multilayer network wiring using specimens of 100 x 100 x 6mm in size. Various physical effects including charging, discharging, secondary electron emission and others allow a complete test to be performed. The contrast mechanism of the detected signal is based on the secondary electron yield vs. the beam potential and will be discussed in detail. Other signal mechanisms were also applied. By coordinating a pulsed electron beam in a vector mode to predetermined network terminals, computer controlled experiments were carried out. Results on the present status of this new testing approach will be presented.

The total sales dollars of semiconductors over the past six years have grown roughly at the rate of 25% per year in spite of the fact that the price of some of the individual components has decreased dramatically. This has resulted in a significant reduction in the cost per function. As this occurs, new markets open up creating additional demands.

Shaped E-Beam systems have superior writing speed for a given resolution requirement by virtue of their ability to expose numerous pattern elements in parallel. The added optic elements and circuitry for shaping makes the systems somewhat more complex than gaussian spot systems however, this is compensated by the lower circuit operating speeds and greater flexibility.

Advances in X-ray lithography technology are occurring at a promising rate. Impressive progress has been made in the development of high-intensity sources, mask membrane and patterning technology, precision mask-to-wafer alignment, and faster, high-resolution X-ray resists. The concept of using this inherently low defect lithographic technique for manufacturing submicron integrated circuits by 1985 and beyond, is realistic. Current X-ray Lithographic research systems replicate integrated circuit patterns on a full wafer with a single exposure, but step-and-repeat exposure systems are being developed for more advanced submicron applications. Both system types are discussed, and performance trade analyses are presented to show the relative merits of each approach.

X-ray lithography is composed of three elements, the alignment machine with an X-ray source, X-ray photomasks, and X-ray resist. This paper describes the processes used to manufacture boron-nitride X-ray masks and some of the results using those masks.

A full field X-ray exposure system has been developed and utilized in the fabrication of 1pm high performance NMOS logic circuits of various complexities from simple ring oscillators to large-scale custom devices. The exposure system is based on a 4 kW stationary palladium source emitting the 4.37Å L_α; line from a 3mm effective spot diameter. A special shadow mask consisting of 0.6pm gold features on a 6μm boron nitride membrane is used to transfer features into a chlorine based X-ray resist sensitive to the 4.37Å radiation. Pattern transfer to the silicon surface is faithfully reproduced through the use of a tri-level resist structure and anisotropic reactive sputter etching. Alignment of various levels is accomplished optically through the use of a bifocal, split field microscope at high magnification and the use of dark field edge sensing. Linewidth control and registration data are presented for various NMOS circuit designs fabricated in the 1pm dimensional region and some circuit performance characterization is reviewed.

Recent advances in x-ray lithography show that accurate, low defect replication of submicron features is becoming a reality. However, before x-ray lithography can be implemented in production several difficult issues must be resolved. In particular, x-ray masks must be fabricated on thin membranes with low defect density and high dimensional stability. The Intel Magnetics one megabit bubble memory is an ideal initial evaluation device because of the high resolution required (1.2 μm minimum feature size) together with its defect and alignment tolerance. Data is presented on one megabit bubble memories fabricated with the trilevel resist scheme using the commercially available resist Sel-N, Type A (exposure time is typically 2 minutes with the Perkin-Elmer 10kW tungsten x-ray exposure system). Distortion and defect data is presented showing our learning experience in fabricating x-ray masks with MEBES. Masks with sufficient stability to start LSI silicon device evaluation have been available for more than a year, masks with sufficiently low defect density to start evaluation of such devices are projected to be available in 1982. Radiation sensitive LSI devices have been exposed to lithographic levels of x-ray flux while undergoing otherwise conventional fabrication. Test data showing no performance degradation in these devices is reviewed.

Zone plates are patterned areas with imaging properties. When printed on masks and wafers and suitably illuminated, they form high contrast images which are useful for alignment in microlithography. As with holograms, defects in the pattern arising from variations in processing and linewidth control and poor edge definition degrade the images only marginally. This paper describes the use of zone plates for automatic alignment in X-ray proximity printing. The best signal to noise ratios (important in automatic alignment) are obtained by using the zone plates to focus laser beams to nearly diffraction limited point sources. With zone plates approximately 100 microns in diameter and 300 microns focal length, we have obtained signal to noise ratios greater than 100 to 1 and position accuracies better than ±0.1 micron. In addition our geometry is chosen so that magnification errors in the mask or wafer up to ~1 micron are automatically compensated. A microprocessor based system is described which performs the alignment automatically.

Presently there are several approaches to achieving a high throughput, production worthy X-ray lithography system. One approach utilizes a conventional X-ray source with fast X-ray resist materials to expose a large diameter wafer (typically 3" to 4" in one step). Another approach also utilizes a conventional X-ray source (or perhaps a plasma X-ray source) and fast X-ray resist materials to expose in a step and repeat fashion a large diameter wafer (e.g., ≤5"). A third approach utilizes a storage ring source of X-ray radiation in combination with conventional resist materials (i.e., AZ, PMMA, etc.) to expose large diameter wafers in a step and repeat fashion. In particular, single step exposure systems are limited to small diameter wafers due to registration errors which are ameliorated in step and repeat systems. Furthermore, the complex multilevel resist processing necessary to obtain high throughput in the first two approaches is unattractive to some manufacturers. However, it may be one economic way of obtaining relatively high throughput for some applications that require a small volume of devices with ≤1,μm features. For high volume manufacturers with well established production lines using conventional resist processing, a multiple port storage ring system offers economical and performance advantages relative to other exposure systems (i.e., electron beam) for VLSI manufacturing. The important parameters of each fo the above approaches will be described in this talk.

The Gas Puff Z-Pinch (GPZP) plasma X-ray source has a number of demonstrated advantages over conventional X-ray sources as applied to high throughput X-ray microlithography. The Physics International Company (PI) is presently constructing a GPZP X-ray source that has been designed for application to the microlithography industry.

A broad range of materials and processing techniques amenable to producing resist systems for ion beam lithography are discussed. The effect of random fluctuations in exposure dose on feature size for a gaussian beam of constant shape is calculated. The results of Monte Carlo simulations of exposures of PMMA on silicon by 50 KeV H₂+, 100 KeV and and 150 KeV Li⁺ ions are presented and it is shown that feature resolution is fundamentally limited by the physical processes through which energy is deposited.

The characteristics of the ion source determine the writing soeed and resolution that can be realized in direct writing ion beam lithography with focussed ion orobes. We have developed an H₂+ ion source with very high brightness and low energy snread.1 Two ion beam lithography systems based on this source are being develoned. CAD has been used to design two ion optical-deflector systems to focus this source to high resolution, high current density Probes. The desicn narameters are calculated to produce ion probes 10 to 50 nm in diameter with current densities 100 amn/cm2. The systems will be use 1. to investigate and a' my ion beam lithogranhy: ion-resist interactions, resist eNnosure and develonment characteristics, resolution limits, ion beam structuring of devices, etc.

We describe the operation and functions of a scanning ion microscope. This has been shown capable of detecting ion-channelling phenomena in crystalline materials through the observation of crystallographic contrast in images obtained with the secondary electron and secondary ion signal. The instrument also provides on-line quantitative information on surface amorphization and on channelling effects in direct ion beam writing.

Silver-sensitized obliquely deposited germanium selenide films have been shown to exhibit enhanced lithographic sensitivities. Rutherford backscattering (RBS) measurements of silver diffusion profiles indicate absence of any enhanced silver diffusion in the obliquely deposited films during the exposure process. From dissolution rate measurements and a quantitative measure of the silver left on the film at various stages, we conclude that the enhanced silver uptake in the oblique films during the sensitization process and the specific way the silver coats the columnar structure of the obliquely deposited films cause the sensitivity enhancement.

An essential step in the evaluation of masked ion beam lithography (MIBL) as a practical technology for submicrometer pattern replication has been taken in the fabrication of functional NMOS devices using MIBL exposures on all levels. In MIBL, a collimated beam of protons is directed through a patterned mask to expose a resist-covered wafer in proximity to the mask. Employing silicon channeling masks with appropriate gold absorber patterns for each level of a four-mask level NMOS process, exposures of high resolution resists were performed and patterns transferred with standard etching processes. We present details on the NMOS test chip vehicle, the resist and processing technology development, and the measured device characteristics.