30 June 1982 Intralevel Hybrid Resist Process With Submicron Capability
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Abstract
A hybrid lithographic process, utilizing both e-beam and conventional optical exposure techniques within the same device level, has been developed using a commercially available positive photoresist. Following E-beam exposure of the < 3.0 micron geometries and optical exposure of the larger sized patterns, both sets of images are developed in a single development. Using this process, working CMOS devices have been fabricated with polysilicon gate lengths of 0.75 and 0.50 micron. The effect of E-beam dosage upon the submicron gate critical dimensions has been determined as well as other processing characteristics.
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J. N. Helbert, J. N. Helbert, P. A. Seese, P. A. Seese, A. J. Gonzales, A. J. Gonzales, C. C. Walker, C. C. Walker, } "Intralevel Hybrid Resist Process With Submicron Capability", Proc. SPIE 0333, Submicron Lithography I, (30 June 1982); doi: 10.1117/12.933408; https://doi.org/10.1117/12.933408
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