The use of multilevel resist processing techniques for fine line resolution applications has been reported. These techniques commonly require coating the wafer surface with two or more materials (photopolymer, polymer, and/or an inorganic) prior to alignment and imaging of the desired circuit pattern. By a combination of one or more such materials, the relatively rugged surface topography of the the wafer can be planarized to provide an optimally flat surface upon which a thin photoresist can then be applied. This thin resist then allows imaging of very fine linewidths. Subsequent processing (re-exposure, chemical and/or dry etching) of the multilevel materials and the wafer material transfers the desired fine line image to the wafer. This paper treats the practice of three multilevel resist processing methods in a wafer fabrication manufacturing environment. Specifically, the three multilevel resist processing techniques investigated are a dual level process, and two triple level processes using inorganic materials. The issues of material flow, line balance, required equipment, equipment capability and process control are treated in contrast to the common practice of single level resist processing. The resultant implications for work space layouts, net throughput, incurred manufacturing costs and operational complexity are addressed. Finally, the use of multilevel resist processing methods for critical device layers are examined in context of these factors.