28 December 1982 Performance Analysis Of Systolic Array Architectures
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Proceedings Volume 0341, Real-Time Signal Processing V; (1982) https://doi.org/10.1117/12.933722
Event: 1982 Technical Symposium East, 1982, Arlington, United States
Abstract
In this paper we briefly describe the systolic array architecture. We discuss performance issues that arise in the evaluation of systolic array architectures. We review the fundamental concepts of Petri nets and consider their suitability as a tool for the modeling and analysis of systolic array architectures. We review known results concerning the use of timed decision-free Petri nets for performance evaluation of computing systems. We propose a new class of Petri nets (called coherent safety nets) that appear to be useful for performance evaluation of pipelined signal processing architectures. These techniques are applied to systolic array architectures.
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J. A. Bannister, J. A. Bannister, J. B. Clary, J. B. Clary, "Performance Analysis Of Systolic Array Architectures", Proc. SPIE 0341, Real-Time Signal Processing V, (28 December 1982); doi: 10.1117/12.933722; https://doi.org/10.1117/12.933722
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