Electrical Test Methods For Evaluating Lithographic Processes And Equipment

Dwight Yen

doi:10.1117/12.933682

15 October 1982 Electrical Test Methods For Evaluating Lithographic Processes And Equipment

Dwight Yen

Proceedings Volume 0342, Integrated Circuit Metrology I; (1982) https://doi.org/10.1117/12.933682
Event: 1982 Technical Symposium East, 1982, Arlington, United States

Abstract

A test structure is a microelectronic device that is fabricated by the same process used to fabricate integrated circuits (ICs) and can be tested electrically to determine important process parameters. Test structures can be used to evaluate semiconductor materials, evaluate and control process uniformity, measure device and circuit parameters, obtain input parameters for circuit simulation programs, and determine the performance of processing equipment. This paper reviews previous work at NBS on the design, measurement, and application of two types of test structures that have been used for evaluating lithographic processes and lithographic equipment performance. First, the cross-bridge sheet-resistor test structure is described. Test results from electrical measurements on this structure can be used to determine the electrical linewidth of a conducting layer. The use of test chips containing arrays of identical cross bridges for determining the uniformity of a lithographic process will be described. Analysis of test results from these arrays has been used to identify and separate the contribution to linewidth nonuniformities introduced by individual equipment and processes. The precision to which linewidth can be determined using this structure is discussed. Also, an electrical alignment test structure for determining the misalignment between two photomask steps is described and an example of its use presented. Finally, an automated dc parametric test system used for measuring these structures is described.

Citation Download Citation

Dwight Yen "Electrical Test Methods For Evaluating Lithographic Processes And Equipment", Proc. SPIE 0342, Integrated Circuit Metrology I, (15 October 1982); https://doi.org/10.1117/12.933682

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