15 October 1982 Temperature and Chemical Vapor Deposition (CVD) film effects on wafer flatness
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Proceedings Volume 0342, Integrated Circuit Metrology I; (1982) https://doi.org/10.1117/12.933684
Event: 1982 Technical Symposium East, 1982, Arlington, United States
Abstract
The dependency of wafer flatness on high temperature and Chemical Vapor Deposition (CVD) processes has been quantified for a 400 gate array bipolar process. Experimental data is presented which describes wafer flatness variations at six critical front-end process steps.
© (1982) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Peter Gise, "Temperature and Chemical Vapor Deposition (CVD) film effects on wafer flatness", Proc. SPIE 0342, Integrated Circuit Metrology I, (15 October 1982); doi: 10.1117/12.933684; https://doi.org/10.1117/12.933684
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