The dependency of wafer flatness on high temperature and Chemical Vapor Deposition (CVD) processes has been quantified for a 400 gate array bipolar process. Experimental data is presented which describes wafer flatness variations at six critical front-end process steps.
Peter Gise, Peter Gise,
"Temperature and Chemical Vapor Deposition (CVD) film effects on wafer flatness", Proc. SPIE 0342, Integrated Circuit Metrology I, (15 October 1982); doi: 10.1117/12.933684; https://doi.org/10.1117/12.933684