Image parallelism implies a SIMD-architecture where a two-dimensional array of processors and memory modules are controlled by a central master control unit. It is emphasized that effective access of artribrarily sized neighborhoods (which is everso common in image processors) are distributed over the image plane. The access and interconnection problem for such an architecture is shown to have several possible solutions with different trade-offs. No existing design presents good solutions of the neighborhood access problem. It is shown that a proper design in this respect results in a 13-fold increase in speed compared to what has recently been reported for the MPP.