15 April 1983 Architectures For A Sequential Optical Logic Processor
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Proceedings Volume 0422, 10th Intl Optical Computing Conf; (1983) https://doi.org/10.1117/12.936117
Event: 10th International Optical Computing Conference, 1983, Cambridge, United States
Abstract
A general technique is described for implementing sequential logic circuits optically. The system consists of a nonlinear transducer which provides a two-dimensional array of gates and one or more computer generated holograms (CGHs) to interconnect the gates. The limitations on the number of gates which can be implemented in an optical system is affected by the interconnection method. We describe three interconnection methods and their respective limitations. One method, which is a hybrid of space-variant and space-invariant CGH elements, provides high gate densities and high gate-utilization rates.
© (1983) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
P. Chavel, R. Forchheimer, B. K. Jenkins, A. A . Sawchuk, T. C. Strand, "Architectures For A Sequential Optical Logic Processor", Proc. SPIE 0422, 10th Intl Optical Computing Conf, (15 April 1983); doi: 10.1117/12.936117; https://doi.org/10.1117/12.936117
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