The Massively Parallel Processor (MPP) was developed to support ultra high-speed ground based image processing. The architecture comprises an array unit (ARU) which processes arrays of data; an array control unit (ACU) which controls the operation of the ARU and performs scalar arithmetic; front-end computers which control the flow of data; and a unique staging memory (SM) which buffers and permutes data. The ARU contains a 128 by 128 array of bit-serial processing elements (PE's). Two-by-four subarrays of PE's are packaged in a custom VLSI HCMOS chip. The staging memory is a large multidimensional-access memory whose primary purpose is to perform a "corner-turning" operation which converts data stored in conventional format to the bit plane format required for ARU processing.
Paul A. Gilmore,
"The Massively Parallel Processor (MPP): A Large Scale SIMD Processor", Proc. SPIE 0431, Real-Time Signal Processing VI, (28 November 1983); doi: 10.1117/12.936455; https://doi.org/10.1117/12.936455