28 November 1983 The Relationship Between Word And Bit Level Systolic Arrays As Applied To Matrix X Matrix Multiplication
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Abstract
The mapping of matrix x matrix multiplication on to both word and bit level systolic arrays has been investigated. It has been found that well defined word and bit level data flow constraints must be satisified within such circuits. An efficient and highly regular bit level array has been generated by exploiting the basic compatibilities in data flow symmetries at each level of the problem. A detailed description of the circuit which emerges is given and some details relating to its practical implementation are discussed.
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J. V. McCanny, J. V. McCanny, K. W. Wood, K. W. Wood, J. G. McWhirter, J. G. McWhirter, C. J. Oliver, C. J. Oliver, } "The Relationship Between Word And Bit Level Systolic Arrays As Applied To Matrix X Matrix Multiplication", Proc. SPIE 0431, Real-Time Signal Processing VI, (28 November 1983); doi: 10.1117/12.936449; https://doi.org/10.1117/12.936449
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