28 November 1983 Time Integrating Digital Correlator
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Abstract
This paper introduces "Interlaced Counter Propagating (ICP) Systolic Array", a new architecture for high speed systolic digital correlator operation. The interlaced arrangement of Multiply/Accumulate Units (MAUs) allow the processor to achieve 100% efficiency in MAU usage without need for complicated clocking scheme. It also shows a pipelined multiply and accumulate hardware combined with ICP architecture which allows the throughput to exceed the one with an array of conventional MAUs.
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Poohsan N. Tamura, Paul R. Haugen, B. Keith Betz, "Time Integrating Digital Correlator", Proc. SPIE 0431, Real-Time Signal Processing VI, (28 November 1983); doi: 10.1117/12.936450; https://doi.org/10.1117/12.936450
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