29 June 1984 Wafer Alignment Performance Through An MOS Process
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The sources of errors arising in the implementation of a Censor SRA100 wafer stepper in a CMOS process are analysed with reference to a specially designed standard alignment mark. Results confirm that the registration performance of the machine is in the range 0.2 to 0.4μm and indicate critical areas for attention to attain a registration consistently below 0.20μm. The paper is divided into two main sections: metrology and process experience.
© (1984) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
A Marsh, A Marsh, } "Wafer Alignment Performance Through An MOS Process", Proc. SPIE 0470, Optical Microlithography III: Technology for the Next Decade, (29 June 1984); doi: 10.1117/12.941898; https://doi.org/10.1117/12.941898

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