Out of all possible multiprocessor interconnection schemes, the time-sleazed bus ias some advantages for hardware realisations. Not only is it one of the simpliest and cheapest ways to tie processors together, but it is also an ideal interconnection scheme if one wants to keep the structure flexible and modular. On the other hand, the main disadvantage of the time-shared bus is the limited bandwidth. Especially in image processing, this can be very troublesome. This paper will try to explore the possibilities of a time-shared bus in this field of application. A process is divided into a set of processors, each with a specified number of inputs and outputs. Furthermore, each processor is determined by a set of delays between these inputs and outputs. The model is characterised by four parameters: - the delays per processor - the constancy of the delays - the use or no use of internal memory in a processor - the fact whether the operations on a processor are pipelined or not. These parameters influence the complexity and the effectiveness of the hardware. Using them to classify different hardware approaches, we develop a hardware definition of a time-shared bus, that optimises the use of that bus in order to diminish the disadvantage of the limited bandwidth. An example of a process, constructed by putting processors in pipeline and/or in parallel, illustrate the possibilities.