4 January 1986 Digital Beamforming Radar VLSI Processor
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Proceedings Volume 0564, Real-Time Signal Processing VIII; (1986); doi: 10.1117/12.949705
Event: 29th Annual Technical Symposium, 1985, San Diego, United States
Abstract
A radar digital beamformer VLSI architecture is defined which provides the very high-throughput data flow in a modular failure-tolerant structure. A number of VHSIC/VLSI chip implementation approaches were evaluated and tradeoff curves are presented here. The results indicate affordability of radar elemental beamformers including large two-dimensional arrays.
© (1986) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
J. Peter Costello, "Digital Beamforming Radar VLSI Processor", Proc. SPIE 0564, Real-Time Signal Processing VIII, (4 January 1986); doi: 10.1117/12.949705; https://doi.org/10.1117/12.949705
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KEYWORDS
Phased arrays

Radar

Very large scale integration

Receivers

Signal processing

Data communications

Voltage controlled current source

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