A VLSI Based Systolic Architecture For Fast Gaussian Convolution

A . Giordano; M. Maresca; G. Sandini; T. Vernazza

doi:10.1117/12.950818

11 December 1985 A VLSI Based Systolic Architecture For Fast Gaussian Convolution

A . Giordano, M. Maresca, G. Sandini, T. Vernazza

Proceedings Volume 0579, Intelligent Robots and Computer Vision IV; (1985) https://doi.org/10.1117/12.950818
Event: 1985 Cambridge Symposium, 1985, Cambridge, United States

Abstract

The paper deals with an algorithm driven architecture devoted to fast edge detection. The architecture has been specifically designed to process large convolution masks in a pyramidal (multiresolution) scheme. The basic element of the convolution board is a pro-grammable VLSI component. Several identical components can be connected in a virtually systolic structure in order to achieve the desired throughput rate. A distinctive feature of the system is the multiple-resolution capability of the convolver board. The number of convolver boards hosted by a multiple bus vision machine can be selected to achieve a parallel multiple-resolution operation. The main application of the proposed architecture is for fast edge detection based on the extraction of the zero-crossings of Gaussian filtered images. The paper is divided into two sections: In the first one results of numerical simulations are presented showing the accuracy of this edge detection technique applied on convolved images in a pyramidal structure while in the second, one the systolic architecture implementing the algorithm is presented.

Citation Download Citation

A . Giordano, M. Maresca, G. Sandini, and T. Vernazza "A VLSI Based Systolic Architecture For Fast Gaussian Convolution", Proc. SPIE 0579, Intelligent Robots and Computer Vision IV, (11 December 1985); https://doi.org/10.1117/12.950818

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